Timed yielding in vmm_halt to avoid pegging CPU

[palacios.git] / palacios / src / palacios / vmm_halt.c

diff --git a/palacios/src/palacios/vmm_halt.c b/palacios/src/palacios/vmm_halt.c
index 5015046..60ca74b 100644 (file)
--- a/palacios/src/palacios/vmm_halt.c
+++ b/palacios/src/palacios/vmm_halt.c
@@ -20,14 +20,16 @@
 
 #include <palacios/vmm_halt.h>
 #include <palacios/vmm_intr.h>
+#include <palacios/vmm_lowlevel.h> 
 
-
-#ifndef CONFIG_DEBUG_HALT
+#ifndef V3_CONFIG_DEBUG_HALT
 #undef PrintDebug
 #define PrintDebug(fmt, args...)
 #endif
 
 
+#define YIELD_TIME_USEC 1000
+
 
 //
 // This should trigger a #GP if cpl != 0, otherwise, yield to host
@@ -38,27 +40,30 @@ int v3_handle_halt(struct guest_info * info) {
     if (info->cpl != 0) { 
        v3_raise_exception(info, GPF_EXCEPTION);
     } else {
-       uint64_t yield_start = 0;
-       
        PrintDebug("CPU Yield\n");
 
-       while (!v3_intr_pending(info)) {
-           rdtscll(yield_start);
-           v3_yield(info);
-           
-           v3_update_time(info, yield_start - info->time_state.cached_host_tsc);
-           
-           rdtscll(info->time_state.cached_host_tsc);
-           
+       while (!v3_intr_pending(info) && (info->vm_info->run_state == VM_RUNNING)) {
+            uint64_t t, cycles;
+           /* Yield, allowing time to pass while yielded */
+           t = v3_get_host_time(&info->time_state);
+           v3_yield_timed(info,YIELD_TIME_USEC);
+           cycles = v3_get_host_time(&info->time_state) - t;
+           v3_advance_time(info, &cycles);
+
+           v3_update_timers(info);
+           
            /* At this point, we either have some combination of 
               interrupts, including perhaps a timer interrupt, or 
               no interrupt.
            */
            if (!v3_intr_pending(info)) {
                /* if no interrupt, then we do halt */
-               asm("hlt");
+               /* asm("hlt"); */
            }
+
        }
+
+       /* V3_Print("palacios: done with halt\n"); */
        
        info->rip += 1;
     }