}
+static inline int invalidate_addr_32pae(struct guest_info * info, addr_t inv_addr) {
+ pdpe32pae_t * pdpe = NULL;
+ pde32pae_t * pde = NULL;
+ pte32pae_t * pte = NULL;
+
+
+ // TODO:
+ // Call INVLPGA
+
+ // clear the page table entry
+ int pdpe_index = PDPE32PAE_INDEX(inv_addr);
+ int pde_index = PDE32PAE_INDEX(inv_addr);
+ int pte_index = PTE32PAE_INDEX(inv_addr);
+
+
+ // Lookup the correct PDE address based on the PAGING MODE
+ if (info->shdw_pg_mode == SHADOW_PAGING) {
+ pdpe = CR3_TO_PDPE32PAE_VA(info->ctrl_regs.cr3);
+ } else {
+ pdpe = CR3_TO_PDPE32PAE_VA(info->direct_map_pt);
+ }
+
+
+ if (pdpe[pdpe_index].present == 0) {
+ return 0;
+ }
+
+ pde = V3_VAddr((void*)BASE_TO_PAGE_ADDR(pdpe[pdpe_index].pd_base_addr));
+
+ if (pde[pde_index].present == 0) {
+ return 0;
+ } else if (pde[pde_index].large_page) {
+ pde[pde_index].present = 0;
+ return 0;
+ }
+
+ pte = V3_VAddr((void*)BASE_TO_PAGE_ADDR(pde[pde_index].pt_base_addr));
+
+ pte[pte_index].present = 0;
+
+ return 0;
+}
+
+
+
#endif