#include <palacios/vmm_rbtree.h>
#include <palacios/vmm_barrier.h>
+#ifdef V3_CONFIG_CHECKPOINT
+#include <palacios/vmm_checkpoint.h>
+#endif
#include <palacios/vmm_direct_paging.h>
ctrl_area->instrs.HLT = 1;
-#ifdef V3_CONFIG_TIME_VIRTUALIZE_TSC
- ctrl_area->instrs.RDTSC = 1;
- ctrl_area->svm_instrs.RDTSCP = 1;
-#endif
+ /* Set at VMM launch as needed */
+ ctrl_area->instrs.RDTSC = 0;
+ ctrl_area->svm_instrs.RDTSCP = 0;
// guest_state->cr0 = 0x00000001; // PE
ctrl_area->instrs.NMI = 1;
ctrl_area->instrs.SMI = 0; // allow SMIs to run in guest
ctrl_area->instrs.INIT = 1;
- ctrl_area->instrs.PAUSE = 1;
+ // ctrl_area->instrs.PAUSE = 1;
ctrl_area->instrs.shutdown_evts = 1;
&v3_handle_vm_cr_read,
&v3_handle_vm_cr_write,
core);
+
+
+ {
+#define INT_PENDING_AMD_MSR 0xc0010055
+
+ v3_hook_msr(core->vm_info, IA32_STAR_MSR, NULL, NULL, NULL);
+ v3_hook_msr(core->vm_info, IA32_LSTAR_MSR, NULL, NULL, NULL);
+ v3_hook_msr(core->vm_info, IA32_FMASK_MSR, NULL, NULL, NULL);
+ v3_hook_msr(core->vm_info, IA32_KERN_GS_BASE_MSR, NULL, NULL, NULL);
+ v3_hook_msr(core->vm_info, IA32_CSTAR_MSR, NULL, NULL, NULL);
+
+ v3_hook_msr(core->vm_info, SYSENTER_CS_MSR, NULL, NULL, NULL);
+ v3_hook_msr(core->vm_info, SYSENTER_ESP_MSR, NULL, NULL, NULL);
+ v3_hook_msr(core->vm_info, SYSENTER_EIP_MSR, NULL, NULL, NULL);
+
+
+ v3_hook_msr(core->vm_info, FS_BASE_MSR, NULL, NULL, NULL);
+ v3_hook_msr(core->vm_info, GS_BASE_MSR, NULL, NULL, NULL);
+
+ // Passthrough read operations are ok.
+ v3_hook_msr(core->vm_info, INT_PENDING_AMD_MSR, NULL, v3_msr_unhandled_write, NULL);
+ }
}
}
+#ifdef V3_CONFIG_CHECKPOINT
+int v3_svm_save_core(struct guest_info * core, void * ctx){
+
+ v3_chkpt_save_8(ctx, "cpl", &(core->cpl));
+ v3_chkpt_save(ctx, "vmcb_data", PAGE_SIZE, core->vmm_data);
+
+ return 0;
+}
+
+int v3_svm_load_core(struct guest_info * core, void * ctx){
+
+ v3_chkpt_load_8(ctx, "cpl", &(core->cpl));
+
+ if (v3_chkpt_load(ctx, "vmcb_data", PAGE_SIZE, core->vmm_data) == -1) {
+ return -1;
+ }
+
+ return 0;
+}
+#endif
+
static int update_irq_exit_state(struct guest_info * info) {
vmcb_ctrl_t * guest_ctrl = GET_VMCB_CTRL_AREA((vmcb_t*)(info->vmm_data));
return 0;
}
+int
+v3_svm_config_tsc_virtualization(struct guest_info * info) {
+ vmcb_ctrl_t * ctrl_area = GET_VMCB_CTRL_AREA((vmcb_t*)(info->vmm_data));
+
+ if (info->time_state.flags & VM_TIME_TRAP_RDTSC) {
+ ctrl_area->instrs.RDTSC = 1;
+ ctrl_area->svm_instrs.RDTSCP = 1;
+ } else {
+ ctrl_area->instrs.RDTSC = 0;
+ ctrl_area->svm_instrs.RDTSCP = 0;
+ ctrl_area->TSC_OFFSET = v3_tsc_host_offset(&info->time_state);
+ }
+ return 0;
+}
/*
* CAUTION and DANGER!!!
vmcb_ctrl_t * guest_ctrl = GET_VMCB_CTRL_AREA((vmcb_t*)(info->vmm_data));
vmcb_saved_state_t * guest_state = GET_VMCB_SAVE_STATE_AREA((vmcb_t*)(info->vmm_data));
addr_t exit_code = 0, exit_info1 = 0, exit_info2 = 0;
+ uint64_t guest_cycles = 0;
// Conditionally yield the CPU if the timeslice has expired
v3_yield_cond(info);
- // Perform any additional yielding needed for time adjustment
- v3_adjust_time(info);
+ // Update timer devices after being in the VM before doing
+ // IRQ updates, so that any interrupts they raise get seen
+ // immediately.
+ v3_advance_time(info, NULL);
+ v3_update_timers(info);
// disable global interrupts for vm state transition
v3_clgi();
- // Update timer devices after being in the VM, with interupts
- // disabled, but before doing IRQ updates, so that any interrupts they
- //raise get seen immediately.
- v3_update_timers(info);
-
// Synchronize the guest state to the VMCB
guest_state->cr0 = info->ctrl_regs.cr0;
guest_state->cr2 = info->ctrl_regs.cr2;
guest_state->rflags = info->ctrl_regs.rflags;
guest_state->efer = info->ctrl_regs.efer;
+ /* Synchronize MSRs */
+ guest_state->star = info->msrs.star;
+ guest_state->lstar = info->msrs.lstar;
+ guest_state->sfmask = info->msrs.sfmask;
+ guest_state->KernelGsBase = info->msrs.kern_gs_base;
+
guest_state->cpl = info->cpl;
v3_set_vmcb_segments((vmcb_t*)(info->vmm_data), &(info->segments));
}
#endif
- v3_time_enter_vm(info);
- guest_ctrl->TSC_OFFSET = v3_tsc_host_offset(&info->time_state);
+ v3_svm_config_tsc_virtualization(info);
//V3_Print("Calling v3_svm_launch\n");
+ {
+ uint64_t entry_tsc = 0;
+ uint64_t exit_tsc = 0;
+
+ rdtscll(entry_tsc);
+
+ v3_svm_launch((vmcb_t *)V3_PAddr(info->vmm_data), &(info->vm_regs), (vmcb_t *)host_vmcbs[V3_Get_CPU()]);
+
+ rdtscll(exit_tsc);
+
+ guest_cycles = exit_tsc - entry_tsc;
+ }
- v3_svm_launch((vmcb_t *)V3_PAddr(info->vmm_data), &(info->vm_regs), (vmcb_t *)host_vmcbs[V3_Get_CPU()]);
//V3_Print("SVM Returned: Exit Code: %x, guest_rip=%lx\n", (uint32_t)(guest_ctrl->exit_code), (unsigned long)guest_state->rip);
v3_last_exit = (uint32_t)(guest_ctrl->exit_code);
- // Immediate exit from VM time bookkeeping
- v3_time_exit_vm(info);
+ v3_advance_time(info, &guest_cycles);
info->num_exits++;
info->ctrl_regs.rflags = guest_state->rflags;
info->ctrl_regs.efer = guest_state->efer;
+ /* Synchronize MSRs */
+ info->msrs.star = guest_state->star;
+ info->msrs.lstar = guest_state->lstar;
+ info->msrs.sfmask = guest_state->sfmask;
+ info->msrs.kern_gs_base = guest_state->KernelGsBase;
+
v3_get_vmcb_segments((vmcb_t*)(info->vmm_data), &(info->segments));
info->cpu_mode = v3_get_vm_cpu_mode(info);
info->mem_mode = v3_get_vm_mem_mode(info);
// Conditionally yield the CPU if the timeslice has expired
v3_yield_cond(info);
+ // This update timers is for time-dependent handlers
+ // if we're slaved to host time
+ v3_advance_time(info, NULL);
+ v3_update_timers(info);
+
{
int ret = v3_handle_svm_exit(info, exit_code, exit_info1, exit_info2);
}
}
+ if (info->timeouts.timeout_active) {
+ /* Check to see if any timeouts have expired */
+ v3_handle_timeouts(info, guest_cycles);
+ }
+
return 0;
}
if (info->vcpu_id == 0) {
info->core_run_state = CORE_RUNNING;
- info->vm_info->run_state = VM_RUNNING;
} else {
PrintDebug("SVM core %u (on %u): Waiting for core initialization\n", info->vcpu_id, info->pcpu_id);
while (info->core_run_state == CORE_STOPPED) {
+
+ if (info->vm_info->run_state == VM_STOPPED) {
+ // The VM was stopped before this core was initialized.
+ return 0;
+ }
+
v3_yield(info);
//PrintDebug("SVM core %u: still waiting for INIT\n", info->vcpu_id);
}
PrintDebug("SVM core %u(on %u) initialized\n", info->vcpu_id, info->pcpu_id);
+
+ // We'll be paranoid about race conditions here
+ v3_wait_at_barrier(info);
}
PrintDebug("SVM core %u(on %u): I am starting at CS=0x%x (base=0x%p, limit=0x%x), RIP=0x%p\n",
