union {
uint16_t val;
struct {
- uint8_t rx_ok : 1;
- uint8_t rx_bad_align : 1;
- uint8_t rx_crc_err : 1;
- uint8_t rx_too_long : 1;
- uint8_t rx_runt : 1;
- uint8_t rx_bad_sym : 1;
- uint8_t reserved : 7;
- uint8_t rx_brdcast : 1;
- uint8_t rx_phys : 1;
- uint8_t rx_multi : 1;
+ uint16_t rx_ok : 1;
+ uint16_t rx_bad_align : 1;
+ uint16_t rx_crc_err : 1;
+ uint16_t rx_too_long : 1;
+ uint16_t rx_runt : 1;
+ uint16_t rx_bad_sym : 1;
+ uint16_t reserved : 7;
+ uint16_t rx_brdcast : 1;
+ uint16_t rx_phys : 1;
+ uint16_t rx_multi : 1;
} __attribute__((packed));
} __attribute__((packed));
} __attribute__((packed));
union {
uint16_t val;
struct {
- uint8_t rx_ok :1;
- uint8_t rx_err : 1;
- uint8_t tx_ok : 1;
- uint8_t tx_err : 1;
- uint8_t rx_ovw : 1;
- uint8_t pun_linkchg : 1;
- uint8_t rx_fifo_ovw : 1;
- uint8_t reservd: 6;
- uint8_t lenchg :1;
- uint8_t timeout :1;
- uint8_t syserr :1;
+ uint16_t rx_ok :1;
+ uint16_t rx_err : 1;
+ uint16_t tx_ok : 1;
+ uint16_t tx_err : 1;
+ uint16_t rx_ovw : 1;
+ uint16_t pun_linkchg : 1;
+ uint16_t rx_fifo_ovw : 1;
+ uint16_t reservd: 6;
+ uint16_t lenchg :1;
+ uint16_t timeout :1;
+ uint16_t syserr :1;
} __attribute__((packed));
} __attribute__((packed));
} __attribute__((packed));
if(isr & 0xffff){
v3_pci_raise_irq(nic_state->pci_bus, 0, nic_state->pci_dev);
- nic_state->statistic.interrupts ++;
+ nic_state->statistic.tx_interrupts ++;
}
}
}
bars[0].type = PCI_BAR_IO;
- bars[0].default_base_port = 0xc100;
+ bars[0].default_base_port = -1;
bars[0].num_ports = 0x100;
bars[0].io_read = rtl8139_ioport_read;
ops->recv = rtl8139_rx;
ops->poll = NULL;
- ops->start_tx = NULL;
- ops->stop_tx = NULL;
- ops->frontend_data = nic_state;
- memcpy(ops->fnt_mac, nic_state->mac, ETH_ALEN);
+ ops->config.frontend_data = nic_state;
+ ops->config.fnt_mac = nic_state->mac;
return 0;
}