break;
}
+ case PCI_BAR_MEM32: {
+ v3_unhook_mem(pci->vm_dev->vm, (addr_t)(bar->val));
+
+ if (bar->mem_read) {
+ v3_hook_full_mem(pci->vm_dev->vm, PCI_MEM32_BASE(new_val),
+ PCI_MEM32_BASE(new_val) + (bar->num_pages * PAGE_SIZE_4KB),
+ bar->mem_read, bar->mem_write, pci->vm_dev);
+ } else {
+ PrintError("Write hooks not supported for PCI\n");
+ return -1;
+ }
+
+ bar->val = new_val;
+
+ break;
+ }
case PCI_BAR_NONE: {
PrintDebug("Reprogramming an unsupported BAR register (Dev=%s) (bar=%d) (val=%x)\n",
pci->name, bar_num, new_val);
-static int pci_deinit_device(struct vm_device * dev) {
+static int pci_free(struct vm_device * dev) {
int i = 0;
for (i = 0; i < 4; i++){
-static int pci_init_device(struct vm_device * dev) {
- struct pci_internal * pci_state = (struct pci_internal *)dev->private_data;;
+
+static struct v3_device_ops dev_ops = {
+ .free = pci_free,
+ .reset = pci_reset_device,
+ .start = pci_start_device,
+ .stop = pci_stop_device,
+};
+
+
+
+
+static int pci_init(struct guest_info * vm, void * cfg_data) {
+ struct pci_internal * pci_state = V3_Malloc(sizeof(struct pci_internal));
int i = 0;
- PrintDebug("pci: init_device\n");
+ PrintDebug("PCI internal at %p\n",(void *)pci_state);
+
+ struct vm_device * dev = v3_allocate_device("PCI", &dev_ops, pci_state);
+
+ if (v3_attach_device(vm, dev) == -1) {
+ PrintError("Could not attach device %s\n", "PCI");
+ return -1;
+ }
- // JRL: Fix this....
- // dev->vm->pci = dev; //should be in vmm_config.c
pci_state->addr_reg.val = 0;
}
-static struct vm_device_ops dev_ops = {
- .init = pci_init_device,
- .deinit = pci_deinit_device,
- .reset = pci_reset_device,
- .start = pci_start_device,
- .stop = pci_stop_device,
-};
-
-
-struct vm_device * v3_create_pci() {
- struct pci_internal * pci_state = V3_Malloc(sizeof(struct pci_internal));
-
- PrintDebug("PCI internal at %p\n",(void *)pci_state);
-
- struct vm_device * device = v3_create_device("PCI", &dev_ops, pci_state);
-
- return device;
-}
-
+device_register("PCI", pci_init)
static inline int init_bars(struct pci_device * pci_dev) {
pci_dev->bar[i].default_base_port = bars[i].default_base_port;
pci_dev->bar[i].io_read = bars[i].io_read;
pci_dev->bar[i].io_write = bars[i].io_write;
- } else {
+ } else if (pci_dev->bar[i].type == PCI_BAR_MEM32) {
pci_dev->bar[i].num_pages = bars[i].num_pages;
pci_dev->bar[i].default_base_addr = bars[i].default_base_addr;
pci_dev->bar[i].mem_read = bars[i].mem_read;
pci_dev->bar[i].mem_write = bars[i].mem_write;
+ } else {
+ pci_dev->bar[i].num_pages = 0;
+ pci_dev->bar[i].default_base_addr = 0;
+ pci_dev->bar[i].mem_read = NULL;
+ pci_dev->bar[i].mem_write = NULL;
}
}