#include <devices/apic.h>
#include <palacios/vm_guest.h>
-#ifndef CONFIG_DEBUG_IO_APIC
+#ifndef V3_CONFIG_DEBUG_IO_APIC
#undef PrintDebug
#define PrintDebug(fmt, args...)
#endif
struct io_apic_state * ioapic = (struct io_apic_state *)(private_data);
struct redir_tbl_entry * irq_entry = NULL;
+ if (irq==0) {
+ // IRQ 0 being raised, in the Palacios context, means the PIT
+ // However, the convention is that it is the PIC that is connected
+ // to PIN 0 of the IOAPIC and the PIT is connected to pin 2
+ // Hence we convert this to the relvant pin. In the future,
+ // the PIC may signal to the IOAPIC in a different path.
+ // Yes, this is kind of hideous, but it is needed to have the
+ // PIT correctly show up via the IOAPIC
+ irq=2;
+ }
+
if (irq > 24) {
PrintDebug("ioapic %u: IRQ out of range of IO APIC\n", ioapic->ioapic_id.id);
return -1;
return 0;
}
+#ifdef V3_CONFIG_CHECKPOINT
+static int io_apic_save(struct v3_chkpt_ctx * ctx, void * private_data) {
+ struct io_apic_state * io_apic = (struct io_apic_state *)private_data;
+
+ V3_CHKPT_STD_SAVE(ctx, io_apic->base_addr);
+ V3_CHKPT_STD_SAVE(ctx, io_apic->index_reg);
+ V3_CHKPT_STD_SAVE(ctx, io_apic->ioapic_id);
+ V3_CHKPT_STD_SAVE(ctx, io_apic->ioapic_ver);
+ V3_CHKPT_STD_SAVE(ctx, io_apic->ioapic_arb_id);
+ V3_CHKPT_STD_SAVE(ctx, io_apic->redir_tbl);
+
+ return 0;
+}
+
+static int io_apic_load(struct v3_chkpt_ctx * ctx, void * private_data) {
+ struct io_apic_state * io_apic = (struct io_apic_state *)private_data;
+
+ V3_CHKPT_STD_LOAD(ctx, io_apic->base_addr);
+ V3_CHKPT_STD_LOAD(ctx, io_apic->index_reg);
+ V3_CHKPT_STD_LOAD(ctx, io_apic->ioapic_id);
+ V3_CHKPT_STD_LOAD(ctx, io_apic->ioapic_ver);
+ V3_CHKPT_STD_LOAD(ctx, io_apic->ioapic_arb_id);
+ V3_CHKPT_STD_LOAD(ctx, io_apic->redir_tbl);
+
+ return 0;
+}
+#endif
+
+
static struct v3_device_ops dev_ops = {
.free = (int (*)(void *))io_apic_free,
-
+#ifdef V3_CONFIG_CHECKPOINT
+ .save = io_apic_save,
+ .load = io_apic_load
+#endif
};