#define EXT_INT_LOC_VEC_TBL_OFFSET2 0x520 // 0x500 - 0x530
#define EXT_INT_LOC_VEC_TBL_OFFSET3 0x530 // 0x500 - 0x530
-
-
-
-
struct apic_msr {
union {
uint64_t value;
return 1;
}
- return should_deliver_cluster_ipi(dst_core, dst_apic, mda);
+ return should_deliver_flat_ipi(dst_core, dst_apic, mda);
} else if (dst_apic->dst_fmt.model == 0x0) {
if (mda == 0xff) {
return 1;
}
- return should_deliver_flat_ipi(dst_core, dst_apic, mda);
+ return should_deliver_cluster_ipi(dst_core, dst_apic, mda);
} else {
PrintError("apic %u core %u: invalid destination format register value 0x%x for logical mode delivery.\n",
dst_apic->lapic_id.val, dst_core->cpu_id, dst_apic->dst_fmt.model);
icr->dst,
icr->val);
-
switch (icr->dst_shorthand) {
case 0: // no shorthand
PrintDebug("apic %u: core %u: at %p and priv_data is at %p\n",
apic->lapic_id.val, core->cpu_id, apic, priv_data);
- PrintDebug("Write to address space (%p) (val=%x)\n",
- (void *)guest_addr, *(uint32_t *)src);
+ PrintDebug("apic %u: core %u: write to address space (%p) (val=%x)\n",
+ apic->lapic_id.val, core->cpu_id, (void *)guest_addr, *(uint32_t *)src);
if (msr->apic_enable == 0) {
PrintError("apic %u: core %u: Write to APIC address space with disabled APIC, apic msr=0x%llx\n",