icr->dst,
icr->val);
-
switch (icr->dst_shorthand) {
case 0: // no shorthand
PrintDebug("apic %u: core %u: at %p and priv_data is at %p\n",
apic->lapic_id.val, core->cpu_id, apic, priv_data);
- PrintDebug("Write to address space (%p) (val=%x)\n",
- (void *)guest_addr, *(uint32_t *)src);
+ PrintDebug("apic %u: core %u: write to address space (%p) (val=%x)\n",
+ apic->lapic_id.val, core->cpu_id, (void *)guest_addr, *(uint32_t *)src);
if (msr->apic_enable == 0) {
PrintError("apic %u: core %u: Write to APIC address space with disabled APIC, apic msr=0x%llx\n",
};
-static struct vm_timer_ops timer_ops = {
+static struct v3_timer_ops timer_ops = {
.update_timer = apic_update_time,
};