#define EXT_INT_LOC_VEC_TBL_OFFSET2 0x520 // 0x500 - 0x530
#define EXT_INT_LOC_VEC_TBL_OFFSET3 0x530 // 0x500 - 0x530
-
-
-
-
struct apic_msr {
union {
uint64_t value;
-typedef enum {INIT_ST, SIPI, STARTED} ipi_state_t;
+typedef enum {INIT_ST,
+ SIPI,
+ STARTED} ipi_state_t;
struct apic_dev_state;
struct guest_info * core;
+ struct v3_timer * timer;
+
uint32_t eoi;
v3_lock_t lock;
if (irq_num <= 15) {
- PrintError("apic %u: core ?: Attempting to raise an invalid interrupt: %d\n", apic->lapic_id.val,irq_num);
+ PrintError("apic %u: core %d: Attempting to raise an invalid interrupt: %d\n",
+ apic->lapic_id.val, apic->core->cpu_id, irq_num);
return -1;
}
- PrintDebug("apic %u: core ?: Raising APIC IRQ %d\n", apic->lapic_id.val, irq_num);
+ PrintDebug("apic %u: core %d: Raising APIC IRQ %d\n", apic->lapic_id.val, apic->core->cpu_id, irq_num);
if (*req_location & flag) {
- //V3_Print("Interrupts coallescing\n");
+ PrintDebug("Interrupt %d coallescing\n", irq_num);
}
if (*en_location & flag) {
*req_location |= flag;
} else {
- PrintDebug("apic %u: core ?: Interrupt not enabled... %.2x\n",
- apic->lapic_id.val, *en_location);
+ PrintDebug("apic %u: core %d: Interrupt not enabled... %.2x\n",
+ apic->lapic_id.val, apic->core->cpu_id,*en_location);
return 0;
}
return 1;
}
- return should_deliver_cluster_ipi(dst_core, dst_apic, mda);
+ return should_deliver_flat_ipi(dst_core, dst_apic, mda);
} else if (dst_apic->dst_fmt.model == 0x0) {
if (mda == 0xff) {
return 1;
}
- return should_deliver_flat_ipi(dst_core, dst_apic, mda);
+ return should_deliver_cluster_ipi(dst_core, dst_apic, mda);
} else {
PrintError("apic %u core %u: invalid destination format register value 0x%x for logical mode delivery.\n",
dst_apic->lapic_id.val, dst_core->cpu_id, dst_apic->dst_fmt.model);
case 0: //fixed
case 1: // lowest priority
- PrintDebug(" delivering IRQ to core %u\n", dst_core->cpu_id);
+ PrintDebug("delivering IRQ %d to core %u\n", vector, dst_core->cpu_id);
activate_apic_irq(dst_apic, vector);
// Sanity check
if (dst_apic->ipi_state != INIT_ST) {
PrintError(" Warning: core %u is not in INIT state (mode = %d), ignored\n",
- dst_core->cpu_id, dst_core->cpu_mode);
+ dst_core->cpu_id, dst_apic->ipi_state);
// Only a warning, since INIT INIT SIPI is common
break;
}
// Sanity check
if (dst_apic->ipi_state != SIPI) {
PrintError(" core %u is not in SIPI state (mode = %d), ignored!\n",
- dst_core->cpu_id, dst_core->cpu_mode);
+ dst_core->cpu_id, dst_apic->ipi_state);
break;
}
struct int_cmd_reg * icr) {
struct apic_state * dest_apic = NULL;
- PrintDebug("route_ipi: src_apic=%p, icr_data=%x",
- src_apic, icr_val);
+ PrintDebug("route_ipi: src_apic=%p, icr_data=%p\n",
+ src_apic, (void *)(addr_t)icr->val);
if ((icr->dst_mode == 0) && (icr->dst >= apic_dev->num_apics)) {
icr->dst,
icr->val);
-
switch (icr->dst_shorthand) {
case 0: // no shorthand
}
} else {
// logical delivery
- PrintError("icc_bus: use of logical delivery in self is not yet supported.\n");
+ PrintError("use of logical delivery in self is not yet supported.\n");
return -1;
}
break;
PrintDebug("apic %u: core %u: at %p and priv_data is at %p\n",
apic->lapic_id.val, core->cpu_id, apic, priv_data);
- PrintDebug("Write to address space (%p) (val=%x)\n",
- (void *)guest_addr, *(uint32_t *)src);
+ PrintDebug("apic %u: core %u: write to address space (%p) (val=%x)\n",
+ apic->lapic_id.val, core->cpu_id, (void *)guest_addr, *(uint32_t *)src);
if (msr->apic_enable == 0) {
PrintError("apic %u: core %u: Write to APIC address space with disabled APIC, apic msr=0x%llx\n",
tmp_icr.dst = ipi->dst;
- route_ipi(apic_dev, NULL, &tmp_icr);
- return -1;
+ return route_ipi(apic_dev, NULL, &tmp_icr);
}
};
-static struct vm_timer_ops timer_ops = {
+static struct v3_timer_ops timer_ops = {
.update_timer = apic_update_time,
};
static int apic_free(struct vm_device * dev) {
+ struct apic_dev_state * apic_dev = (struct apic_dev_state *)dev->private_data;
+ int i = 0;
+
+ for (i = 0; i < dev->vm->num_cores; i++) {
+ struct apic_state * apic = &(apic_dev->apics[i]);
+ struct guest_info * core = &(dev->vm->cores[i]);
+
+
+ // unregister intr controller
- /* TODO: This should crosscall to force an unhook on each CPU */
+ if (apic->timer) {
+ v3_remove_timer(core, apic->timer);
+ }
- // struct apic_state * apic = (struct apic_state *)dev->private_data;
+ // unhook memory
+
+ }
v3_unhook_msr(dev->vm, BASE_ADDR_MSR);
+ V3_Free(apic_dev);
return 0;
}
if (v3_attach_device(vm, dev) == -1) {
PrintError("apic: Could not attach device %s\n", dev_id);
+ V3_Free(apic_dev);
return -1;
}
v3_register_intr_controller(core, &intr_ops, apic_dev);
- v3_add_timer(core, &timer_ops, apic_dev);
+ apic->timer = v3_add_timer(core, &timer_ops, apic_dev);
+
+ if (apic->timer == NULL) {
+ PrintError("APIC: Failed to attach timer to core %d\n", i);
+ v3_detach_device(dev);
+ return -1;
+ }
v3_hook_full_mem(vm, core->cpu_id, apic->base_addr, apic->base_addr + PAGE_SIZE_4KB, apic_read, apic_write, apic_dev);