struct pic_internal * state = (struct pic_internal*)dev->private_data;
uchar_t cw = *(uchar_t *)src;
+ PrintDebug("8259 PIC: Write master port 1 with 0x%x\n",cw);
+
if (length != 1) {
PrintError("8259 PIC: Invalid Write length (wr_Master1)\n");
return -1;
}
if (IS_ICW1(cw)) {
+
+ PrintDebug("8259 PIC: Setting ICW1 = %x (wr_Master1)\n", cw);
+
state->master_icw1 = cw;
state->master_state = ICW2;
// handle the EOI here
struct ocw2 * cw2 = (struct ocw2*)&cw;
+ PrintDebug("8259 PIC: Handling OCW2 = %x (wr_Master1)\n", cw);
if ((cw2->EOI) && (!cw2->R) && (cw2->SL)) {
// specific EOI;
state->master_ocw2 = cw;
} else if (IS_OCW3(cw)) {
+ PrintDebug("8259 PIC: Handling OCW3 = %x (wr_Master1)\n", cw);
state->master_ocw3 = cw;
} else {
PrintError("8259 PIC: Invalid OCW to PIC (wr_Master1)\n");
struct pic_internal * state = (struct pic_internal*)dev->private_data;
uchar_t cw = *(uchar_t *)src;
+ PrintDebug("8259 PIC: Write master port 2 with 0x%x\n",cw);
+
if (length != 1) {
PrintError("8259 PIC: Invalid Write length (wr_Master2)\n");
return -1;
} else if (state->master_state == ICW3) {
struct icw1 * cw1 = (struct icw1 *)&(state->master_icw1);
+ PrintDebug("8259 PIC: Setting ICW3 = %x (wr_Master2)\n", cw);
+
state->master_icw3 = cw;
if (cw1->ic4 == 1) {
}
} else if (state->master_state == ICW4) {
+ PrintDebug("8259 PIC: Setting ICW4 = %x (wr_Master2)\n", cw);
state->master_icw4 = cw;
state->master_state = READY;
} else if (state->master_state == READY) {
+ PrintDebug("8259 PIC: Setting IMR = %x (wr_Master2)\n", cw);
state->master_imr = cw;
} else {
// error
struct pic_internal * state = (struct pic_internal*)dev->private_data;
uchar_t cw = *(uchar_t *)src;
+ PrintDebug("8259 PIC: Write slave port 1 with 0x%x\n",cw);
+
if (length != 1) {
// error
PrintError("8259 PIC: Invalid Write length (wr_Slave1)\n");
}
if (IS_ICW1(cw)) {
+ PrintDebug("8259 PIC: Setting ICW1 = %x (wr_Slave1)\n", cw);
state->slave_icw1 = cw;
state->slave_state = ICW2;
} else if (state->slave_state == READY) {
if (IS_OCW2(cw)) {
// handle the EOI here
struct ocw2 * cw2 = (struct ocw2 *)&cw;
+
+ PrintDebug("8259 PIC: Setting OCW2 = %x (wr_Slave1)\n", cw);
if ((cw2->EOI) && (!cw2->R) && (cw2->SL)) {
// specific EOI;
state->slave_ocw2 = cw;
} else if (IS_OCW3(cw)) {
// Basically sets the IRR/ISR read flag
+ PrintDebug("8259 PIC: Setting OCW3 = %x (wr_Slave1)\n", cw);
state->slave_ocw3 = cw;
} else {
PrintError("8259 PIC: Invalid command work (wr_Slave1)\n");
struct pic_internal * state = (struct pic_internal*)dev->private_data;
uchar_t cw = *(uchar_t *)src;
+ PrintDebug("8259 PIC: Write slave port 2 with 0x%x\n",cw);
+
if (length != 1) {
PrintError("8259 PIC: Invalid write length (wr_Slave2)\n");
return -1;
if (state->slave_state == ICW2) {
struct icw1 * cw1 = (struct icw1 *)&(state->master_icw1);
+ PrintDebug("8259 PIC: Setting ICW2 = %x (wr_Slave2)\n", cw);
+
state->slave_icw2 = cw;
if (cw1->sngl == 0) {
} else if (state->slave_state == ICW3) {
struct icw1 * cw1 = (struct icw1 *)&(state->master_icw1);
+ PrintDebug("8259 PIC: Setting ICW3 = %x (wr_Slave2)\n", cw);
+
state->slave_icw3 = cw;
if (cw1->ic4 == 1) {
}
} else if (state->slave_state == ICW4) {
+ PrintDebug("8259 PIC: Setting ICW4 = %x (wr_Slave2)\n", cw);
state->slave_icw4 = cw;
state->slave_state = READY;
} else if (state->slave_state == READY) {
+ PrintDebug("8259 PIC: Setting IMR = %x (wr_Slave2)\n", cw);
state->slave_imr = cw;
} else {
PrintError("8259 PIC: Invalid State at write (wr_Slave2)\n");