return -1;
}
- v3_interrupt_cpu(vm, 0);
+ v3_interrupt_cpu(vm, 0, 0);
return 0;
}
for (i = 0; i < 16; i++) {
if (i <= 7) {
- if (((state->master_irr & ~(state->master_imr)) >> i) == 0x01) {
+ if (((state->master_irr & ~(state->master_imr)) >> i) & 0x01) {
//state->master_isr |= (0x1 << i);
// reset the irr
//state->master_irr &= ~(0x1 << i);
break;
}
} else {
- if (((state->slave_irr & ~(state->slave_imr)) >> (i - 8)) == 0x01) {
+ if (((state->slave_irr & ~(state->slave_imr)) >> (i - 8)) & 0x01) {
//state->slave_isr |= (0x1 << (i - 8));
//state->slave_irr &= ~(0x1 << (i - 8));
PrintDebug("8259 PIC: IRQ: %d, slave_icw2: %x\n", i, state->slave_icw2);
- irq= (i - 8) + state->slave_icw2;
+ irq = (i - 8) + state->slave_icw2;
break;
}
}
}
+#if 1
if ((i == 15) || (i == 6)) {
DumpPICState(state);
}
+#endif
if (i == 16) {
return -1;
} else {
+ PrintDebug("8259 PIC: get num is returning %d\n",irq);
return irq;
}
}
}
if (irq <= 7) {
- if (((state->master_irr & ~(state->master_imr)) >> irq) == 0x01) {
+ // This should always be true: See pic_get_intr_number
+ if (((state->master_irr & ~(state->master_imr)) >> irq) & 0x01) {
state->master_isr |= (0x1 << irq);
if (!(state->master_elcr & (0x1 << irq))) {
state->master_irr &= ~(0x1 << irq);
}
+ } else {
+ PrintDebug("8259 PIC: (master) Ignoring begin_irq for %d since I don't own it\n",irq);
}
+
} else {
- state->slave_isr |= (0x1 << (irq - 8));
+ // This should always be true: See pic_get_intr_number
+ if (((state->slave_irr & ~(state->slave_imr)) >> (irq - 8)) & 0x01) {
+ state->slave_isr |= (0x1 << (irq - 8));
+
+ if (!(state->slave_elcr & (0x1 << (irq - 8)))) {
+ state->slave_irr &= ~(0x1 << (irq - 8));
+ }
+ } else {
+ PrintDebug("8259 PIC: (slave) Ignoring begin_irq for %d since I don't own it\n",irq);
+ }
- if (!(state->slave_elcr & (0x1 << irq))) {
- state->slave_irr &= ~(0x1 << (irq - 8));
- }
}
return 0;
return -1;
}
+ v3_clear_pending_intr(core);
+
if (IS_ICW1(cw)) {
PrintDebug("8259 PIC: Setting ICW1 = %x (wr_Master1)\n", cw);
return -1;
}
+ v3_clear_pending_intr(core);
+
if (state->master_state == ICW2) {
struct icw1 * cw1 = (struct icw1 *)&(state->master_icw1);
PrintDebug("8259 PIC: Setting ICW2 = %x (wr_Master2)\n", cw);
state->master_icw2 = cw;
+
+
if (cw1->sngl == 0) {
state->master_state = ICW3;
} else if (cw1->ic4 == 1) {
state->master_state = READY;
}
+
+
} else if (state->master_state == ICW3) {
struct icw1 * cw1 = (struct icw1 *)&(state->master_icw1);
return -1;
}
+ v3_clear_pending_intr(core);
+
if (IS_ICW1(cw)) {
PrintDebug("8259 PIC: Setting ICW1 = %x (wr_Slave1)\n", cw);
state->slave_icw1 = cw;
return -1;
}
+ v3_clear_pending_intr(core);
+
+
if (state->slave_state == ICW2) {
struct icw1 * cw1 = (struct icw1 *)&(state->master_icw1);
static int pic_init(struct v3_vm_info * vm, v3_cfg_tree_t * cfg) {
struct pic_internal * state = NULL;
state = (struct pic_internal *)V3_Malloc(sizeof(struct pic_internal));
- char * name = v3_cfg_val(cfg, "name");
+ char * dev_id = v3_cfg_val(cfg, "ID");
// PIC is only usable in non-multicore environments
// just hardcode the core context
V3_ASSERT(state != NULL);
- struct vm_device * dev = v3_allocate_device(name, &dev_ops, state);
+ struct vm_device * dev = v3_allocate_device(dev_id, &dev_ops, state);
if (v3_attach_device(vm, dev) == -1) {
- PrintError("Could not attach device %s\n", name);
+ PrintError("Could not attach device %s\n", dev_id);
return -1;
}