#include <palacios/vmm_types.h>
#include <palacios/vmm.h>
#include <palacios/vmm_dev_mgr.h>
+#include <palacios/vm_guest.h>
-#ifndef CONFIG_DEBUG_PIC
+#ifndef V3_CONFIG_DEBUG_PIC
#undef PrintDebug
#define PrintDebug(fmt, args...)
#endif
pic_state_t master_state;
pic_state_t slave_state;
+
+ struct guest_info * core;
+
+
+ void * router_handle;
+ void * controller_handle;
};
return -1;
}
+#ifdef V3_CONFIG_MULTITHREAD_OS
v3_interrupt_cpu(vm, 0, 0);
+#endif
return 0;
}
+static int pic_free(struct pic_internal * state) {
+ struct guest_info * core = state->core;
+
+ v3_remove_intr_controller(core, state->controller_handle);
+ v3_remove_intr_router(core->vm_info, state->router_handle);
+
+ V3_Free(state);
+ return 0;
+}
+
+#ifdef V3_CONFIG_CHECKPOINT
+static int pic_save(struct v3_chkpt_ctx * ctx, void * private_data) {
+ struct pic_internal * pic = (struct pic_internal *)private_data;
+
+ V3_CHKPT_STD_SAVE(ctx, pic->master_irr);
+ V3_CHKPT_STD_SAVE(ctx, pic->slave_irr);
+
+ V3_CHKPT_STD_SAVE(ctx, pic->master_isr);
+ V3_CHKPT_STD_SAVE(ctx, pic->slave_isr);
+
+ V3_CHKPT_STD_SAVE(ctx, pic->master_elcr);
+ V3_CHKPT_STD_SAVE(ctx, pic->slave_elcr);
+ V3_CHKPT_STD_SAVE(ctx, pic->master_elcr_mask);
+ V3_CHKPT_STD_SAVE(ctx, pic->slave_elcr_mask);
+
+ V3_CHKPT_STD_SAVE(ctx, pic->master_icw1);
+ V3_CHKPT_STD_SAVE(ctx, pic->master_icw2);
+ V3_CHKPT_STD_SAVE(ctx, pic->master_icw3);
+ V3_CHKPT_STD_SAVE(ctx, pic->master_icw4);
+ V3_CHKPT_STD_SAVE(ctx, pic->slave_icw1);
+ V3_CHKPT_STD_SAVE(ctx, pic->slave_icw2);
+ V3_CHKPT_STD_SAVE(ctx, pic->slave_icw3);
+ V3_CHKPT_STD_SAVE(ctx, pic->slave_icw4);
-static int pic_free(struct vm_device * dev) {
+ V3_CHKPT_STD_SAVE(ctx, pic->master_imr);
+ V3_CHKPT_STD_SAVE(ctx, pic->slave_imr);
+ V3_CHKPT_STD_SAVE(ctx, pic->master_ocw2);
+ V3_CHKPT_STD_SAVE(ctx, pic->master_ocw3);
+ V3_CHKPT_STD_SAVE(ctx, pic->slave_ocw2);
+ V3_CHKPT_STD_SAVE(ctx, pic->slave_ocw3);
+
+ V3_CHKPT_STD_SAVE(ctx, pic->master_state);
+ V3_CHKPT_STD_SAVE(ctx, pic->slave_state);
+
+
return 0;
+
}
+static int pic_load(struct v3_chkpt_ctx * ctx, void * private_data) {
+ struct pic_internal * pic = (struct pic_internal *)private_data;
+ V3_CHKPT_STD_LOAD(ctx, pic->master_irr);
+ V3_CHKPT_STD_LOAD(ctx, pic->slave_irr);
+
+ V3_CHKPT_STD_LOAD(ctx, pic->master_isr);
+ V3_CHKPT_STD_LOAD(ctx, pic->slave_isr);
+ V3_CHKPT_STD_LOAD(ctx, pic->master_elcr);
+ V3_CHKPT_STD_LOAD(ctx, pic->slave_elcr);
+ V3_CHKPT_STD_LOAD(ctx, pic->master_elcr_mask);
+ V3_CHKPT_STD_LOAD(ctx, pic->slave_elcr_mask);
+ V3_CHKPT_STD_LOAD(ctx, pic->master_icw1);
+ V3_CHKPT_STD_LOAD(ctx, pic->master_icw2);
+ V3_CHKPT_STD_LOAD(ctx, pic->master_icw3);
+ V3_CHKPT_STD_LOAD(ctx, pic->master_icw4);
+ V3_CHKPT_STD_LOAD(ctx, pic->slave_icw1);
+ V3_CHKPT_STD_LOAD(ctx, pic->slave_icw2);
+ V3_CHKPT_STD_LOAD(ctx, pic->slave_icw3);
+ V3_CHKPT_STD_LOAD(ctx, pic->slave_icw4);
-static struct v3_device_ops dev_ops = {
- .free = pic_free,
+ V3_CHKPT_STD_LOAD(ctx, pic->master_imr);
+ V3_CHKPT_STD_LOAD(ctx, pic->slave_imr);
+ V3_CHKPT_STD_LOAD(ctx, pic->master_ocw2);
+ V3_CHKPT_STD_LOAD(ctx, pic->master_ocw3);
+ V3_CHKPT_STD_LOAD(ctx, pic->slave_ocw2);
+ V3_CHKPT_STD_LOAD(ctx, pic->slave_ocw3);
+
+ V3_CHKPT_STD_LOAD(ctx, pic->master_state);
+ V3_CHKPT_STD_LOAD(ctx, pic->slave_state);
+
+ return 0;
+}
+
+#endif
+
+
+static struct v3_device_ops dev_ops = {
+ .free = (int (*)(void *))pic_free,
+#ifdef V3_CONFIG_CHECKPOINT
+ .save = pic_save,
+ .load = pic_load
+#endif
};
-#include <palacios/vm_guest.h>
+
static int pic_init(struct v3_vm_info * vm, v3_cfg_tree_t * cfg) {
struct pic_internal * state = NULL;
// PIC is only usable in non-multicore environments
// just hardcode the core context
struct guest_info * core = &(vm->cores[0]);
+
+ state = (struct pic_internal *)V3_Malloc(sizeof(struct pic_internal));
V3_ASSERT(state != NULL);
-
- state = (struct pic_internal *)V3_Malloc(sizeof(struct pic_internal));
-
struct vm_device * dev = v3_add_device(vm, dev_id, &dev_ops, state);
return -1;
}
+ state->core = core;
- v3_register_intr_controller(core, &intr_ops, state);
- v3_register_intr_router(vm, &router_ops, state);
+ state->controller_handle = v3_register_intr_controller(core, &intr_ops, state);
+ state->router_handle = v3_register_intr_router(vm, &router_ops, state);
state->master_irr = 0;
state->master_isr = 0;