V3_OP_SETB, V3_OP_SETBE, V3_OP_SETL, V3_OP_SETLE, V3_OP_SETNB,
V3_OP_SETNBE, V3_OP_SETNL, V3_OP_SETNLE, V3_OP_SETNO, V3_OP_SETNP,
V3_OP_SETNS, V3_OP_SETNZ, V3_OP_SETO, V3_OP_SETP, V3_OP_SETS,
- V3_OP_SETZ, V3_OP_MOVS, V3_OP_STOS, V3_OP_MOVZX, V3_OP_MOVSX } v3_op_type_t;
+ V3_OP_SETZ, V3_OP_MOVS, V3_OP_STOS, V3_OP_MOVZX, V3_OP_MOVSX, V3_OP_INT } v3_op_type_t;
typedef enum {INVALID_OPERAND, REG_OPERAND, MEM_OPERAND, IMM_OPERAND} v3_operand_type_t;
addr_t operand;
uint_t size;
v3_operand_type_t type;
- uint8_t read : 1;
- uint8_t write : 1;
-};
+ uint8_t read : 1; // This operand value will be read by the instruction
+ uint8_t write : 1; // This operand value will be written to by the instruction
+} __attribute__((packed));
struct x86_prefixes {
- uint_t lock : 1; // 0xF0
- uint_t repne : 1; // 0xF2
- uint_t repnz : 1; // 0xF2
- uint_t rep : 1; // 0xF3
- uint_t repe : 1; // 0xF3
- uint_t repz : 1; // 0xF3
- uint_t cs_override : 1; // 0x2E
- uint_t ss_override : 1; // 0x36
- uint_t ds_override : 1; // 0x3E
- uint_t es_override : 1; // 0x26
- uint_t fs_override : 1; // 0x64
- uint_t gs_override : 1; // 0x65
- uint_t br_not_taken : 1; // 0x2E
- uint_t br_taken : 1; // 0x3E
- uint_t op_size : 1; // 0x66
- uint_t addr_size : 1; // 0x67
-
- uint_t rex : 1;
+ union {
+ uint32_t val;
+
+ struct {
+ uint32_t lock : 1; // 0xF0
+ uint32_t repne : 1; // 0xF2
+ uint32_t repnz : 1; // 0xF2
+ uint32_t rep : 1; // 0xF3
+ uint32_t repe : 1; // 0xF3
+ uint32_t repz : 1; // 0xF3
+ uint32_t cs_override : 1; // 0x2E
+ uint32_t ss_override : 1; // 0x36
+ uint32_t ds_override : 1; // 0x3E
+ uint32_t es_override : 1; // 0x26
+ uint32_t fs_override : 1; // 0x64
+ uint32_t gs_override : 1; // 0x65
+ uint32_t br_not_taken : 1; // 0x2E
+ uint32_t br_taken : 1; // 0x3E
+ uint32_t op_size : 1; // 0x66
+ uint32_t addr_size : 1; // 0x67
+
+ uint32_t rex : 1;
- uint_t rex_rm : 1; // REX.B
- uint_t rex_sib_idx : 1; // REX.X
- uint_t rex_reg : 1; // REX.R
- uint_t rex_op_size : 1; // REX.W
-
+ uint32_t rex_rm : 1; // REX.B
+ uint32_t rex_sib_idx : 1; // REX.X
+ uint32_t rex_reg : 1; // REX.R
+ uint32_t rex_op_size : 1; // REX.W
+
+ uint32_t rsvd : 11;
+ } __attribute__((packed));
+ } __attribute__((packed));
} __attribute__((packed));
return addr + seg->base;
break;
- case LONG:
+ case LONG: {
+ uint64_t seg_base = 0;
+
// In long mode the segment bases are disregarded (forced to 0), unless using
// FS or GS, then the base addresses are added
- return addr + seg->base;
+ if (seg) {
+ seg_base = seg->base;
+ }
+
+ return addr + seg_base;
+ }
case LONG_16_COMPAT:
default:
PrintError("Unsupported CPU Mode: %d\n", info->cpu_mode);