#ifndef __VMCB_H
#define __VMCB_H
-#include <palacios/vmm_types.h>
+#ifdef __V3VEE__
+#include <palacios/vmm_types.h>
+#include <palacios/vm_guest.h>
#define VMCB_CTRL_AREA_OFFSET 0x0
#define VMCB_STATE_SAVE_AREA_OFFSET 0x400
typedef void vmcb_t;
-union Ctrl_Registers {
- ushort_t bitmap PACKED;
- struct {
+struct Ctrl_Registers {
uint_t cr0 : 1 PACKED;
uint_t cr1 : 1 PACKED;
uint_t cr2 : 1 PACKED;
uint_t cr13 : 1 PACKED;
uint_t cr14 : 1 PACKED;
uint_t cr15 : 1 PACKED;
- } crs;
};
-union Debug_Registers {
- ushort_t bitmap PACKED;
- struct {
+struct Debug_Registers {
uint_t dr0 : 1 PACKED;
uint_t dr1 : 1 PACKED;
uint_t dr2 : 1 PACKED;
uint_t dr13 : 1 PACKED;
uint_t dr14 : 1 PACKED;
uint_t dr15 : 1 PACKED;
- } drs;
};
-union Exception_Vectors {
- uint_t bitmap PACKED;
- struct {
- uint_t ex0 : 1 PACKED;
- uint_t ex1 : 1 PACKED;
- uint_t ex2 : 1 PACKED;
- uint_t ex3 : 1 PACKED;
- uint_t ex4 : 1 PACKED;
- uint_t ex5 : 1 PACKED;
- uint_t ex6 : 1 PACKED;
- uint_t ex7 : 1 PACKED;
- uint_t ex8 : 1 PACKED;
- uint_t ex9 : 1 PACKED;
- uint_t ex10 : 1 PACKED;
- uint_t ex11 : 1 PACKED;
- uint_t ex12 : 1 PACKED;
- uint_t ex13 : 1 PACKED;
- uint_t ex14 : 1 PACKED;
- uint_t ex15 : 1 PACKED;
- uint_t ex16 : 1 PACKED;
- uint_t ex17 : 1 PACKED;
- uint_t ex18 : 1 PACKED;
- uint_t ex19 : 1 PACKED;
- uint_t ex20 : 1 PACKED;
- uint_t ex21 : 1 PACKED;
- uint_t ex22 : 1 PACKED;
- uint_t ex23 : 1 PACKED;
- uint_t ex24 : 1 PACKED;
- uint_t ex25 : 1 PACKED;
- uint_t ex26 : 1 PACKED;
- uint_t ex27 : 1 PACKED;
- uint_t ex28 : 1 PACKED;
- uint_t ex29 : 1 PACKED;
- uint_t ex30 : 1 PACKED;
- uint_t ex31 : 1 PACKED;
- } ex_numbers;
- struct {
- uint_t de : 1 PACKED; // divide by zero
- uint_t db : 1 PACKED; // Debug
- uint_t nmi : 1 PACKED; // Non-maskable interrupt
- uint_t bp : 1 PACKED; // Breakpoint
- uint_t of : 1 PACKED; // Overflow
- uint_t br : 1 PACKED; // Bound-Range
- uint_t ud : 1 PACKED; // Invalid-Opcode
- uint_t nm : 1 PACKED; // Device-not-available
- uint_t df : 1 PACKED; // Double Fault
+struct Exception_Vectors {
+ uint_t de : 1 PACKED; // (0) divide by zero
+ uint_t db : 1 PACKED; // (1) Debug
+ uint_t nmi : 1 PACKED; // (2) Non-maskable interrupt
+ uint_t bp : 1 PACKED; // (3) Breakpoint
+ uint_t of : 1 PACKED; // (4) Overflow
+ uint_t br : 1 PACKED; // (5) Bound-Range
+ uint_t ud : 1 PACKED; // (6) Invalid-Opcode
+ uint_t nm : 1 PACKED; // (7) Device-not-available
+ uint_t df : 1 PACKED; // (8) Double Fault
uint_t ex9 : 1 PACKED;
- uint_t ts : 1 PACKED; // Invalid TSS
- uint_t np : 1 PACKED; // Segment-not-present
- uint_t ss : 1 PACKED; // Stack
- uint_t gp : 1 PACKED; // General Protection Fault
- uint_t pf : 1 PACKED; // Page fault
+ uint_t ts : 1 PACKED; // (10) Invalid TSS
+ uint_t np : 1 PACKED; // (11) Segment-not-present
+ uint_t ss : 1 PACKED; // (12) Stack
+ uint_t gp : 1 PACKED; // (13) General Protection Fault
+ uint_t pf : 1 PACKED; // (14) Page fault
uint_t ex15 : 1 PACKED;
- uint_t mf : 1 PACKED; // Floating point exception
- uint_t ac : 1 PACKED; // Alignment-check
- uint_t mc : 1 PACKED; // Machine Check
- uint_t xf : 1 PACKED; // SIMD floating-point
+ uint_t mf : 1 PACKED; // (15) Floating point exception
+ uint_t ac : 1 PACKED; // (16) Alignment-check
+ uint_t mc : 1 PACKED; // (17) Machine Check
+ uint_t xf : 1 PACKED; // (18) SIMD floating-point
uint_t ex20 : 1 PACKED;
uint_t ex21 : 1 PACKED;
uint_t ex22 : 1 PACKED;
uint_t ex27 : 1 PACKED;
uint_t ex28 : 1 PACKED;
uint_t ex29 : 1 PACKED;
- uint_t sx : 1 PACKED; // Security Exception
+ uint_t sx : 1 PACKED; // (30) Security Exception
uint_t ex31 : 1 PACKED;
- } ex_names;
};
-union Instr_Intercepts {
- uint_t bitmap PACKED;
- struct {
+struct Instr_Intercepts {
uint_t INTR : 1 PACKED;
uint_t NMI : 1 PACKED;
uint_t SMI : 1 PACKED;
uint_t task_switch : 1 PACKED;
uint_t FERR_FREEZE : 1 PACKED;
uint_t shutdown_evts: 1 PACKED;
- } instrs;
};
-union SVM_Instr_Intercepts {
- uint_t bitmap PACKED;
- struct {
- uint_t VMRUN : 1 PACKED;
- uint_t VMMCALL : 1 PACKED;
- uint_t VMLOAD : 1 PACKED;
- uint_t VMSAVE : 1 PACKED;
- uint_t STGI : 1 PACKED;
- uint_t CLGI : 1 PACKED;
- uint_t SKINIT : 1 PACKED;
- uint_t RDTSCP : 1 PACKED;
- uint_t ICEBP : 1 PACKED;
- uint_t WBINVD : 1 PACKED;
- uint_t MONITOR : 1 PACKED;
- uint_t MWAIT_always : 1 PACKED;
- uint_t MWAIT_if_armed : 1 PACKED;
- uint_t reserved : 19 PACKED; // Should be 0
- } instrs;
+struct SVM_Instr_Intercepts {
+ uint_t VMRUN : 1 PACKED;
+ uint_t VMMCALL : 1 PACKED;
+ uint_t VMLOAD : 1 PACKED;
+ uint_t VMSAVE : 1 PACKED;
+ uint_t STGI : 1 PACKED;
+ uint_t CLGI : 1 PACKED;
+ uint_t SKINIT : 1 PACKED;
+ uint_t RDTSCP : 1 PACKED;
+ uint_t ICEBP : 1 PACKED;
+ uint_t WBINVD : 1 PACKED;
+ uint_t MONITOR : 1 PACKED;
+ uint_t MWAIT_always : 1 PACKED;
+ uint_t MWAIT_if_armed : 1 PACKED;
+ uint_t reserved : 19 PACKED; // Should be 0
};
-union Guest_Control {
- uint_t bitmap PACKED;
- struct {
- uchar_t V_TPR PACKED;
- uint_t V_IRQ : 1 PACKED;
- uint_t rsvd1 : 7 PACKED; // Should be 0
- uint_t V_INTR_PRIO : 4 PACKED;
- uint_t V_IGN_TPR : 1 PACKED;
- uint_t rsvd2 : 3 PACKED; // Should be 0
- uint_t V_INTR_MASKING : 1 PACKED;
- uint_t rsvd3 : 7 PACKED; // Should be 0
- uchar_t V_INTR_VECTOR PACKED;
- uint_t rsvd4 : 24 PACKED; // Should be 0
- } ctrls;
+struct Guest_Control {
+ uchar_t V_TPR PACKED;
+ uint_t V_IRQ : 1 PACKED;
+ uint_t rsvd1 : 7 PACKED; // Should be 0
+ uint_t V_INTR_PRIO : 4 PACKED;
+ uint_t V_IGN_TPR : 1 PACKED;
+ uint_t rsvd2 : 3 PACKED; // Should be 0
+ uint_t V_INTR_MASKING : 1 PACKED;
+ uint_t rsvd3 : 7 PACKED; // Should be 0
+ uchar_t V_INTR_VECTOR PACKED;
+ uint_t rsvd4 : 24 PACKED; // Should be 0
};
+#define SVM_INJECTION_EXTERNAL_INTR 0
+#define SVM_INJECTION_VIRTUAL_INTR 0
+#define SVM_INJECTION_NMI 2
+#define SVM_INJECTION_EXCEPTION 3
+#define SVM_INJECTION_SOFT_INTR 4
+
+struct Interrupt_Info {
+ uint_t vector : 8 PACKED;
+ uint_t type : 3 PACKED;
+ uint_t ev : 1 PACKED;
+ uint_t rsvd : 19 PACKED;
+ uint_t valid : 1 PACKED;
+ uint_t error_code : 32 PACKED;
+};
typedef struct VMCB_Control_Area {
// offset 0x0
- union Ctrl_Registers cr_reads PACKED;
- union Ctrl_Registers cr_writes PACKED;
- union Debug_Registers dr_reads PACKED;
- union Debug_Registers dr_writes PACKED;
- union Exception_Vectors exceptions PACKED;
- union Instr_Intercepts instrs PACKED;
- union SVM_Instr_Intercepts svm_instrs PACKED;
+ struct Ctrl_Registers cr_reads PACKED;
+ struct Ctrl_Registers cr_writes PACKED;
+ struct Debug_Registers dr_reads PACKED;
+ struct Debug_Registers dr_writes PACKED;
+ struct Exception_Vectors exceptions PACKED;
+ struct Instr_Intercepts instrs PACKED;
+ struct SVM_Instr_Intercepts svm_instrs PACKED;
uchar_t rsvd1[44] PACKED; // Should be 0
uchar_t rsvd2[3] PACKED; // Should be 0
- union Guest_Control guest_ctrl PACKED;
+ struct Guest_Control guest_ctrl PACKED;
uint_t interrupt_shadow : 1 PACKED;
uint_t rsvd3 : 31 PACKED; // Should be 0
* But it does say that the EXITINTINFO field is in bits 63-1
* ALL other occurances mention a 1 bit reserved field
*/
- uint_t rsvd5 : 1 PACKED;
- ullong_t exit_int_info : 63 PACKED;
+ // uint_t rsvd5 : 1 PACKED;
+ //ullong_t exit_int_info : 63 PACKED;
/* ** */
+ // AMD Manual 2, pg 391, sect: 15.19
+ struct Interrupt_Info exit_int_info PACKED;
+
// uint_t NP_ENABLE : 1 PACKED;
//ullong_t rsvd6 : 63 PACKED; // Should be 0
ullong_t NP_ENABLE PACKED;
uchar_t rsvd7[16] PACKED; // Should be 0
// Offset 0xA8
- ullong_t EVENTINJ PACKED;
+ struct Interrupt_Info EVENTINJ PACKED;
/* This could be a typo in the manual....
uint_t avl : 1 PACKED; // available for use by system software
uint_t L : 1 PACKED; // long mode (64 bit?)
uint_t db : 1 PACKED; // default op size (0=16 bit seg, 1=32 bit seg)
- uint_t G : 1 PACKED; // Granularity, (0=bytes, 1=4k)
+ uint_t G : 1 PACKED; // Granularity, (0=bytes, 1=4k)
+ uint_t rsvd : 4 PACKED;
} fields;
} attrib;
uint_t limit PACKED;
void PrintDebugVMCB(vmcb_t * vmcb);
+void set_vmcb_segments(vmcb_t * vmcb, struct v3_segments * segs);
+void get_vmcb_segments(vmcb_t * vmcb, struct v3_segments * segs);
+
+#endif // ! __V3VEE__
+
#endif