#include <palacios/vmm.h>
-
/*
The purpose of this interface is to make it possible to implement
/* There is a notion of a bus class to which the device is attached */
-typedef enum { DIRECT, PCI } v3_bus_class_t;
+typedef enum { V3_BUS_CLASS_DIRECT, V3_BUS_CLASS_PCI } v3_bus_class_t;
#ifdef __V3VEE__
+struct v3_vm_info;
+
v3_host_dev_t v3_host_dev_open(char *impl,
v3_bus_class_t bus,
- v3_guest_dev_t gdev);
+ v3_guest_dev_t gdev,
+ struct v3_vm_info *vm);
-uin64_t v3_host_dev_read_io(v3_host_dev_t hostdev,
- uint16_t port,
- void *dest
- uint64_t len);
+int v3_host_dev_close(v3_host_dev_t hdev);
+
+uint64_t v3_host_dev_read_io(v3_host_dev_t hostdev,
+ uint16_t port,
+ void *dest,
+ uint64_t len);
uint64_t v3_host_dev_write_io(v3_host_dev_t hostdev,
uint16_t port,
void *src,
uint64_t len);
-int v3_host_dev_ack_irq(v3_host_dev_t hostdev, uint32_t irq);
+int v3_host_dev_ack_irq(v3_host_dev_t hostdev, uint8_t irq);
-uint64_t v3_host_dev_config_read(v3_host_dev_t hostdev,
+uint64_t v3_host_dev_read_config(v3_host_dev_t hostdev,
+ uint64_t offset,
void *dest,
uint64_t len);
-uint64_t v3_host_dev_config_write(v3_host_dev_t hostdev,
+uint64_t v3_host_dev_write_config(v3_host_dev_t hostdev,
+ uint64_t offset,
void *src,
uint64_t len);
// this device is attached to and an opaque pointer back to the
// guest device. It returns an opaque representation of
// the host device it has attached to, with zero indicating
- // failure
+ // failure. The host_priv_data arguement supplies to the
+ // host the pointer that the VM was originally registered with
v3_host_dev_t (*open)(char *impl,
v3_bus_class_t bus,
- v3_guest_dev_t gdev);
+ v3_guest_dev_t gdev,
+ void *host_priv_data);
+
+ int (*close)(v3_host_dev_t hdev);
// Read/Write from/to an IO port. The read must either
// completely succeed, returning len or completely
// Callee gets the host dev id and the port in the guest
uint64_t (*read_io)(v3_host_dev_t hostdev,
uint16_t port,
- void *dest
+ void *dest,
uint64_t len);
uint64_t (*write_io)(v3_host_dev_t hostdev,
// fail, returning != len
// Callee gets the host dev id, and the guest physical address
uint64_t (*read_mem)(v3_host_dev_t hostdev,
- addr_t gpa,
+ void * gpa,
void *dest,
uint64_t len);
uint64_t (*write_mem)(v3_host_dev_t hostdev,
- addr_t gpa,
+ void * gpa,
void *src,
uint64_t len);
- // Palacis will call this when it has taken posession of the
- // IRQ ad wants the host device to lower it
- // This interface is unclear
+ //
+ // Palacios or the guest device will call this
+ // function when it has injected the irq
+ // requested by the guest
//
- // One potential use would be to allow for a palacios
- // side device to raise the irq asynchronously from
- // the host device. If this is permitted, then we
- // need a way of informing the host device that the
- // irq has actually been signalled.
int (*ack_irq)(v3_host_dev_t hostdev, uint8_t irq);
// Configuration space reads/writes for devices that
// config space info. However, a read will return
// the host device's config, while a write will affect
// both the palacios-internal config and the hsot device's config
- uint64_t (*config_read)(v3_host_dev_t hostdev,
+ //
+ // for V3_BUS_CLASS_PCI they correspond to PCI config space (e.g., BARS, etc)
+ // reads and writes
+ //
+ uint64_t (*read_config)(v3_host_dev_t hostdev,
+ uint64_t offset,
void *dest,
uint64_t len);
-
- uint64_t (*config_write)(v3_host_dev_t hostdev,
+
+ uint64_t (*write_config)(v3_host_dev_t hostdev,
+ uint64_t offset,
void *src,
uint64_t len);
/* These functions allow the host to read and write the guest
memory by physical address, for example to implement DMA
-
- These functions are incremental - that is, they can return
- a smaller amount than requested
*/
uint64_t v3_host_dev_read_guest_mem(v3_host_dev_t hostdev,
v3_guest_dev_t guest_dev,
- addr_t gpa,
+ void * gpa,
void *dest,
uint64_t len);
uint64_t v3_host_dev_write_guest_mem(v3_host_dev_t hostdev,
v3_guest_dev_t guest_dev,
- addr_t gpa,
+ void * gpa,
void *src,
uint64_t len);
