// struct pci_device_config
struct pci_config_header {
- union {
- uint32_t reg_00;
- struct {
- uint16_t vendor_id;
- uint16_t device_id;
- } __attribute__((packed));
- } __attribute__((packed));
-
- union {
- uint32_t reg_04;
- struct {
- uint16_t command;
- uint16_t status;
- } __attribute__((packed));
- } __attribute__((packed));
+ uint16_t vendor_id;
+ uint16_t device_id;
-
- union {
- uint32_t reg_08;
- struct {
- uint16_t revision;
- uint8_t subclass;
- uint8_t class;
- } __attribute__((packed));
- } __attribute__((packed));
-
- union {
- uint32_t reg_0c;
- struct {
- uint8_t cache_line_size;
- uint8_t latency_time;
- uint8_t header_type; // bits 6-0: 00: other, 01: pci-pci bridge, 02: pci-cardbus; bit 7: 1=multifunction
- uint8_t BIST;
- } __attribute__((packed));
- } __attribute__((packed));
+ uint16_t command;
+ uint16_t status;
+
+
+ uint8_t revision;
+ uint8_t prog_if;
+ uint8_t subclass;
+ uint8_t class;
+
+ uint8_t cache_line_size;
+ uint8_t latency_time;
+ uint8_t header_type; // bits 6-0: 00: other, 01: pci-pci bridge, 02: pci-cardbus; bit 7: 1=multifunction
+ uint8_t BIST;
- union {
- uint32_t reg_10;
- uint32_t BAR0;
- } __attribute__((packed));
-
- union {
- uint32_t reg_14;
- uint32_t BAR1;
- } __attribute__((packed));
-
- union {
- uint32_t reg_18;
- uint32_t BAR2;
- } __attribute__((packed));
-
- union {
- uint32_t reg_1c;
- uint32_t BAR3;
- } __attribute__((packed));
-
- union {
- uint32_t reg_20;
- uint32_t BAR4;
- } __attribute__((packed));
-
- union {
- uint32_t reg_24;
- uint32_t BAR5;
- } __attribute__((packed));
-
-
- union {
- uint32_t reg_28;
- uint32_t cardbus_cis_pointer;
- } __attribute__((packed));
-
- union {
- uint32_t reg_2c;
- struct {
- uint16_t subsystem_vendor_id;
- uint16_t subsystem_id;
- } __attribute__((packed));
- } __attribute__((packed));
-
- union {
- uint32_t reg_30;
- uint32_t expansion_rom_address;
- } __attribute__((packed));;
-
- union {
- uint32_t reg_34;
- struct {
- uint8_t cap_ptr; // capabilities list offset in config space
- uint8_t rsvd1[3];
- } __attribute__((packed));
- } __attribute__((packed));
-
- union {
- uint32_t reg_38;
- uint32_t rsvd2;
- } __attribute__((packed));
-
-
- union {
- uint32_t reg_3c;
- struct {
- uint8_t intr_line; // 00=none, 01=IRQ1, etc.
- uint8_t intr_pin; // 00=none, otherwise INTA# to INTD#
- uint8_t min_grant; // min busmaster time - units of 250ns
- uint8_t max_latency; // units of 250ns - busmasters
- } __attribute__((packed));
- } __attribute__((packed));
+ uint32_t BAR0;
+ uint32_t BAR1;
+ uint32_t BAR2;
+ uint32_t BAR3;
+ uint32_t BAR4;
+ uint32_t BAR5;
+ uint32_t cardbus_cis_pointer;
+ uint16_t subsystem_vendor_id;
+ uint16_t subsystem_id;
+ uint32_t expansion_rom_address;
+ uint8_t cap_ptr; // capabilities list offset in config space
+ uint8_t rsvd1[3];
+ uint32_t rsvd2;
+ uint8_t intr_line; // 00=none, 01=IRQ1, etc.
+ uint8_t intr_pin; // 00=none, otherwise INTA# to INTD#
+ uint8_t min_grant; // min busmaster time - units of 250ns
+ uint8_t max_latency; // units of 250ns - busmasters
} __attribute__((packed));
+typedef enum { PCI_CLASS_PRE2 = 0x00,
+ PCI_CLASS_STORAGE = 0x01,
+ PCI_CLASS_NETWORK = 0x02,
+ PCI_CLASS_DISPLAY = 0x03,
+ PCI_CLASS_MMEDIA = 0x04,
+ PCI_CLASS_MEMORY = 0x05,
+ PCI_CLASS_BRIDGE = 0x06,
+ PCI_CLASS_COMM_CTRL = 0x07,
+ PCI_CLASS_BASE_PERIPH = 0x08,
+ PCI_CLASS_INPUT = 0x09,
+ PCI_CLASS_DOCK = 0x0a,
+ PCI_CLASS_PROC = 0x0b,
+ PCI_CLASS_SERIAL = 0x0c,
+ PCI_CLASS_MISC = 0xff } pci_class_t;
+
+typedef enum { PCI_STORAGE_SUBCLASS_SCSI = 0x00,
+ PCI_STORAGE_SUBCLASS_IDE = 0x01,
+ PCI_STORAGE_SUBCLASS_FLOPPY = 0x02,
+ PCI_STORAGE_SUBCLASS_IPI = 0x03,
+ PCI_STORAGE_SUBCLASS_RAID = 0x04,
+ PCI_STORAGE_SUBCLASS_SATA = 0x06,
+ PCI_STORAGE_SUBCLASS_SAS = 0x07,
+ PCI_STORAGE_SUBCLASS_OTHER = 0x80 } pci_storage_subclass_t;
+
+
+
+typedef enum { PCI_NET_SUBCLASS_ETHER = 0x00,
+ PCI_NET_SUBCLASS_TOKRING = 0x01,
+ PCI_NET_SUBCLASS_FDDI = 0x02,
+ PCI_NET_SUBCLASS_ATM = 0x03,
+ PCI_NET_SUBCLASS_OTHER = 0x80 } pci_network_subclass_t;
+
+typedef enum { PCI_DISPLAY_SUBCLASS_VGA = 0x00,
+ PCI_DISPLAY_SUBCLASS_XGA = 0x01,
+ PCI_DISPLAY_SUBCLASS_OTHER = 0x80 } pci_display_subclass_t;
+
+typedef enum { PCI_MMEDIA_SUBCLASS_VIDEO = 0x00,
+ PCI_MMEDIA_SUBCLASS_AUDIO = 0x01,
+ PCI_MMEDIA_SUBCLASS_OTHER = 0x80 } pci_multimedia_subclass_t;
+
+typedef enum { PCI_MEM_SUBCLASS_RAM = 0x00,
+ PCI_MEM_SUBCLASS_FLASH = 0x01,
+ PCI_MEM_SUBCLASS_OTHER = 0x80 } pci_memory_subclass_t;
+
+typedef enum { PCI_BRIDGE_SUBCLASS_HOST_PCI = 0x00,
+ PCI_BRIDGE_SUBCLASS_PCI_ISA = 0x01,
+ PCI_BRIDGE_SUBCLASS_PCI_EISA = 0x02,
+ PCI_BRIDGE_SUBCLASS_PCI_MICRO = 0x03,
+ PCI_BRIDGE_SUBCLASS_PCI_PCI = 0x04,
+ PCI_BRIDGE_SUBCLASS_PCI_PCMCIA = 0x05,
+ PCI_BRIDGE_SUBCLASS_PCI_NUBUS = 0x06,
+ PCI_BRIDGE_SUBCLASS_PCI_CARDBUS = 0x07,
+ PCI_BRIDGE_SUBCLASS_PCI_OTHER = 0x80 } pci_bridge_subclass_t;
+
+
+
/*
struct pci_class_desc {
uint16_t class;