2 * This file is part of the Palacios Virtual Machine Monitor developed
3 * by the V3VEE Project with funding from the United States National
4 * Science Foundation and the Department of Energy.
6 * The V3VEE Project is a joint project between Northwestern University
7 * and the University of New Mexico. You can find out more at
10 * Copyright (c) 2011, Jack Lange <jarusl@cs.northwestern.edu>
11 * Copyright (c) 2011, The V3VEE Project <http://www.v3vee.org>
12 * All rights reserved.
14 * Author: Jack Lange <jarusl@cs.northwestern.edu>
16 * This is free software. You are permitted to use,
17 * redistribute, and modify it as specified in the file "V3VEE_LICENSE".
21 #include <palacios/vmx.h>
22 #include <palacios/vmm.h>
23 #include <palacios/vmx_handler.h>
24 #include <palacios/vmcs.h>
25 #include <palacios/vmx_lowlevel.h>
26 #include <palacios/vmm_lowlevel.h>
27 #include <palacios/vmm_ctrl_regs.h>
28 #include <palacios/vmm_config.h>
29 #include <palacios/vmm_time.h>
30 #include <palacios/vm_guest_mem.h>
31 #include <palacios/vmm_direct_paging.h>
32 #include <palacios/vmx_io.h>
33 #include <palacios/vmx_msr.h>
34 #include <palacios/vmm_decoder.h>
35 #include <palacios/vmm_barrier.h>
36 #include <palacios/vmm_timeout.h>
37 #include <palacios/vmm_debug.h>
39 #ifdef V3_CONFIG_CHECKPOINT
40 #include <palacios/vmm_checkpoint.h>
43 #include <palacios/vmx_ept.h>
44 #include <palacios/vmx_assist.h>
45 #include <palacios/vmx_hw_info.h>
47 #ifndef V3_CONFIG_DEBUG_VMX
49 #define PrintDebug(fmt, args...)
53 /* These fields contain the hardware feature sets supported by the local CPU */
54 static struct vmx_hw_info hw_info;
56 extern v3_cpu_arch_t v3_mach_type;
58 static addr_t host_vmcs_ptrs[V3_CONFIG_MAX_CPUS] = { [0 ... V3_CONFIG_MAX_CPUS - 1] = 0};
60 extern int v3_vmx_launch(struct v3_gprs * vm_regs, struct guest_info * info, struct v3_ctrl_regs * ctrl_regs);
61 extern int v3_vmx_resume(struct v3_gprs * vm_regs, struct guest_info * info, struct v3_ctrl_regs * ctrl_regs);
63 static int inline check_vmcs_write(vmcs_field_t field, addr_t val) {
66 ret = vmcs_write(field, val);
68 if (ret != VMX_SUCCESS) {
69 PrintError("VMWRITE error on %s!: %d\n", v3_vmcs_field_to_str(field), ret);
79 static int inline check_vmcs_read(vmcs_field_t field, void * val) {
82 ret = vmcs_read(field, val);
84 if (ret != VMX_SUCCESS) {
85 PrintError("VMREAD error on %s!: %d\n", v3_vmcs_field_to_str(field), ret);
94 static addr_t allocate_vmcs() {
95 struct vmcs_data * vmcs_page = NULL;
97 PrintDebug("Allocating page\n");
99 vmcs_page = (struct vmcs_data *)V3_VAddr(V3_AllocPages(1));
100 memset(vmcs_page, 0, 4096);
102 vmcs_page->revision = hw_info.basic_info.revision;
103 PrintDebug("VMX Revision: 0x%x\n", vmcs_page->revision);
105 return (addr_t)V3_PAddr((void *)vmcs_page);
110 static int debug_efer_read(struct guest_info * core, uint_t msr, struct v3_msr * src, void * priv_data) {
111 struct v3_msr * efer = (struct v3_msr *)&(core->ctrl_regs.efer);
112 V3_Print("\n\nEFER READ (val = %p)\n", (void *)efer->value);
114 v3_print_guest_state(core);
118 src->value = efer->value;
122 static int debug_efer_write(struct guest_info * core, uint_t msr, struct v3_msr src, void * priv_data) {
123 struct v3_msr * efer = (struct v3_msr *)&(core->ctrl_regs.efer);
124 V3_Print("\n\nEFER WRITE (old_val = %p) (new_val = %p)\n", (void *)efer->value, (void *)src.value);
126 v3_print_guest_state(core);
129 efer->value = src.value;
136 static int init_vmcs_bios(struct guest_info * core, struct vmx_data * vmx_state) {
139 /* Get Available features */
140 struct vmx_pin_ctrls avail_pin_ctrls;
141 avail_pin_ctrls.value = v3_vmx_get_ctrl_features(&(hw_info.pin_ctrls));
145 // disable global interrupts for vm state initialization
148 PrintDebug("Loading VMCS\n");
149 vmx_ret = vmcs_load(vmx_state->vmcs_ptr_phys);
150 vmx_state->state = VMX_UNLAUNCHED;
152 if (vmx_ret != VMX_SUCCESS) {
153 PrintError("VMPTRLD failed\n");
158 /*** Setup default state from HW ***/
160 vmx_state->pin_ctrls.value = hw_info.pin_ctrls.def_val;
161 vmx_state->pri_proc_ctrls.value = hw_info.proc_ctrls.def_val;
162 vmx_state->exit_ctrls.value = hw_info.exit_ctrls.def_val;
163 vmx_state->entry_ctrls.value = hw_info.entry_ctrls.def_val;
164 vmx_state->sec_proc_ctrls.value = hw_info.sec_proc_ctrls.def_val;
166 /* Print Control MSRs */
167 V3_Print("CR0 MSR: req_val=%p, req_mask=%p\n", (void *)(addr_t)hw_info.cr0.req_val, (void *)(addr_t)hw_info.cr0.req_mask);
168 V3_Print("CR4 MSR: req_val=%p, req_mask=%p\n", (void *)(addr_t)hw_info.cr4.req_val, (void *)(addr_t)hw_info.cr4.req_mask);
172 /******* Setup Host State **********/
174 /* Cache GDTR, IDTR, and TR in host struct */
177 /********** Setup VMX Control Fields ***********/
179 /* Add external interrupts, NMI exiting, and virtual NMI */
180 vmx_state->pin_ctrls.nmi_exit = 1;
181 vmx_state->pin_ctrls.ext_int_exit = 1;
184 /* We enable the preemption timer by default to measure accurate guest time */
185 if (avail_pin_ctrls.active_preempt_timer) {
186 V3_Print("VMX Preemption Timer is available\n");
187 vmx_state->pin_ctrls.active_preempt_timer = 1;
188 vmx_state->exit_ctrls.save_preempt_timer = 1;
191 vmx_state->pri_proc_ctrls.hlt_exit = 1;
194 vmx_state->pri_proc_ctrls.pause_exit = 0;
195 vmx_state->pri_proc_ctrls.tsc_offset = 1;
196 #ifdef V3_CONFIG_TIME_VIRTUALIZE_TSC
197 vmx_state->pri_proc_ctrls.rdtsc_exit = 1;
201 vmx_state->pri_proc_ctrls.use_io_bitmap = 1;
202 vmx_ret |= check_vmcs_write(VMCS_IO_BITMAP_A_ADDR, (addr_t)V3_PAddr(core->vm_info->io_map.arch_data));
203 vmx_ret |= check_vmcs_write(VMCS_IO_BITMAP_B_ADDR,
204 (addr_t)V3_PAddr(core->vm_info->io_map.arch_data) + PAGE_SIZE_4KB);
207 vmx_state->pri_proc_ctrls.use_msr_bitmap = 1;
208 vmx_ret |= check_vmcs_write(VMCS_MSR_BITMAP, (addr_t)V3_PAddr(core->vm_info->msr_map.arch_data));
213 // Ensure host runs in 64-bit mode at each VM EXIT
214 vmx_state->exit_ctrls.host_64_on = 1;
219 // Restore host's EFER register on each VM EXIT
220 vmx_state->exit_ctrls.ld_efer = 1;
222 // Save/restore guest's EFER register to/from VMCS on VM EXIT/ENTRY
223 vmx_state->exit_ctrls.save_efer = 1;
224 vmx_state->entry_ctrls.ld_efer = 1;
226 vmx_state->exit_ctrls.save_pat = 1;
227 vmx_state->exit_ctrls.ld_pat = 1;
228 vmx_state->entry_ctrls.ld_pat = 1;
230 /* Temporary GPF trap */
231 // vmx_state->excp_bmap.gp = 1;
233 // Setup Guests initial PAT field
234 vmx_ret |= check_vmcs_write(VMCS_GUEST_PAT, 0x0007040600070406LL);
237 if (core->shdw_pg_mode == SHADOW_PAGING) {
238 PrintDebug("Creating initial shadow page table\n");
240 if (v3_init_passthrough_pts(core) == -1) {
241 PrintError("Could not initialize passthrough page tables\n");
245 #define CR0_PE 0x00000001
246 #define CR0_PG 0x80000000
247 #define CR0_WP 0x00010000 // To ensure mem hooks work
248 #define CR0_NE 0x00000020
249 vmx_ret |= check_vmcs_write(VMCS_CR0_MASK, (CR0_PE | CR0_PG | CR0_WP | CR0_NE));
252 // Cause VM_EXIT whenever CR4.VMXE or CR4.PAE bits are written
253 vmx_ret |= check_vmcs_write(VMCS_CR4_MASK, CR4_VMXE | CR4_PAE);
255 core->ctrl_regs.cr3 = core->direct_map_pt;
257 // vmx_state->pinbased_ctrls |= NMI_EXIT;
260 vmx_state->pri_proc_ctrls.cr3_ld_exit = 1;
261 vmx_state->pri_proc_ctrls.cr3_str_exit = 1;
263 vmx_state->pri_proc_ctrls.invlpg_exit = 1;
265 /* Add page fault exits */
266 vmx_state->excp_bmap.pf = 1;
269 v3_vmxassist_init(core, vmx_state);
271 // Hook all accesses to EFER register
272 v3_hook_msr(core->vm_info, EFER_MSR,
273 &v3_handle_efer_read,
274 &v3_handle_efer_write,
277 } else if ((core->shdw_pg_mode == NESTED_PAGING) &&
278 (v3_mach_type == V3_VMX_EPT_CPU)) {
280 #define CR0_PE 0x00000001
281 #define CR0_PG 0x80000000
282 #define CR0_WP 0x00010000 // To ensure mem hooks work
283 #define CR0_NE 0x00000020
284 vmx_ret |= check_vmcs_write(VMCS_CR0_MASK, (CR0_PE | CR0_PG | CR0_WP | CR0_NE));
286 // vmx_state->pinbased_ctrls |= NMI_EXIT;
288 // Cause VM_EXIT whenever CR4.VMXE or CR4.PAE bits are written
289 vmx_ret |= check_vmcs_write(VMCS_CR4_MASK, CR4_VMXE | CR4_PAE);
291 /* Disable CR exits */
292 vmx_state->pri_proc_ctrls.cr3_ld_exit = 0;
293 vmx_state->pri_proc_ctrls.cr3_str_exit = 0;
295 vmx_state->pri_proc_ctrls.invlpg_exit = 0;
297 /* Add page fault exits */
298 // vmx_state->excp_bmap.pf = 1; // This should never happen..., enabled to catch bugs
301 v3_vmxassist_init(core, vmx_state);
304 vmx_state->pri_proc_ctrls.sec_ctrls = 1; // Enable secondary proc controls
305 vmx_state->sec_proc_ctrls.enable_ept = 1; // enable EPT paging
309 if (v3_init_ept(core, &hw_info) == -1) {
310 PrintError("Error initializing EPT\n");
314 // Hook all accesses to EFER register
315 v3_hook_msr(core->vm_info, EFER_MSR, NULL, NULL, NULL);
317 } else if ((core->shdw_pg_mode == NESTED_PAGING) &&
318 (v3_mach_type == V3_VMX_EPT_UG_CPU)) {
320 // For now we will assume that unrestricted guest mode is assured w/ EPT
323 core->vm_regs.rsp = 0x00;
325 core->vm_regs.rdx = 0x00000f00;
326 core->ctrl_regs.rflags = 0x00000002; // The reserved bit is always 1
327 core->ctrl_regs.cr0 = 0x60010030;
328 core->ctrl_regs.cr4 = 0x00002010; // Enable VMX and PSE flag
331 core->segments.cs.selector = 0xf000;
332 core->segments.cs.limit = 0xffff;
333 core->segments.cs.base = 0x0000000f0000LL;
335 // (raw attributes = 0xf3)
336 core->segments.cs.type = 0xb;
337 core->segments.cs.system = 0x1;
338 core->segments.cs.dpl = 0x0;
339 core->segments.cs.present = 1;
343 struct v3_segment * segregs [] = {&(core->segments.ss), &(core->segments.ds),
344 &(core->segments.es), &(core->segments.fs),
345 &(core->segments.gs), NULL};
347 for ( i = 0; segregs[i] != NULL; i++) {
348 struct v3_segment * seg = segregs[i];
350 seg->selector = 0x0000;
351 // seg->base = seg->selector << 4;
352 seg->base = 0x00000000;
360 // seg->granularity = 1;
365 core->segments.gdtr.limit = 0x0000ffff;
366 core->segments.gdtr.base = 0x0000000000000000LL;
368 core->segments.idtr.limit = 0x0000ffff;
369 core->segments.idtr.base = 0x0000000000000000LL;
371 core->segments.ldtr.selector = 0x0000;
372 core->segments.ldtr.limit = 0x0000ffff;
373 core->segments.ldtr.base = 0x0000000000000000LL;
374 core->segments.ldtr.type = 0x2;
375 core->segments.ldtr.present = 1;
377 core->segments.tr.selector = 0x0000;
378 core->segments.tr.limit = 0x0000ffff;
379 core->segments.tr.base = 0x0000000000000000LL;
380 core->segments.tr.type = 0xb;
381 core->segments.tr.present = 1;
383 // core->dbg_regs.dr6 = 0x00000000ffff0ff0LL;
384 core->dbg_regs.dr7 = 0x0000000000000400LL;
387 vmx_state->pri_proc_ctrls.sec_ctrls = 1; // Enable secondary proc controls
388 vmx_state->sec_proc_ctrls.enable_ept = 1; // enable EPT paging
389 vmx_state->sec_proc_ctrls.unrstrct_guest = 1; // enable unrestricted guest operation
392 /* Disable shadow paging stuff */
393 vmx_state->pri_proc_ctrls.cr3_ld_exit = 0;
394 vmx_state->pri_proc_ctrls.cr3_str_exit = 0;
396 vmx_state->pri_proc_ctrls.invlpg_exit = 0;
399 // Cause VM_EXIT whenever the CR4.VMXE bit is set
400 vmx_ret |= check_vmcs_write(VMCS_CR4_MASK, CR4_VMXE);
401 #define CR0_NE 0x00000020
402 vmx_ret |= check_vmcs_write(VMCS_CR0_MASK, CR0_NE);
403 ((struct cr0_32 *)&(core->shdw_pg_state.guest_cr0))->ne = 1;
405 if (v3_init_ept(core, &hw_info) == -1) {
406 PrintError("Error initializing EPT\n");
410 // Hook all accesses to EFER register
411 // v3_hook_msr(core->vm_info, EFER_MSR, &debug_efer_read, &debug_efer_write, core);
412 v3_hook_msr(core->vm_info, EFER_MSR, NULL, NULL, NULL);
414 PrintError("Invalid Virtual paging mode (pg_mode=%d) (mach_type=%d)\n", core->shdw_pg_mode, v3_mach_type);
421 // Setup SYSCALL/SYSENTER MSRs in load/store area
423 // save STAR, LSTAR, FMASK, KERNEL_GS_BASE MSRs in MSR load/store area
426 struct vmcs_msr_save_area * msr_entries = NULL;
427 int max_msrs = (hw_info.misc_info.max_msr_cache_size + 1) * 4;
430 V3_Print("Setting up MSR load/store areas (max_msr_count=%d)\n", max_msrs);
433 PrintError("Max MSR cache size is too small (%d)\n", max_msrs);
437 vmx_state->msr_area_paddr = (addr_t)V3_AllocPages(1);
439 if (vmx_state->msr_area_paddr == (addr_t)NULL) {
440 PrintError("could not allocate msr load/store area\n");
444 msr_entries = (struct vmcs_msr_save_area *)V3_VAddr((void *)(vmx_state->msr_area_paddr));
445 vmx_state->msr_area = msr_entries; // cache in vmx_info
447 memset(msr_entries, 0, PAGE_SIZE);
449 msr_entries->guest_star.index = IA32_STAR_MSR;
450 msr_entries->guest_lstar.index = IA32_LSTAR_MSR;
451 msr_entries->guest_fmask.index = IA32_FMASK_MSR;
452 msr_entries->guest_kern_gs.index = IA32_KERN_GS_BASE_MSR;
454 msr_entries->host_star.index = IA32_STAR_MSR;
455 msr_entries->host_lstar.index = IA32_LSTAR_MSR;
456 msr_entries->host_fmask.index = IA32_FMASK_MSR;
457 msr_entries->host_kern_gs.index = IA32_KERN_GS_BASE_MSR;
459 msr_ret |= check_vmcs_write(VMCS_EXIT_MSR_STORE_CNT, 4);
460 msr_ret |= check_vmcs_write(VMCS_EXIT_MSR_LOAD_CNT, 4);
461 msr_ret |= check_vmcs_write(VMCS_ENTRY_MSR_LOAD_CNT, 4);
463 msr_ret |= check_vmcs_write(VMCS_EXIT_MSR_STORE_ADDR, (addr_t)V3_PAddr(msr_entries->guest_msrs));
464 msr_ret |= check_vmcs_write(VMCS_ENTRY_MSR_LOAD_ADDR, (addr_t)V3_PAddr(msr_entries->guest_msrs));
465 msr_ret |= check_vmcs_write(VMCS_EXIT_MSR_LOAD_ADDR, (addr_t)V3_PAddr(msr_entries->host_msrs));
468 msr_ret |= v3_hook_msr(core->vm_info, IA32_STAR_MSR, NULL, NULL, NULL);
469 msr_ret |= v3_hook_msr(core->vm_info, IA32_LSTAR_MSR, NULL, NULL, NULL);
470 msr_ret |= v3_hook_msr(core->vm_info, IA32_FMASK_MSR, NULL, NULL, NULL);
471 msr_ret |= v3_hook_msr(core->vm_info, IA32_KERN_GS_BASE_MSR, NULL, NULL, NULL);
474 // IMPORTANT: These MSRs appear to be cached by the hardware....
475 msr_ret |= v3_hook_msr(core->vm_info, SYSENTER_CS_MSR, NULL, NULL, NULL);
476 msr_ret |= v3_hook_msr(core->vm_info, SYSENTER_ESP_MSR, NULL, NULL, NULL);
477 msr_ret |= v3_hook_msr(core->vm_info, SYSENTER_EIP_MSR, NULL, NULL, NULL);
479 msr_ret |= v3_hook_msr(core->vm_info, FS_BASE_MSR, NULL, NULL, NULL);
480 msr_ret |= v3_hook_msr(core->vm_info, GS_BASE_MSR, NULL, NULL, NULL);
482 msr_ret |= v3_hook_msr(core->vm_info, IA32_PAT_MSR, NULL, NULL, NULL);
484 // Not sure what to do about this... Does not appear to be an explicit hardware cache version...
485 msr_ret |= v3_hook_msr(core->vm_info, IA32_CSTAR_MSR, NULL, NULL, NULL);
488 PrintError("Error configuring MSR save/restore area\n");
495 /* Sanity check ctrl/reg fields against hw_defaults */
500 /*** Write all the info to the VMCS ***/
504 // IS THIS NECESSARY???
505 #define DEBUGCTL_MSR 0x1d9
506 struct v3_msr tmp_msr;
507 v3_get_msr(DEBUGCTL_MSR, &(tmp_msr.hi), &(tmp_msr.lo));
508 vmx_ret |= check_vmcs_write(VMCS_GUEST_DBG_CTL, tmp_msr.value);
509 core->dbg_regs.dr7 = 0x400;
514 vmx_ret |= check_vmcs_write(VMCS_LINK_PTR, (addr_t)0xffffffffffffffffULL);
516 vmx_ret |= check_vmcs_write(VMCS_LINK_PTR, (addr_t)0xffffffffUL);
517 vmx_ret |= check_vmcs_write(VMCS_LINK_PTR_HIGH, (addr_t)0xffffffffUL);
523 if (v3_update_vmcs_ctrl_fields(core)) {
524 PrintError("Could not write control fields!\n");
529 if (v3_update_vmcs_host_state(core)) {
530 PrintError("Could not write host state\n");
535 // reenable global interrupts for vm state initialization now
536 // that the vm state is initialized. If another VM kicks us off,
537 // it'll update our vmx state so that we know to reload ourself
544 static void __init_vmx_vmcs(void * arg) {
545 struct guest_info * core = arg;
546 struct vmx_data * vmx_state = NULL;
549 vmx_state = (struct vmx_data *)V3_Malloc(sizeof(struct vmx_data));
550 memset(vmx_state, 0, sizeof(struct vmx_data));
552 PrintDebug("vmx_data pointer: %p\n", (void *)vmx_state);
554 PrintDebug("Allocating VMCS\n");
555 vmx_state->vmcs_ptr_phys = allocate_vmcs();
557 PrintDebug("VMCS pointer: %p\n", (void *)(vmx_state->vmcs_ptr_phys));
559 core->vmm_data = vmx_state;
560 vmx_state->state = VMX_UNLAUNCHED;
562 PrintDebug("Initializing VMCS (addr=%p)\n", core->vmm_data);
564 // TODO: Fix vmcs fields so they're 32-bit
566 PrintDebug("Clearing VMCS: %p\n", (void *)vmx_state->vmcs_ptr_phys);
567 vmx_ret = vmcs_clear(vmx_state->vmcs_ptr_phys);
569 if (vmx_ret != VMX_SUCCESS) {
570 PrintError("VMCLEAR failed\n");
574 if (core->vm_info->vm_class == V3_PC_VM) {
575 PrintDebug("Initializing VMCS\n");
576 if (init_vmcs_bios(core, vmx_state) == -1) {
577 PrintError("Error initializing VMCS to BIOS state\n");
581 PrintError("Invalid VM Class\n");
585 PrintDebug("Serializing VMCS: %p\n", (void *)vmx_state->vmcs_ptr_phys);
586 vmx_ret = vmcs_clear(vmx_state->vmcs_ptr_phys);
588 core->core_run_state = CORE_STOPPED;
594 int v3_init_vmx_vmcs(struct guest_info * core, v3_vm_class_t vm_class) {
595 extern v3_cpu_arch_t v3_cpu_types[];
597 if (v3_cpu_types[V3_Get_CPU()] == V3_INVALID_CPU) {
600 for (i = 0; i < V3_CONFIG_MAX_CPUS; i++) {
601 if (v3_cpu_types[i] != V3_INVALID_CPU) {
606 if (i == V3_CONFIG_MAX_CPUS) {
607 PrintError("Could not find VALID CPU for VMX guest initialization\n");
611 V3_Call_On_CPU(i, __init_vmx_vmcs, core);
614 __init_vmx_vmcs(core);
617 if (core->core_run_state != CORE_STOPPED) {
618 PrintError("Error initializing VMX Core\n");
626 int v3_deinit_vmx_vmcs(struct guest_info * core) {
627 struct vmx_data * vmx_state = core->vmm_data;
629 V3_FreePages((void *)(vmx_state->vmcs_ptr_phys), 1);
630 V3_FreePages(V3_PAddr(vmx_state->msr_area), 1);
639 #ifdef V3_CONFIG_CHECKPOINT
641 * JRL: This is broken
643 int v3_vmx_save_core(struct guest_info * core, void * ctx){
644 struct vmx_data * vmx_info = (struct vmx_data *)(core->vmm_data);
646 // note that the vmcs pointer is an HPA, but we need an HVA
647 if (v3_chkpt_save(ctx, "vmcs_data", PAGE_SIZE_4KB,
648 V3_VAddr((void*) (vmx_info->vmcs_ptr_phys))) ==-1) {
649 PrintError("Could not save vmcs data for VMX\n");
656 int v3_vmx_load_core(struct guest_info * core, void * ctx){
657 struct vmx_data * vmx_info = (struct vmx_data *)(core->vmm_data);
658 struct cr0_32 * shadow_cr0;
659 addr_t vmcs_page_paddr; //HPA
661 vmcs_page_paddr = (addr_t) V3_AllocPages(1);
663 if (!vmcs_page_paddr) {
664 PrintError("Could not allocate space for a vmcs in VMX\n");
668 if (v3_chkpt_load(ctx, "vmcs_data", PAGE_SIZE_4KB,
669 V3_VAddr((void *)vmcs_page_paddr)) == -1) {
670 PrintError("Could not load vmcs data for VMX\n");
674 vmcs_clear(vmx_info->vmcs_ptr_phys);
676 // Probably need to delete the old one...
677 V3_FreePages((void*)(vmx_info->vmcs_ptr_phys),1);
679 vmcs_load(vmcs_page_paddr);
681 v3_vmx_save_vmcs(core);
683 shadow_cr0 = (struct cr0_32 *)&(core->ctrl_regs.cr0);
686 /* Get the CPU mode to set the guest_ia32e entry ctrl */
688 if (core->shdw_pg_mode == SHADOW_PAGING) {
689 if (v3_get_vm_mem_mode(core) == VIRTUAL_MEM) {
690 if (v3_activate_shadow_pt(core) == -1) {
691 PrintError("Failed to activate shadow page tables\n");
695 if (v3_activate_passthrough_pt(core) == -1) {
696 PrintError("Failed to activate passthrough page tables\n");
707 void v3_flush_vmx_vm_core(struct guest_info * core) {
708 struct vmx_data * vmx_info = (struct vmx_data *)(core->vmm_data);
709 vmcs_clear(vmx_info->vmcs_ptr_phys);
710 vmx_info->state = VMX_UNLAUNCHED;
715 static int update_irq_exit_state(struct guest_info * info) {
716 struct vmx_exit_idt_vec_info idt_vec_info;
718 check_vmcs_read(VMCS_IDT_VECTOR_INFO, &(idt_vec_info.value));
720 if ((info->intr_core_state.irq_started == 1) && (idt_vec_info.valid == 0)) {
721 #ifdef V3_CONFIG_DEBUG_INTERRUPTS
722 V3_Print("Calling v3_injecting_intr\n");
724 info->intr_core_state.irq_started = 0;
725 v3_injecting_intr(info, info->intr_core_state.irq_vector, V3_EXTERNAL_IRQ);
731 static int update_irq_entry_state(struct guest_info * info) {
732 struct vmx_exit_idt_vec_info idt_vec_info;
733 struct vmcs_interrupt_state intr_core_state;
734 struct vmx_data * vmx_info = (struct vmx_data *)(info->vmm_data);
736 check_vmcs_read(VMCS_IDT_VECTOR_INFO, &(idt_vec_info.value));
737 check_vmcs_read(VMCS_GUEST_INT_STATE, &(intr_core_state));
739 /* Check for pending exceptions to inject */
740 if (v3_excp_pending(info)) {
741 struct vmx_entry_int_info int_info;
744 // In VMX, almost every exception is hardware
745 // Software exceptions are pretty much only for breakpoint or overflow
747 int_info.vector = v3_get_excp_number(info);
749 if (info->excp_state.excp_error_code_valid) {
750 check_vmcs_write(VMCS_ENTRY_EXCP_ERR, info->excp_state.excp_error_code);
751 int_info.error_code = 1;
753 #ifdef V3_CONFIG_DEBUG_INTERRUPTS
754 V3_Print("Injecting exception %d with error code %x\n",
755 int_info.vector, info->excp_state.excp_error_code);
760 #ifdef V3_CONFIG_DEBUG_INTERRUPTS
761 V3_Print("Injecting exception %d (EIP=%p)\n", int_info.vector, (void *)(addr_t)info->rip);
763 check_vmcs_write(VMCS_ENTRY_INT_INFO, int_info.value);
765 v3_injecting_excp(info, int_info.vector);
767 } else if ((((struct rflags *)&(info->ctrl_regs.rflags))->intr == 1) &&
768 (intr_core_state.val == 0)) {
770 if ((info->intr_core_state.irq_started == 1) && (idt_vec_info.valid == 1)) {
772 #ifdef V3_CONFIG_DEBUG_INTERRUPTS
773 V3_Print("IRQ pending from previous injection\n");
776 // Copy the IDT vectoring info over to reinject the old interrupt
777 if (idt_vec_info.error_code == 1) {
778 uint32_t err_code = 0;
780 check_vmcs_read(VMCS_IDT_VECTOR_ERR, &err_code);
781 check_vmcs_write(VMCS_ENTRY_EXCP_ERR, err_code);
784 idt_vec_info.undef = 0;
785 check_vmcs_write(VMCS_ENTRY_INT_INFO, idt_vec_info.value);
788 struct vmx_entry_int_info ent_int;
791 switch (v3_intr_pending(info)) {
792 case V3_EXTERNAL_IRQ: {
793 info->intr_core_state.irq_vector = v3_get_intr(info);
794 ent_int.vector = info->intr_core_state.irq_vector;
796 ent_int.error_code = 0;
799 #ifdef V3_CONFIG_DEBUG_INTERRUPTS
800 V3_Print("Injecting Interrupt %d at exit %u(EIP=%p)\n",
801 info->intr_core_state.irq_vector,
802 (uint32_t)info->num_exits,
803 (void *)(addr_t)info->rip);
806 check_vmcs_write(VMCS_ENTRY_INT_INFO, ent_int.value);
807 info->intr_core_state.irq_started = 1;
812 PrintDebug("Injecting NMI\n");
817 check_vmcs_write(VMCS_ENTRY_INT_INFO, ent_int.value);
820 case V3_SOFTWARE_INTR:
821 PrintDebug("Injecting software interrupt\n");
825 check_vmcs_write(VMCS_ENTRY_INT_INFO, ent_int.value);
829 // Not sure what to do here, Intel doesn't have virtual IRQs
830 // May be the same as external interrupts/IRQs
833 case V3_INVALID_INTR:
838 } else if ((v3_intr_pending(info)) && (vmx_info->pri_proc_ctrls.int_wndw_exit == 0)) {
839 // Enable INTR window exiting so we know when IF=1
842 check_vmcs_read(VMCS_EXIT_INSTR_LEN, &instr_len);
844 #ifdef V3_CONFIG_DEBUG_INTERRUPTS
845 V3_Print("Enabling Interrupt-Window exiting: %d\n", instr_len);
848 vmx_info->pri_proc_ctrls.int_wndw_exit = 1;
849 check_vmcs_write(VMCS_PROC_CTRLS, vmx_info->pri_proc_ctrls.value);
858 static struct vmx_exit_info exit_log[10];
859 static uint64_t rip_log[10];
863 static void print_exit_log(struct guest_info * info) {
864 int cnt = info->num_exits % 10;
868 V3_Print("\nExit Log (%d total exits):\n", (uint32_t)info->num_exits);
870 for (i = 0; i < 10; i++) {
871 struct vmx_exit_info * tmp = &exit_log[cnt];
873 V3_Print("%d:\texit_reason = %p\n", i, (void *)(addr_t)tmp->exit_reason);
874 V3_Print("\texit_qual = %p\n", (void *)tmp->exit_qual);
875 V3_Print("\tint_info = %p\n", (void *)(addr_t)tmp->int_info);
876 V3_Print("\tint_err = %p\n", (void *)(addr_t)tmp->int_err);
877 V3_Print("\tinstr_info = %p\n", (void *)(addr_t)tmp->instr_info);
878 V3_Print("\tguest_linear_addr= %p\n", (void *)(addr_t)tmp->guest_linear_addr);
879 V3_Print("\tRIP = %p\n", (void *)rip_log[cnt]);
893 v3_vmx_config_tsc_virtualization(struct guest_info * info) {
894 struct vmx_data * vmx_info = (struct vmx_data *)(info->vmm_data);
896 if (info->time_state.flags & VM_TIME_TRAP_RDTSC) {
897 if (!vmx_info->pri_proc_ctrls.rdtsc_exit) {
898 vmx_info->pri_proc_ctrls.rdtsc_exit = 1;
899 check_vmcs_write(VMCS_PROC_CTRLS, vmx_info->pri_proc_ctrls.value);
903 uint32_t tsc_offset_low, tsc_offset_high;
905 if (vmx_info->pri_proc_ctrls.rdtsc_exit) {
906 vmx_info->pri_proc_ctrls.rdtsc_exit = 0;
907 check_vmcs_write(VMCS_PROC_CTRLS, vmx_info->pri_proc_ctrls.value);
910 if (info->time_state.flags & VM_TIME_TSC_PASSTHROUGH) {
913 tsc_offset = v3_tsc_host_offset(&info->time_state);
915 tsc_offset_high = (uint32_t)(( tsc_offset >> 32) & 0xffffffff);
916 tsc_offset_low = (uint32_t)(tsc_offset & 0xffffffff);
918 check_vmcs_write(VMCS_TSC_OFFSET_HIGH, tsc_offset_high);
919 check_vmcs_write(VMCS_TSC_OFFSET, tsc_offset_low);
925 * CAUTION and DANGER!!!
927 * The VMCS CANNOT(!!) be accessed outside of the cli/sti calls inside this function
928 * When exectuing a symbiotic call, the VMCS WILL be overwritten, so any dependencies
929 * on its contents will cause things to break. The contents at the time of the exit WILL
930 * change before the exit handler is executed.
932 int v3_vmx_enter(struct guest_info * info) {
934 struct vmx_exit_info exit_info;
935 struct vmx_data * vmx_info = (struct vmx_data *)(info->vmm_data);
936 uint64_t guest_cycles = 0;
938 // Conditionally yield the CPU if the timeslice has expired
941 // Update timer devices late after being in the VM so that as much
942 // of the time in the VM is accounted for as possible. Also do it before
943 // updating IRQ entry state so that any interrupts the timers raise get
944 // handled on the next VM entry.
945 v3_advance_time(info, NULL);
946 v3_update_timers(info);
948 // disable global interrupts for vm state transition
951 if (vmcs_store() != vmx_info->vmcs_ptr_phys) {
952 vmcs_clear(vmx_info->vmcs_ptr_phys);
953 vmcs_load(vmx_info->vmcs_ptr_phys);
954 vmx_info->state = VMX_UNLAUNCHED;
957 v3_vmx_restore_vmcs(info);
960 #ifdef V3_CONFIG_SYMCALL
961 if (info->sym_core_state.symcall_state.sym_call_active == 0) {
962 update_irq_entry_state(info);
965 update_irq_entry_state(info);
970 vmcs_read(VMCS_GUEST_CR3, &guest_cr3);
971 vmcs_write(VMCS_GUEST_CR3, guest_cr3);
975 // Perform last-minute time setup prior to entering the VM
976 v3_vmx_config_tsc_virtualization(info);
978 if (v3_update_vmcs_host_state(info)) {
980 PrintError("Could not write host state\n");
984 if (vmx_info->pin_ctrls.active_preempt_timer) {
985 /* Preemption timer is active */
986 uint32_t preempt_window = 0xffffffff;
988 if (info->timeouts.timeout_active) {
989 preempt_window = info->timeouts.next_timeout;
992 check_vmcs_write(VMCS_PREEMPT_TIMER, preempt_window);
997 uint64_t entry_tsc = 0;
998 uint64_t exit_tsc = 0;
1000 if (vmx_info->state == VMX_UNLAUNCHED) {
1001 vmx_info->state = VMX_LAUNCHED;
1003 ret = v3_vmx_launch(&(info->vm_regs), info, &(info->ctrl_regs));
1007 V3_ASSERT(vmx_info->state != VMX_UNLAUNCHED);
1009 ret = v3_vmx_resume(&(info->vm_regs), info, &(info->ctrl_regs));
1013 guest_cycles = exit_tsc - entry_tsc;
1016 // PrintDebug("VMX Exit: ret=%d\n", ret);
1018 if (ret != VMX_SUCCESS) {
1020 vmcs_read(VMCS_INSTR_ERR, &error);
1024 PrintError("VMENTRY Error: %d (launch_ret = %d)\n", error, ret);
1031 /* If we have the preemption time, then use it to get more accurate guest time */
1032 if (vmx_info->pin_ctrls.active_preempt_timer) {
1033 uint32_t cycles_left = 0;
1034 check_vmcs_read(VMCS_PREEMPT_TIMER, &(cycles_left));
1036 if (info->timeouts.timeout_active) {
1037 guest_cycles = info->timeouts.next_timeout - cycles_left;
1039 guest_cycles = 0xffffffff - cycles_left;
1043 // Immediate exit from VM time bookkeeping
1044 v3_advance_time(info, &guest_cycles);
1046 /* Update guest state */
1047 v3_vmx_save_vmcs(info);
1049 // info->cpl = info->segments.cs.selector & 0x3;
1051 info->mem_mode = v3_get_vm_mem_mode(info);
1052 info->cpu_mode = v3_get_vm_cpu_mode(info);
1056 check_vmcs_read(VMCS_EXIT_INSTR_LEN, &(exit_info.instr_len));
1057 check_vmcs_read(VMCS_EXIT_INSTR_INFO, &(exit_info.instr_info));
1058 check_vmcs_read(VMCS_EXIT_REASON, &(exit_info.exit_reason));
1059 check_vmcs_read(VMCS_EXIT_QUAL, &(exit_info.exit_qual));
1060 check_vmcs_read(VMCS_EXIT_INT_INFO, &(exit_info.int_info));
1061 check_vmcs_read(VMCS_EXIT_INT_ERR, &(exit_info.int_err));
1062 check_vmcs_read(VMCS_GUEST_LINEAR_ADDR, &(exit_info.guest_linear_addr));
1064 if (info->shdw_pg_mode == NESTED_PAGING) {
1065 check_vmcs_read(VMCS_GUEST_PHYS_ADDR, &(exit_info.ept_fault_addr));
1068 //PrintDebug("VMX Exit taken, id-qual: %u-%lu\n", exit_info.exit_reason, exit_info.exit_qual);
1070 exit_log[info->num_exits % 10] = exit_info;
1071 rip_log[info->num_exits % 10] = get_addr_linear(info, info->rip, &(info->segments.cs));
1073 #ifdef V3_CONFIG_SYMCALL
1074 if (info->sym_core_state.symcall_state.sym_call_active == 0) {
1075 update_irq_exit_state(info);
1078 update_irq_exit_state(info);
1081 if (exit_info.exit_reason == VMX_EXIT_INTR_WINDOW) {
1082 // This is a special case whose only job is to inject an interrupt
1083 vmcs_read(VMCS_PROC_CTRLS, &(vmx_info->pri_proc_ctrls.value));
1084 vmx_info->pri_proc_ctrls.int_wndw_exit = 0;
1085 vmcs_write(VMCS_PROC_CTRLS, vmx_info->pri_proc_ctrls.value);
1087 #ifdef V3_CONFIG_DEBUG_INTERRUPTS
1088 V3_Print("Interrupts available again! (RIP=%llx)\n", info->rip);
1092 // reenable global interrupts after vm exit
1095 // Conditionally yield the CPU if the timeslice has expired
1096 v3_yield_cond(info);
1097 v3_advance_time(info, NULL);
1098 v3_update_timers(info);
1100 if (v3_handle_vmx_exit(info, &exit_info) == -1) {
1101 PrintError("Error in VMX exit handler (Exit reason=%x)\n", exit_info.exit_reason);
1105 if (info->timeouts.timeout_active) {
1106 /* Check to see if any timeouts have expired */
1107 v3_handle_timeouts(info, guest_cycles);
1114 int v3_start_vmx_guest(struct guest_info * info) {
1116 PrintDebug("Starting VMX core %u\n", info->vcpu_id);
1118 if (info->vcpu_id == 0) {
1119 info->core_run_state = CORE_RUNNING;
1122 PrintDebug("VMX core %u: Waiting for core initialization\n", info->vcpu_id);
1124 while (info->core_run_state == CORE_STOPPED) {
1126 if (info->vm_info->run_state == VM_STOPPED) {
1127 // The VM was stopped before this core was initialized.
1132 //PrintDebug("VMX core %u: still waiting for INIT\n",info->vcpu_id);
1135 PrintDebug("VMX core %u initialized\n", info->vcpu_id);
1137 // We'll be paranoid about race conditions here
1138 v3_wait_at_barrier(info);
1142 PrintDebug("VMX core %u: I am starting at CS=0x%x (base=0x%p, limit=0x%x), RIP=0x%p\n",
1143 info->vcpu_id, info->segments.cs.selector, (void *)(info->segments.cs.base),
1144 info->segments.cs.limit, (void *)(info->rip));
1147 PrintDebug("VMX core %u: Launching VMX VM on logical core %u\n", info->vcpu_id, info->pcpu_id);
1149 v3_start_time(info);
1153 if (info->vm_info->run_state == VM_STOPPED) {
1154 info->core_run_state = CORE_STOPPED;
1158 if (v3_vmx_enter(info) == -1) {
1161 addr_t linear_addr = 0;
1163 info->vm_info->run_state = VM_ERROR;
1165 V3_Print("VMX core %u: VMX ERROR!!\n", info->vcpu_id);
1167 v3_print_guest_state(info);
1169 V3_Print("VMX core %u\n", info->vcpu_id);
1171 linear_addr = get_addr_linear(info, info->rip, &(info->segments.cs));
1173 if (info->mem_mode == PHYSICAL_MEM) {
1174 v3_gpa_to_hva(info, linear_addr, &host_addr);
1175 } else if (info->mem_mode == VIRTUAL_MEM) {
1176 v3_gva_to_hva(info, linear_addr, &host_addr);
1179 V3_Print("VMX core %u: Host Address of rip = 0x%p\n", info->vcpu_id, (void *)host_addr);
1181 V3_Print("VMX core %u: Instr (15 bytes) at %p:\n", info->vcpu_id, (void *)host_addr);
1182 v3_dump_mem((uint8_t *)host_addr, 15);
1184 v3_print_stack(info);
1188 print_exit_log(info);
1192 v3_wait_at_barrier(info);
1195 if (info->vm_info->run_state == VM_STOPPED) {
1196 info->core_run_state = CORE_STOPPED;
1200 if ((info->num_exits % 5000) == 0) {
1201 V3_Print("VMX Exit number %d\n", (uint32_t)info->num_exits);
1213 #define VMX_FEATURE_CONTROL_MSR 0x0000003a
1214 #define CPUID_VMX_FEATURES 0x00000005 /* LOCK and VMXON */
1215 #define CPUID_1_ECX_VTXFLAG 0x00000020
1217 int v3_is_vmx_capable() {
1218 v3_msr_t feature_msr;
1219 uint32_t eax = 0, ebx = 0, ecx = 0, edx = 0;
1221 v3_cpuid(0x1, &eax, &ebx, &ecx, &edx);
1223 PrintDebug("ECX: 0x%x\n", ecx);
1225 if (ecx & CPUID_1_ECX_VTXFLAG) {
1226 v3_get_msr(VMX_FEATURE_CONTROL_MSR, &(feature_msr.hi), &(feature_msr.lo));
1228 PrintDebug("MSRREGlow: 0x%.8x\n", feature_msr.lo);
1230 if ((feature_msr.lo & CPUID_VMX_FEATURES) != CPUID_VMX_FEATURES) {
1231 PrintDebug("VMX is locked -- enable in the BIOS\n");
1236 PrintDebug("VMX not supported on this cpu\n");
1244 int v3_reset_vmx_vm_core(struct guest_info * core, addr_t rip) {
1247 if ((core->shdw_pg_mode == NESTED_PAGING) &&
1248 (v3_mach_type == V3_VMX_EPT_UG_CPU)) {
1251 core->segments.cs.selector = rip << 8;
1252 core->segments.cs.limit = 0xffff;
1253 core->segments.cs.base = rip << 12;
1255 core->vm_regs.rdx = core->vcpu_id;
1256 core->vm_regs.rbx = rip;
1264 void v3_init_vmx_cpu(int cpu_id) {
1265 addr_t vmx_on_region = 0;
1266 extern v3_cpu_arch_t v3_mach_type;
1267 extern v3_cpu_arch_t v3_cpu_types[];
1269 if (v3_mach_type == V3_INVALID_CPU) {
1270 if (v3_init_vmx_hw(&hw_info) == -1) {
1271 PrintError("Could not initialize VMX hardware features on cpu %d\n", cpu_id);
1279 // Setup VMXON Region
1280 vmx_on_region = allocate_vmcs();
1283 if (vmx_on(vmx_on_region) == VMX_SUCCESS) {
1284 V3_Print("VMX Enabled\n");
1285 host_vmcs_ptrs[cpu_id] = vmx_on_region;
1287 V3_Print("VMX already enabled\n");
1288 V3_FreePages((void *)vmx_on_region, 1);
1291 PrintDebug("VMXON pointer: 0x%p\n", (void *)host_vmcs_ptrs[cpu_id]);
1294 struct vmx_sec_proc_ctrls sec_proc_ctrls;
1295 sec_proc_ctrls.value = v3_vmx_get_ctrl_features(&(hw_info.sec_proc_ctrls));
1297 if (sec_proc_ctrls.enable_ept == 0) {
1298 V3_Print("VMX EPT (Nested) Paging not supported\n");
1299 v3_cpu_types[cpu_id] = V3_VMX_CPU;
1300 } else if (sec_proc_ctrls.unrstrct_guest == 0) {
1301 V3_Print("VMX EPT (Nested) Paging supported\n");
1302 v3_cpu_types[cpu_id] = V3_VMX_EPT_CPU;
1304 V3_Print("VMX EPT (Nested) Paging + Unrestricted guest supported\n");
1305 v3_cpu_types[cpu_id] = V3_VMX_EPT_UG_CPU;
1312 void v3_deinit_vmx_cpu(int cpu_id) {
1313 extern v3_cpu_arch_t v3_cpu_types[];
1314 v3_cpu_types[cpu_id] = V3_INVALID_CPU;
1316 if (host_vmcs_ptrs[cpu_id] != 0) {
1317 V3_Print("Disabling VMX\n");
1319 if (vmx_off() != VMX_SUCCESS) {
1320 PrintError("Error executing VMXOFF\n");
1323 V3_FreePages((void *)host_vmcs_ptrs[cpu_id], 1);
1325 host_vmcs_ptrs[cpu_id] = 0;