2 * This file is part of the Palacios Virtual Machine Monitor developed
3 * by the V3VEE Project with funding from the United States National
4 * Science Foundation and the Department of Energy.
6 * The V3VEE Project is a joint project between Northwestern University
7 * and the University of New Mexico. You can find out more at
10 * Copyright (c) 2008, Peter Dinda <pdinda@northwestern.edu>
11 * Copyright (c) 2008, Jack Lange <jarusl@cs.northwestern.edu>
12 * Copyright (c) 2008, The V3VEE Project <http://www.v3vee.org>
13 * All rights reserved.
15 * Author: Peter Dinda <pdinda@northwestern.edu>
16 * Jack Lange <jarusl@cs.northwestern.edu>
18 * This is free software. You are permitted to use,
19 * redistribute, and modify it as specified in the file "V3VEE_LICENSE".
23 #include <palacios/vmx.h>
24 #include <palacios/vmcs.h>
25 #include <palacios/vmm.h>
26 #include <palacios/vmx_lowlevel.h>
27 #include <palacios/vmm_lowlevel.h>
28 #include <palacios/vmm_config.h>
29 #include <palacios/vmm_ctrl_regs.h>
30 #include <palacios/vm_guest_mem.h>
31 #include <palacios/vmm_direct_paging.h>
32 #include <palacios/vmx_io.h>
33 #include <palacios/vmx_msr.h>
35 static addr_t vmxon_ptr_phys;
36 extern int v3_vmx_exit_handler();
37 extern int v3_vmx_vmlaunch(struct v3_gprs * vm_regs, struct guest_info * info);
39 static int inline check_vmcs_write(vmcs_field_t field, addr_t val)
42 ret = vmcs_write(field,val);
44 if (ret != VMX_SUCCESS) {
45 PrintError("VMWRITE error on %s!: %d\n", v3_vmcs_field_to_str(field), ret);
52 static void inline translate_segment_access(struct v3_segment * v3_seg,
53 struct vmcs_segment_access * access)
55 access->type = v3_seg->type;
56 access->desc_type = v3_seg->system;
57 access->dpl = v3_seg->dpl;
58 access->present = v3_seg->present;
59 access->avail = v3_seg->avail;
60 access->long_mode = v3_seg->long_mode;
61 access->db = v3_seg->db;
62 access->granularity = v3_seg->granularity;
65 static int update_vmcs_ctrl_fields(struct guest_info * info) {
67 struct vmx_data * arch_data = (struct vmx_data *)(info->vmm_data);
69 vmx_ret |= check_vmcs_write(VMCS_PIN_CTRLS, arch_data->pinbased_ctrls);
70 vmx_ret |= check_vmcs_write(VMCS_PROC_CTRLS, arch_data->pri_procbased_ctrls);
72 if(arch_data->pri_procbased_ctrls & ACTIVE_SEC_CTRLS) {
73 vmx_ret |= check_vmcs_write(VMCS_SEC_PROC_CTRLS, arch_data->sec_procbased_ctrls);
76 vmx_ret |= check_vmcs_write(VMCS_EXIT_CTRLS, arch_data->exit_ctrls);
77 vmx_ret |= check_vmcs_write(VMCS_ENTRY_CTRLS, arch_data->entry_ctrls);
78 vmx_ret |= check_vmcs_write(VMCS_EXCP_BITMAP, arch_data->excp_bitmap);
83 static int update_vmcs_host_state(struct guest_info * info) {
86 struct vmx_data * arch_data = (struct vmx_data *)(info->vmm_data);
87 struct v3_msr tmp_msr;
89 __asm__ __volatile__ ( "movq %%cr0, %0; "
93 vmx_ret |= check_vmcs_write(VMCS_HOST_CR0, tmp);
96 __asm__ __volatile__ ( "movq %%cr3, %0; "
100 vmx_ret |= check_vmcs_write(VMCS_HOST_CR3, tmp);
103 __asm__ __volatile__ ( "movq %%cr4, %0; "
107 vmx_ret |= check_vmcs_write(VMCS_HOST_CR4, tmp);
111 vmx_ret |= check_vmcs_write(VMCS_HOST_GDTR_BASE, arch_data->host_state.gdtr.base);
112 vmx_ret |= check_vmcs_write(VMCS_HOST_IDTR_BASE, arch_data->host_state.idtr.base);
113 vmx_ret |= check_vmcs_write(VMCS_HOST_TR_BASE, arch_data->host_state.tr.base);
115 #define FS_BASE_MSR 0xc0000100
116 #define GS_BASE_MSR 0xc0000101
119 v3_get_msr(FS_BASE_MSR, &(tmp_msr.hi), &(tmp_msr.lo));
120 vmx_ret |= check_vmcs_write(VMCS_HOST_FS_BASE, tmp_msr.value);
123 v3_get_msr(GS_BASE_MSR, &(tmp_msr.hi), &(tmp_msr.lo));
124 vmx_ret |= check_vmcs_write(VMCS_HOST_GS_BASE, tmp_msr.value);
128 __asm__ __volatile__ ( "movq %%cs, %0; "
132 vmx_ret |= check_vmcs_write(VMCS_HOST_CS_SELECTOR, tmp);
134 __asm__ __volatile__ ( "movq %%ss, %0; "
138 vmx_ret |= check_vmcs_write(VMCS_HOST_SS_SELECTOR, tmp);
140 __asm__ __volatile__ ( "movq %%ds, %0; "
144 vmx_ret |= check_vmcs_write(VMCS_HOST_DS_SELECTOR, tmp);
146 __asm__ __volatile__ ( "movq %%es, %0; "
150 vmx_ret |= check_vmcs_write(VMCS_HOST_ES_SELECTOR, tmp);
152 __asm__ __volatile__ ( "movq %%fs, %0; "
156 vmx_ret |= check_vmcs_write(VMCS_HOST_FS_SELECTOR, tmp);
158 __asm__ __volatile__ ( "movq %%gs, %0; "
162 vmx_ret |= check_vmcs_write(VMCS_HOST_GS_SELECTOR, tmp);
164 vmx_ret |= check_vmcs_write(VMCS_HOST_TR_SELECTOR, arch_data->host_state.tr.selector);
167 #define SYSENTER_CS_MSR 0x00000174
168 #define SYSENTER_ESP_MSR 0x00000175
169 #define SYSENTER_EIP_MSR 0x00000176
172 v3_get_msr(SYSENTER_CS_MSR, &(tmp_msr.hi), &(tmp_msr.lo));
173 vmx_ret |= check_vmcs_write(VMCS_HOST_SYSENTER_CS, tmp_msr.lo);
176 v3_get_msr(SYSENTER_ESP_MSR, &(tmp_msr.hi), &(tmp_msr.lo));
177 vmx_ret |= check_vmcs_write(VMCS_HOST_SYSENTER_ESP, tmp_msr.value);
180 v3_get_msr(SYSENTER_EIP_MSR, &(tmp_msr.hi), &(tmp_msr.lo));
181 vmx_ret |= check_vmcs_write(VMCS_HOST_SYSENTER_EIP, tmp_msr.value);
187 static int inline update_vmcs_guest_state(struct guest_info * info)
189 struct v3_msr tmp_msr;
192 vmx_ret |= check_vmcs_write(VMCS_GUEST_RIP, info->rip);
193 vmx_ret |= check_vmcs_write(VMCS_GUEST_RSP, info->vm_regs.rsp);
196 vmx_ret |= check_vmcs_write(VMCS_GUEST_CR0, info->ctrl_regs.cr0);
197 vmx_ret |= check_vmcs_write(VMCS_GUEST_CR3, info->ctrl_regs.cr3);
198 vmx_ret |= check_vmcs_write(VMCS_GUEST_CR4, info->ctrl_regs.cr4);
200 vmx_ret |= check_vmcs_write(VMCS_GUEST_RFLAGS, info->ctrl_regs.rflags);
201 #define DEBUGCTL_MSR 0x1d9
203 v3_get_msr(DEBUGCTL_MSR, &(tmp_msr.hi), &(tmp_msr.lo));
204 vmx_ret |= check_vmcs_write(VMCS_GUEST_DBG_CTL, tmp_msr.value);
206 vmx_ret |= check_vmcs_write(VMCS_GUEST_DR7, 0x400);
208 vmx_ret |= check_vmcs_write(VMCS_LINK_PTR, 0xffffffffffffffff);
211 /*** Write VMCS Segments ***/
212 struct vmcs_segment_access access;
214 memset(&access, 0, sizeof(access));
217 translate_segment_access(&(info->segments.cs), &access);
219 vmx_ret |= check_vmcs_write(VMCS_GUEST_CS_BASE, info->segments.cs.base);
220 vmx_ret |= check_vmcs_write(VMCS_GUEST_CS_SELECTOR, info->segments.cs.selector);
221 vmx_ret |= check_vmcs_write(VMCS_GUEST_CS_LIMIT, info->segments.cs.limit);
222 vmx_ret |= check_vmcs_write(VMCS_GUEST_CS_ACCESS, access.value);
225 translate_segment_access(&(info->segments.ss), &access);
227 vmx_ret |= check_vmcs_write(VMCS_GUEST_SS_BASE, info->segments.ss.base);
228 vmx_ret |= check_vmcs_write(VMCS_GUEST_SS_SELECTOR, info->segments.ss.selector);
229 vmx_ret |= check_vmcs_write(VMCS_GUEST_SS_LIMIT, info->segments.ss.limit);
230 vmx_ret |= check_vmcs_write(VMCS_GUEST_SS_ACCESS, access.value);
233 translate_segment_access(&(info->segments.ds), &access);
235 vmx_ret |= check_vmcs_write(VMCS_GUEST_DS_BASE, info->segments.ds.base);
236 vmx_ret |= check_vmcs_write(VMCS_GUEST_DS_SELECTOR, info->segments.ds.selector);
237 vmx_ret |= check_vmcs_write(VMCS_GUEST_DS_LIMIT, info->segments.ds.limit);
238 vmx_ret |= check_vmcs_write(VMCS_GUEST_DS_ACCESS, access.value);
242 translate_segment_access(&(info->segments.es), &access);
244 vmx_ret |= check_vmcs_write(VMCS_GUEST_ES_BASE, info->segments.es.base);
245 vmx_ret |= check_vmcs_write(VMCS_GUEST_ES_SELECTOR, info->segments.es.selector);
246 vmx_ret |= check_vmcs_write(VMCS_GUEST_ES_LIMIT, info->segments.es.limit);
247 vmx_ret |= check_vmcs_write(VMCS_GUEST_ES_ACCESS, access.value);
250 translate_segment_access(&(info->segments.fs), &access);
252 vmx_ret |= check_vmcs_write(VMCS_GUEST_FS_BASE, info->segments.fs.base);
253 vmx_ret |= check_vmcs_write(VMCS_GUEST_FS_SELECTOR, info->segments.fs.selector);
254 vmx_ret |= check_vmcs_write(VMCS_GUEST_FS_LIMIT, info->segments.fs.limit);
255 vmx_ret |= check_vmcs_write(VMCS_GUEST_FS_ACCESS, access.value);
258 translate_segment_access(&(info->segments.gs), &access);
260 vmx_ret |= check_vmcs_write(VMCS_GUEST_GS_BASE, info->segments.gs.base);
261 vmx_ret |= check_vmcs_write(VMCS_GUEST_GS_SELECTOR, info->segments.gs.selector);
262 vmx_ret |= check_vmcs_write(VMCS_GUEST_GS_LIMIT, info->segments.gs.limit);
263 vmx_ret |= check_vmcs_write(VMCS_GUEST_GS_ACCESS, access.value);
266 translate_segment_access(&(info->segments.ldtr), &access);
268 vmx_ret |= check_vmcs_write(VMCS_GUEST_LDTR_BASE, info->segments.ldtr.base);
269 vmx_ret |= check_vmcs_write(VMCS_GUEST_LDTR_SELECTOR, info->segments.ldtr.selector);
270 vmx_ret |= check_vmcs_write(VMCS_GUEST_LDTR_LIMIT, info->segments.ldtr.limit);
271 vmx_ret |= check_vmcs_write(VMCS_GUEST_LDTR_ACCESS, access.value);
274 translate_segment_access(&(info->segments.tr), &access);
276 vmx_ret |= check_vmcs_write(VMCS_GUEST_TR_BASE, info->segments.tr.base);
277 vmx_ret |= check_vmcs_write(VMCS_GUEST_TR_SELECTOR, info->segments.tr.selector);
278 vmx_ret |= check_vmcs_write(VMCS_GUEST_TR_LIMIT, info->segments.tr.limit);
279 vmx_ret |= check_vmcs_write(VMCS_GUEST_TR_ACCESS, access.value);
283 vmx_ret |= check_vmcs_write(VMCS_GUEST_GDTR_BASE, info->segments.gdtr.base);
284 vmx_ret |= check_vmcs_write(VMCS_GUEST_GDTR_LIMIT, info->segments.gdtr.limit);
287 vmx_ret |= check_vmcs_write(VMCS_GUEST_IDTR_BASE, info->segments.idtr.base);
288 vmx_ret |= check_vmcs_write(VMCS_GUEST_IDTR_LIMIT, info->segments.idtr.limit);
298 // For the 32 bit reserved bit fields
299 // MB1s are in the low 32 bits, MBZs are in the high 32 bits of the MSR
300 static uint32_t sanitize_bits1(uint32_t msr_num, uint32_t val) {
303 PrintDebug("sanitize_bits1 (MSR:%x)\n", msr_num);
305 v3_get_msr(msr_num, &mask_msr.hi, &mask_msr.lo);
307 PrintDebug("MSR %x = %x : %x \n", msr_num, mask_msr.hi, mask_msr.lo);
317 static addr_t sanitize_bits2(uint32_t msr_num0, uint32_t msr_num1, addr_t val) {
319 addr_t msr0_val, msr1_val;
321 PrintDebug("sanitize_bits2 (MSR0=%x, MSR1=%x)\n", msr_num0, msr_num1);
323 v3_get_msr(msr_num0, &msr0.hi, &msr0.lo);
324 v3_get_msr(msr_num1, &msr1.hi, &msr1.lo);
326 // This generates a mask that is the natural bit width of the CPU
327 msr0_val = msr0.value;
328 msr1_val = msr1.value;
330 PrintDebug("MSR %x = %p, %x = %p \n", msr_num0, (void*)msr0_val, msr_num1, (void*)msr1_val);
343 static addr_t allocate_vmcs()
346 PrintDebug("Allocating page\n");
347 struct vmcs_data * vmcs_page = (struct vmcs_data *)V3_VAddr(V3_AllocPages(1));
350 memset(vmcs_page, 0, 4096);
352 v3_get_msr(VMX_BASIC_MSR, &(msr.e_reg.high), &(msr.e_reg.low));
354 vmcs_page->revision = ((struct vmx_basic_msr*)&msr)->revision;
355 PrintDebug("VMX Revision: 0x%x\n",vmcs_page->revision);
357 return (addr_t)V3_PAddr((void *)vmcs_page);
361 static void setup_v8086_mode_for_boot(struct guest_info * vm_info)
364 ((struct vmx_data *)vm_info->vmm_data)->state = VMXASSIST_V8086_BIOS;
365 struct rflags * flags = (struct rflags *)&(vm_info->ctrl_regs.rflags);
370 #define GUEST_CR0_MASK 0x80000021
371 #define GUEST_CR4_MASK 0x00002000
372 vm_info->ctrl_regs.cr0 = GUEST_CR0_MASK;
373 vm_info->ctrl_regs.cr4 = GUEST_CR4_MASK;
375 vm_info->rip = 0xd0000;
376 vm_info->vm_regs.rsp = 0x80000;
378 vm_info->segments.cs.selector = 0xf000;
379 vm_info->segments.cs.base = 0xf000 << 4;
380 vm_info->segments.cs.limit = 0xffff;
381 vm_info->segments.cs.type = 3;
382 vm_info->segments.cs.system = 1;
383 vm_info->segments.cs.dpl = 3;
384 vm_info->segments.cs.present = 1;
385 vm_info->segments.cs.granularity = 0;
388 struct v3_segment * seg_ptr = (struct v3_segment *)&(vm_info->segments);
390 /* Set values for selectors ds through ss */
391 for(i = 1; i < 6 ; i++) {
392 seg_ptr[i].selector = 0x0000;
393 seg_ptr[i].base = 0x00000;
394 seg_ptr[i].limit = 0xffff;
397 for(i = 6; i < 10; i++) {
398 seg_ptr[i].base = 0x0;
399 seg_ptr[i].limit = 0xffff;
402 vm_info->segments.ldtr.selector = 0x0;
403 vm_info->segments.ldtr.type = 2;
404 vm_info->segments.ldtr.system = 0;
405 vm_info->segments.ldtr.present = 1;
406 vm_info->segments.ldtr.granularity = 0;
408 vm_info->segments.tr.selector = 0x0;
409 vm_info->segments.tr.type = 3;
410 vm_info->segments.tr.system = 0;
411 vm_info->segments.tr.present = 1;
412 vm_info->segments.tr.granularity = 0;
417 static int init_vmcs_bios(struct guest_info * vm_info)
421 setup_v8086_mode_for_boot(vm_info);
425 // TODO: This is not 32-bit safe!
426 vmx_ret |= check_vmcs_write(VMCS_GUEST_RIP, vm_info->rip);
427 vmx_ret |= check_vmcs_write(VMCS_GUEST_RSP, vm_info->vm_regs.rsp);
430 vmx_ret |= check_vmcs_write(VMCS_GUEST_CR0, vm_info->ctrl_regs.cr0);
431 vmx_ret |= check_vmcs_write(VMCS_GUEST_CR4, vm_info->ctrl_regs.cr4);
433 vmx_ret |= vmcs_write_guest_segments(vm_info);
435 vmx_ret |= check_vmcs_write(VMCS_GUEST_RFLAGS, vm_info->ctrl_regs.rflags);
436 #define DEBUGCTL_MSR 0x1d9
438 v3_get_msr(DEBUGCTL_MSR, &(tmp_msr.hi), &(tmp_msr.lo));
439 vmx_ret |= check_vmcs_write(VMCS_GUEST_DBG_CTL, tmp_msr.value);
441 vmx_ret |= check_vmcs_write(VMCS_GUEST_DR7, 0x400);
443 vmx_ret |= check_vmcs_write(VMCS_LINK_PTR, 0xffffffffffffffff);
446 PrintError("Could not initialize VMCS segments\n");
455 static int init_vmx_guest(struct guest_info * info, struct v3_vm_config * config_ptr) {
456 v3_pre_config_guest(info, config_ptr);
458 struct vmx_data * vmx_data = NULL;
460 vmx_data = (struct vmx_data *)V3_Malloc(sizeof(struct vmx_data));
462 PrintDebug("vmx_data pointer: %p\n", (void *)vmx_data);
464 PrintDebug("Allocating VMCS\n");
465 vmx_data->vmcs_ptr_phys = allocate_vmcs();
467 PrintDebug("VMCS pointer: %p\n", (void *)(vmx_data->vmcs_ptr_phys));
469 info->vmm_data = vmx_data;
471 PrintDebug("Initializing VMCS (addr=%p)\n", info->vmm_data);
473 // TODO: Fix vmcs fields so they're 32-bit
476 PrintDebug("Clearing VMCS: %p\n",(void*)vmx_data->vmcs_ptr_phys);
477 vmx_ret = vmcs_clear(vmx_data->vmcs_ptr_phys);
479 if (vmx_ret != VMX_SUCCESS) {
480 PrintError("VMCLEAR failed\n");
484 PrintDebug("Loading VMCS\n");
485 vmx_ret = vmcs_load(vmx_data->vmcs_ptr_phys);
487 if (vmx_ret != VMX_SUCCESS) {
488 PrintError("VMPTRLD failed\n");
494 /******* Setup Host State **********/
496 /* Cache GDTR, IDTR, and TR in host struct */
501 } __attribute__((packed)) tmp_seg;
504 __asm__ __volatile__(
510 gdtr_base = tmp_seg.base;
511 vmx_data->host_state.gdtr.base = gdtr_base;
513 __asm__ __volatile__(
519 vmx_data->host_state.idtr.base = tmp_seg.base;
521 __asm__ __volatile__(
527 vmx_data->host_state.tr.selector = tmp_seg.selector;
529 /* The GDTR *index* is bits 3-15 of the selector. */
530 struct tss_descriptor * desc = (struct tss_descriptor *)
531 (gdtr_base + 8*(tmp_seg.selector>>3));
535 (desc->base2 << 16) |
536 (desc->base3 << 24) |
538 ((uint64_t)desc->base4 << 32)
544 vmx_data->host_state.tr.base = tmp_seg.base;
548 /********** Setup and VMX Control Fields from MSR ***********/
549 struct v3_msr tmp_msr;
551 v3_get_msr(VMX_PINBASED_CTLS_MSR,&(tmp_msr.hi),&(tmp_msr.lo));
552 /* Add NMI exiting */
553 vmx_data->pinbased_ctrls = tmp_msr.lo | NMI_EXIT;
555 v3_get_msr(VMX_PROCBASED_CTLS_MSR, &(tmp_msr.hi), &(tmp_msr.lo));
556 vmx_data->pri_procbased_ctrls = tmp_msr.lo;
558 v3_get_msr(VMX_EXIT_CTLS_MSR, &(tmp_msr.hi), &(tmp_msr.lo));
559 vmx_data->exit_ctrls = tmp_msr.lo | HOST_ADDR_SPACE_SIZE;
561 v3_get_msr(VMX_ENTRY_CTLS_MSR, &(tmp_msr.hi), &(tmp_msr.lo));
562 vmx_data->entry_ctrls = tmp_msr.lo;
564 vmx_data->excp_bitmap = 0xffffffff;
568 /******* Setup VMXAssist guest state ***********/
571 info->vm_regs.rsp = 0x80000;
573 struct rflags * flags = (struct rflags *)&(info->ctrl_regs.rflags);
576 /* Print Control MSRs */
577 v3_get_msr(VMX_CR0_FIXED0_MSR, &(tmp_msr.hi), &(tmp_msr.lo));
578 PrintDebug("CR0 MSR: %p\n", (void*)tmp_msr.value);
579 v3_get_msr(VMX_CR4_FIXED0_MSR, &(tmp_msr.hi), &(tmp_msr.lo));
580 PrintDebug("CR4 MSR: %p\n", (void*)tmp_msr.value);
583 #define GUEST_CR0 0x80000031
584 #define GUEST_CR4 0x00002000
585 info->ctrl_regs.cr0 = GUEST_CR0;
586 info->ctrl_regs.cr4 = GUEST_CR4;
589 if(info->shdw_pg_mode == SHADOW_PAGING) {
590 PrintDebug("Creating initial shadow page table\n");
592 if(v3_init_passthrough_pts(info) == -1) {
593 PrintError("Could not initialize passthrough page tables\n");
597 info->shdw_pg_state.guest_cr0 = 0x10LL;
598 PrintDebug("Created\n");
600 vmx_ret |= check_vmcs_write(VMCS_CR0_MASK, 0xffffffffffffffffLL);
601 vmx_ret |= check_vmcs_write(VMCS_CR4_MASK, 0xffffffffffffffffLL);
603 info->ctrl_regs.cr3 = info->direct_map_pt;
605 /* Add unconditional I/O and CR exits */
606 vmx_data->pri_procbased_ctrls |= UNCOND_IO_EXIT |
612 struct v3_segment * seg_reg = (struct v3_segment *)&(info->segments);
615 for(i=0; i < 10; i++)
617 seg_reg[i].selector = 3<<3;
618 seg_reg[i].limit = 0xffff;
619 seg_reg[i].base = 0x0;
621 info->segments.cs.selector = 2<<3;
623 /* Set only the segment registers */
624 for(i=0; i < 6; i++) {
625 seg_reg[i].limit = 0xfffff;
626 seg_reg[i].granularity = 1;
628 seg_reg[i].system = 1;
630 seg_reg[i].present = 1;
633 info->segments.cs.type = 0xb;
635 info->segments.ldtr.selector = 0x20;
636 info->segments.ldtr.type = 2;
637 info->segments.ldtr.system = 0;
638 info->segments.ldtr.present = 1;
639 info->segments.ldtr.granularity = 0;
642 (void) v3_init_vmx_io_map(info);
643 (void) v3_init_vmx_msr_map(info);
645 /************* Map in GDT and vmxassist *************/
647 uint64_t gdt[] __attribute__ ((aligned(32))) = {
648 0x0000000000000000ULL, /* 0x00: reserved */
649 0x0000830000000000ULL, /* 0x08: 32-bit TSS */
650 // 0x0000890000000000ULL, /* 0x08: 32-bit TSS */
651 0x00CF9b000000FFFFULL, /* 0x10: CS 32-bit */
652 0x00CF93000000FFFFULL, /* 0x18: DS 32-bit */
653 0x000082000000FFFFULL, /* 0x20: LDTR 32-bit */
656 #define VMXASSIST_GDT 0x10000
657 addr_t vmxassist_gdt = 0;
658 if(guest_pa_to_host_va(info, VMXASSIST_GDT, &vmxassist_gdt) == -1) {
659 PrintError("Could not find VMXASSIST GDT destination\n");
662 memcpy((void*)vmxassist_gdt, gdt, sizeof(uint64_t) * 5);
664 info->segments.gdtr.base = VMXASSIST_GDT;
666 #define VMXASSIST_TSS 0x40000
667 addr_t vmxassist_tss = VMXASSIST_TSS;
668 gdt[0x08 / sizeof(gdt[0])] |=
669 ((vmxassist_tss & 0xFF000000) << (56-24)) |
670 ((vmxassist_tss & 0x00FF0000) << (32-16)) |
671 ((vmxassist_tss & 0x0000FFFF) << (16)) |
674 info->segments.tr.selector = 0x08;
675 info->segments.tr.base = vmxassist_tss;
677 // info->segments.tr.type = 0x9;
678 info->segments.tr.type = 0x3;
679 info->segments.tr.system = 0;
680 info->segments.tr.present = 1;
681 info->segments.tr.granularity = 0;
684 #define VMXASSIST_START 0x000d0000
685 extern uint8_t vmxassist_start[];
686 extern uint8_t vmxassist_end[];
688 addr_t vmxassist_dst = 0;
689 if(guest_pa_to_host_va(info, VMXASSIST_START, &vmxassist_dst) == -1) {
690 PrintError("Could not find VMXASSIST destination\n");
693 memcpy((void*)vmxassist_dst, vmxassist_start, vmxassist_end-vmxassist_start);
695 /*** Write all the info to the VMCS ***/
696 if(update_vmcs_ctrl_fields(info)) {
697 PrintError("Could not write control fields!\n");
701 if(update_vmcs_host_state(info)) {
702 PrintError("Could not write host state\n");
707 if(update_vmcs_guest_state(info) != VMX_SUCCESS) {
708 PrintError("Writing guest state failed!\n");
715 v3_post_config_guest(info, config_ptr);
721 static int start_vmx_guest(struct guest_info* info) {
725 PrintDebug("Attempting VMLAUNCH\n");
727 ret = v3_vmx_vmlaunch(&(info->vm_regs), info);
728 if (ret != VMX_SUCCESS) {
729 vmcs_read(VMCS_INSTR_ERR, &error);
730 PrintError("VMLAUNCH failed: %d\n", error);
735 PrintDebug("Returned from VMLAUNCH ret=%d(0x%x)\n", ret, ret);
741 int v3_is_vmx_capable() {
742 v3_msr_t feature_msr;
743 addr_t eax = 0, ebx = 0, ecx = 0, edx = 0;
745 v3_cpuid(0x1, &eax, &ebx, &ecx, &edx);
747 PrintDebug("ECX: %p\n", (void*)ecx);
749 if (ecx & CPUID_1_ECX_VTXFLAG) {
750 v3_get_msr(VMX_FEATURE_CONTROL_MSR, &(feature_msr.hi), &(feature_msr.lo));
752 PrintTrace("MSRREGlow: 0x%.8x\n", feature_msr.lo);
754 if ((feature_msr.lo & FEATURE_CONTROL_VALID) != FEATURE_CONTROL_VALID) {
755 PrintDebug("VMX is locked -- enable in the BIOS\n");
760 PrintDebug("VMX not supported on this cpu\n");
767 static int has_vmx_nested_paging() {
773 void v3_init_vmx(struct v3_ctrl_ops * vm_ops) {
774 extern v3_cpu_arch_t v3_cpu_type;
776 struct v3_msr tmp_msr;
779 v3_get_msr(VMX_CR4_FIXED0_MSR,&(tmp_msr.hi),&(tmp_msr.lo));
781 __asm__ __volatile__ (
783 "orq $0x00002000, %%rbx;"
790 if((~ret & tmp_msr.value) == 0) {
791 __asm__ __volatile__ (
797 PrintError("Invalid CR4 Settings!\n");
800 __asm__ __volatile__ (
801 "movq %%cr0, %%rbx; "
802 "orq $0x00000020,%%rbx; "
809 // Should check and return Error here....
812 // Setup VMXON Region
813 vmxon_ptr_phys = allocate_vmcs();
814 PrintDebug("VMXON pointer: 0x%p\n", (void*)vmxon_ptr_phys);
816 if (v3_enable_vmx(vmxon_ptr_phys) == VMX_SUCCESS) {
817 PrintDebug("VMX Enabled\n");
819 PrintError("VMX initialization failure\n");
824 if (has_vmx_nested_paging() == 1) {
825 v3_cpu_type = V3_VMX_EPT_CPU;
827 v3_cpu_type = V3_VMX_CPU;
830 // Setup the VMX specific vmm operations
831 vm_ops->init_guest = &init_vmx_guest;
832 vm_ops->start_guest = &start_vmx_guest;
833 vm_ops->has_nested_paging = &has_vmx_nested_paging;