2 * This file is part of the Palacios Virtual Machine Monitor developed
3 * by the V3VEE Project with funding from the United States National
4 * Science Foundation and the Department of Energy.
6 * The V3VEE Project is a joint project between Northwestern University
7 * and the University of New Mexico. You can find out more at
10 * Copyright (c) 2008, Jack Lange <jarusl@cs.northwestern.edu>
11 * Copyright (c) 2008, The V3VEE Project <http://www.v3vee.org>
12 * All rights reserved.
14 * Author: Jack Lange <jarusl@cs.northwestern.edu>
16 * This is free software. You are permitted to use,
17 * redistribute, and modify it as specified in the file "V3VEE_LICENSE".
20 #include <palacios/vmm_mem.h>
21 #include <palacios/vmm.h>
22 #include <palacios/vmcb.h>
23 #include <palacios/vmm_decoder.h>
24 #include <palacios/vm_guest_mem.h>
25 #include <palacios/vmm_ctrl_regs.h>
26 #include <palacios/vmm_direct_paging.h>
27 #include <palacios/svm.h>
29 #ifndef V3_CONFIG_DEBUG_CTRL_REGS
31 #define PrintDebug(fmt, args...)
35 static int handle_lmsw(struct guest_info * info, struct x86_instr * dec_instr);
36 static int handle_clts(struct guest_info * info, struct x86_instr * dec_instr);
37 static int handle_mov_to_cr0(struct guest_info * info, struct x86_instr * dec_instr);
40 // First Attempt = 494 lines
41 // current = 106 lines
42 int v3_handle_cr0_write(struct guest_info * info) {
45 struct x86_instr dec_instr;
47 if (info->mem_mode == PHYSICAL_MEM) {
48 ret = v3_read_gpa_memory(info, get_addr_linear(info, info->rip, &(info->segments.cs)), 15, instr);
50 ret = v3_read_gva_memory(info, get_addr_linear(info, info->rip, &(info->segments.cs)), 15, instr);
53 if (v3_decode(info, (addr_t)instr, &dec_instr) == -1) {
54 PrintError(info->vm_info, info, "Could not decode instruction\n");
59 if (dec_instr.op_type == V3_OP_LMSW) {
60 if (handle_lmsw(info, &dec_instr) == -1) {
63 } else if (dec_instr.op_type == V3_OP_MOV2CR) {
64 if (handle_mov_to_cr0(info, &dec_instr) == -1) {
67 } else if (dec_instr.op_type == V3_OP_CLTS) {
68 if (handle_clts(info, &dec_instr) == -1) {
72 PrintError(info->vm_info, info, "Unhandled opcode in handle_cr0_write\n");
76 info->rip += dec_instr.instr_length;
84 // The CR0 register only has flags in the low 32 bits
85 // The hardware does a format check to make sure the high bits are zero
86 // Because of this we can ignore the high 32 bits here
87 static int handle_mov_to_cr0(struct guest_info * info, struct x86_instr * dec_instr) {
89 struct cr0_32 * shadow_cr0 = (struct cr0_32 *)&(info->ctrl_regs.cr0);
90 struct cr0_32 * new_cr0 = (struct cr0_32 *)(dec_instr->src_operand.operand);
91 struct cr0_32 * guest_cr0 = (struct cr0_32 *)&(info->shdw_pg_state.guest_cr0);
92 uint_t paging_transition = 0;
94 PrintDebug(info->vm_info, info, "MOV2CR0 (MODE=%s)\n", v3_cpu_mode_to_str(info->cpu_mode));
96 PrintDebug(info->vm_info, info, "OperandVal = %x, length=%d\n", *(uint_t *)new_cr0, dec_instr->src_operand.size);
98 PrintDebug(info->vm_info, info, "Old CR0=%x\n", *(uint_t *)shadow_cr0);
99 PrintDebug(info->vm_info, info, "Old Guest CR0=%x\n", *(uint_t *)guest_cr0);
102 // We detect if this is a paging transition
103 if (guest_cr0->pg != new_cr0->pg) {
104 paging_transition = 1;
107 // Guest always sees the value they wrote
108 *guest_cr0 = *new_cr0;
110 // This value must always be set to 1
113 // Set the shadow register to catch non-virtualized flags
114 *shadow_cr0 = *guest_cr0;
116 // Paging is always enabled
119 if (guest_cr0->pg == 0) {
120 // If paging is not enabled by the guest, then we always enable write-protect to catch memory hooks
124 // Was there a paging transition
125 // Meaning we need to change the page tables
126 if (paging_transition) {
127 if (v3_get_vm_mem_mode(info) == VIRTUAL_MEM) {
129 struct efer_64 * guest_efer = (struct efer_64 *)&(info->shdw_pg_state.guest_efer);
130 struct efer_64 * shadow_efer = (struct efer_64 *)&(info->ctrl_regs.efer);
132 // Check long mode LME to set LME
133 if (guest_efer->lme == 1) {
134 PrintDebug(info->vm_info, info, "Enabing Long Mode\n");
137 shadow_efer->lma = 1;
138 shadow_efer->lme = 1;
140 PrintDebug(info->vm_info, info, "New EFER %p\n", (void *)*(addr_t *)(shadow_efer));
143 PrintDebug(info->vm_info, info, "Activating Shadow Page Tables\n");
145 if (v3_activate_shadow_pt(info) == -1) {
146 PrintError(info->vm_info, info, "Failed to activate shadow page tables\n");
153 if (v3_activate_passthrough_pt(info) == -1) {
154 PrintError(info->vm_info, info, "Failed to activate passthrough page tables\n");
161 PrintDebug(info->vm_info, info, "New Guest CR0=%x\n",*(uint_t *)guest_cr0);
162 PrintDebug(info->vm_info, info, "New CR0=%x\n", *(uint_t *)shadow_cr0);
170 static int handle_clts(struct guest_info * info, struct x86_instr * dec_instr) {
172 struct cr0_32 * real_cr0 = (struct cr0_32*)&(info->ctrl_regs.cr0);
176 if (info->shdw_pg_mode == SHADOW_PAGING) {
177 struct cr0_32 * guest_cr0 = (struct cr0_32 *)&(info->shdw_pg_state.guest_cr0);
184 static int handle_lmsw(struct guest_info * info, struct x86_instr * dec_instr) {
185 struct cr0_real * real_cr0 = (struct cr0_real *)&(info->ctrl_regs.cr0);
186 // XED is a mess, and basically reverses the operand order for an LMSW
187 struct cr0_real * new_cr0 = (struct cr0_real *)(dec_instr->dst_operand.operand);
190 PrintDebug(info->vm_info, info, "LMSW\n");
192 new_cr0_val = (*(char*)(new_cr0)) & 0x0f;
194 PrintDebug(info->vm_info, info, "OperandVal = %x\n", new_cr0_val);
196 // We can just copy the new value through
197 // we don't need to virtualize the lower 4 bits
198 PrintDebug(info->vm_info, info, "Old CR0=%x\n", *(uint_t *)real_cr0);
199 *(uchar_t*)real_cr0 &= 0xf0;
200 *(uchar_t*)real_cr0 |= new_cr0_val;
201 PrintDebug(info->vm_info, info, "New CR0=%x\n", *(uint_t *)real_cr0);
204 // If Shadow paging is enabled we push the changes to the virtualized copy of cr0
205 if (info->shdw_pg_mode == SHADOW_PAGING) {
206 struct cr0_real * guest_cr0 = (struct cr0_real*)&(info->shdw_pg_state.guest_cr0);
208 PrintDebug(info->vm_info, info, "Old Guest CR0=%x\n", *(uint_t *)guest_cr0);
209 *(uchar_t*)guest_cr0 &= 0xf0;
210 *(uchar_t*)guest_cr0 |= new_cr0_val;
211 PrintDebug(info->vm_info, info, "New Guest CR0=%x\n", *(uint_t *)guest_cr0);
220 // First attempt = 253 lines
221 // current = 51 lines
222 int v3_handle_cr0_read(struct guest_info * info) {
225 struct x86_instr dec_instr;
227 if (info->mem_mode == PHYSICAL_MEM) {
228 ret = v3_read_gpa_memory(info, get_addr_linear(info, info->rip, &(info->segments.cs)), 15, instr);
230 ret = v3_read_gva_memory(info, get_addr_linear(info, info->rip, &(info->segments.cs)), 15, instr);
234 if (v3_decode(info, (addr_t)instr, &dec_instr) == -1) {
235 PrintError(info->vm_info, info, "Could not decode instruction\n");
239 if (dec_instr.op_type == V3_OP_MOVCR2) {
240 PrintDebug(info->vm_info, info, "MOVCR2 (mode=%s)\n", v3_cpu_mode_to_str(info->cpu_mode));
242 if ((v3_get_vm_cpu_mode(info) == LONG) ||
243 (v3_get_vm_cpu_mode(info) == LONG_32_COMPAT)) {
244 struct cr0_64 * dst_reg = (struct cr0_64 *)(dec_instr.dst_operand.operand);
246 if (info->shdw_pg_mode == SHADOW_PAGING) {
247 struct cr0_64 * guest_cr0 = (struct cr0_64 *)&(info->shdw_pg_state.guest_cr0);
248 *dst_reg = *guest_cr0;
250 struct cr0_64 * shadow_cr0 = (struct cr0_64 *)&(info->ctrl_regs.cr0);
251 *dst_reg = *shadow_cr0;
254 PrintDebug(info->vm_info, info, "returned CR0: %p\n", (void *)*(addr_t *)dst_reg);
256 struct cr0_32 * dst_reg = (struct cr0_32 *)(dec_instr.dst_operand.operand);
258 if (info->shdw_pg_mode == SHADOW_PAGING) {
259 struct cr0_32 * guest_cr0 = (struct cr0_32 *)&(info->shdw_pg_state.guest_cr0);
260 *dst_reg = *guest_cr0;
262 struct cr0_32 * shadow_cr0 = (struct cr0_32 *)&(info->ctrl_regs.cr0);
263 *dst_reg = *shadow_cr0;
266 PrintDebug(info->vm_info, info, "returned CR0: %x\n", *(uint_t*)dst_reg);
269 } else if (dec_instr.op_type == V3_OP_SMSW) {
270 struct cr0_real * shadow_cr0 = (struct cr0_real *)&(info->ctrl_regs.cr0);
271 struct cr0_real * dst_reg = (struct cr0_real *)(dec_instr.dst_operand.operand);
272 char cr0_val = *(char*)shadow_cr0 & 0x0f;
274 PrintDebug(info->vm_info, info, "SMSW\n");
276 // The lower 4 bits of the guest/shadow CR0 are mapped through
277 // We can treat nested and shadow paging the same here
278 *(char *)dst_reg &= 0xf0;
279 *(char *)dst_reg |= cr0_val;
282 PrintError(info->vm_info, info, "Unhandled opcode in handle_cr0_read\n");
286 info->rip += dec_instr.instr_length;
294 // First Attempt = 256 lines
295 // current = 65 lines
296 int v3_handle_cr3_write(struct guest_info * info) {
299 struct x86_instr dec_instr;
301 if (info->mem_mode == PHYSICAL_MEM) {
302 ret = v3_read_gpa_memory(info, get_addr_linear(info, info->rip, &(info->segments.cs)), 15, instr);
304 ret = v3_read_gva_memory(info, get_addr_linear(info, info->rip, &(info->segments.cs)), 15, instr);
307 if (v3_decode(info, (addr_t)instr, &dec_instr) == -1) {
308 PrintError(info->vm_info, info, "Could not decode instruction\n");
312 if (dec_instr.op_type == V3_OP_MOV2CR) {
313 PrintDebug(info->vm_info, info, "MOV2CR3 (cpu_mode=%s)\n", v3_cpu_mode_to_str(info->cpu_mode));
315 if (info->shdw_pg_mode == SHADOW_PAGING) {
316 PrintDebug(info->vm_info, info, "Old Shadow CR3=%p; Old Guest CR3=%p\n",
317 (void *)(addr_t)(info->ctrl_regs.cr3),
318 (void*)(addr_t)(info->shdw_pg_state.guest_cr3));
321 // We update the guest CR3
322 if (info->cpu_mode == LONG) {
323 struct cr3_64 * new_cr3 = (struct cr3_64 *)(dec_instr.src_operand.operand);
324 struct cr3_64 * guest_cr3 = (struct cr3_64 *)&(info->shdw_pg_state.guest_cr3);
325 *guest_cr3 = *new_cr3;
327 struct cr3_32 * new_cr3 = (struct cr3_32 *)(dec_instr.src_operand.operand);
328 struct cr3_32 * guest_cr3 = (struct cr3_32 *)&(info->shdw_pg_state.guest_cr3);
329 *guest_cr3 = *new_cr3;
333 // If Paging is enabled in the guest then we need to change the shadow page tables
334 if (info->mem_mode == VIRTUAL_MEM) {
335 if (v3_activate_shadow_pt(info) == -1) {
336 PrintError(info->vm_info, info, "Failed to activate 32 bit shadow page table\n");
341 PrintDebug(info->vm_info, info, "New Shadow CR3=%p; New Guest CR3=%p\n",
342 (void *)(addr_t)(info->ctrl_regs.cr3),
343 (void*)(addr_t)(info->shdw_pg_state.guest_cr3));
345 } else if (info->shdw_pg_mode == NESTED_PAGING) {
347 // This is just a passthrough operation which we probably don't need here
348 if (info->cpu_mode == LONG) {
349 struct cr3_64 * new_cr3 = (struct cr3_64 *)(dec_instr.src_operand.operand);
350 struct cr3_64 * guest_cr3 = (struct cr3_64 *)&(info->ctrl_regs.cr3);
351 *guest_cr3 = *new_cr3;
353 struct cr3_32 * new_cr3 = (struct cr3_32 *)(dec_instr.src_operand.operand);
354 struct cr3_32 * guest_cr3 = (struct cr3_32 *)&(info->ctrl_regs.cr3);
355 *guest_cr3 = *new_cr3;
360 PrintError(info->vm_info, info, "Unhandled opcode in handle_cr3_write\n");
364 info->rip += dec_instr.instr_length;
371 // first attempt = 156 lines
372 // current = 36 lines
373 int v3_handle_cr3_read(struct guest_info * info) {
376 struct x86_instr dec_instr;
378 if (info->mem_mode == PHYSICAL_MEM) {
379 ret = v3_read_gpa_memory(info, get_addr_linear(info, info->rip, &(info->segments.cs)), 15, instr);
381 ret = v3_read_gva_memory(info, get_addr_linear(info, info->rip, &(info->segments.cs)), 15, instr);
384 if (v3_decode(info, (addr_t)instr, &dec_instr) == -1) {
385 PrintError(info->vm_info, info, "Could not decode instruction\n");
389 if (dec_instr.op_type == V3_OP_MOVCR2) {
390 PrintDebug(info->vm_info, info, "MOVCR32 (mode=%s)\n", v3_cpu_mode_to_str(info->cpu_mode));
392 if (info->shdw_pg_mode == SHADOW_PAGING) {
394 if ((v3_get_vm_cpu_mode(info) == LONG) ||
395 (v3_get_vm_cpu_mode(info) == LONG_32_COMPAT)) {
396 struct cr3_64 * dst_reg = (struct cr3_64 *)(dec_instr.dst_operand.operand);
397 struct cr3_64 * guest_cr3 = (struct cr3_64 *)&(info->shdw_pg_state.guest_cr3);
398 *dst_reg = *guest_cr3;
400 struct cr3_32 * dst_reg = (struct cr3_32 *)(dec_instr.dst_operand.operand);
401 struct cr3_32 * guest_cr3 = (struct cr3_32 *)&(info->shdw_pg_state.guest_cr3);
402 *dst_reg = *guest_cr3;
405 } else if (info->shdw_pg_mode == NESTED_PAGING) {
407 // This is just a passthrough operation which we probably don't need here
408 if ((v3_get_vm_cpu_mode(info) == LONG) ||
409 (v3_get_vm_cpu_mode(info) == LONG_32_COMPAT)) {
410 struct cr3_64 * dst_reg = (struct cr3_64 *)(dec_instr.dst_operand.operand);
411 struct cr3_64 * guest_cr3 = (struct cr3_64 *)&(info->ctrl_regs.cr3);
412 *dst_reg = *guest_cr3;
414 struct cr3_32 * dst_reg = (struct cr3_32 *)(dec_instr.dst_operand.operand);
415 struct cr3_32 * guest_cr3 = (struct cr3_32 *)&(info->ctrl_regs.cr3);
416 *dst_reg = *guest_cr3;
421 PrintError(info->vm_info, info, "Unhandled opcode in handle_cr3_read\n");
425 info->rip += dec_instr.instr_length;
431 //return guest cr4 - shadow PAE is always on
432 int v3_handle_cr4_read(struct guest_info * info) {
435 struct x86_instr dec_instr;
437 if (info->mem_mode == PHYSICAL_MEM) {
438 ret = v3_read_gpa_memory(info, get_addr_linear(info, info->rip, &(info->segments.cs)), 15, instr);
440 ret = v3_read_gva_memory(info, get_addr_linear(info, info->rip, &(info->segments.cs)), 15, instr);
443 if (v3_decode(info, (addr_t)instr, &dec_instr) == -1) {
444 PrintError(info->vm_info, info, "Could not decode instruction\n");
447 if (dec_instr.op_type != V3_OP_MOVCR2) {
448 PrintError(info->vm_info, info, "Invalid opcode in read CR4\n");
452 if (info->shdw_pg_mode == SHADOW_PAGING) {
454 if ((v3_get_vm_cpu_mode(info) == LONG) ||
455 (v3_get_vm_cpu_mode(info) == LONG_32_COMPAT)) {
456 struct cr4_64 * dst_reg = (struct cr4_64 *)(dec_instr.dst_operand.operand);
457 struct cr4_64 * guest_cr4 = (struct cr4_64 *)&(info->ctrl_regs.cr4);
458 *dst_reg = *guest_cr4;
461 struct cr4_32 * dst_reg = (struct cr4_32 *)(dec_instr.dst_operand.operand);
462 struct cr4_32 * guest_cr4 = (struct cr4_32 *)&(info->shdw_pg_state.guest_cr4);
463 *dst_reg = *guest_cr4;
466 } else if (info->shdw_pg_mode == NESTED_PAGING) {
469 if ((v3_get_vm_cpu_mode(info) == LONG) ||
470 (v3_get_vm_cpu_mode(info) == LONG_32_COMPAT)) {
471 struct cr4_64 * dst_reg = (struct cr4_64 *)(dec_instr.dst_operand.operand);
472 struct cr4_64 * guest_cr4 = (struct cr4_64 *)&(info->ctrl_regs.cr4);
473 *dst_reg = *guest_cr4;
475 struct cr4_32 * dst_reg = (struct cr4_32 *)(dec_instr.dst_operand.operand);
476 struct cr4_32 * guest_cr4 = (struct cr4_32 *)&(info->ctrl_regs.cr4);
477 *dst_reg = *guest_cr4;
481 info->rip += dec_instr.instr_length;
486 int v3_handle_cr4_write(struct guest_info * info) {
490 struct x86_instr dec_instr;
491 v3_cpu_mode_t cpu_mode = v3_get_vm_cpu_mode(info);
493 if (info->mem_mode == PHYSICAL_MEM) {
494 ret = v3_read_gpa_memory(info, get_addr_linear(info, info->rip, &(info->segments.cs)), 15, instr);
496 ret = v3_read_gva_memory(info, get_addr_linear(info, info->rip, &(info->segments.cs)), 15, instr);
499 if (v3_decode(info, (addr_t)instr, &dec_instr) == -1) {
500 PrintError(info->vm_info, info, "Could not decode instruction\n");
504 if (dec_instr.op_type != V3_OP_MOV2CR) {
505 PrintError(info->vm_info, info, "Invalid opcode in write to CR4\n");
509 // Check to see if we need to flush the tlb
512 if (v3_get_vm_mem_mode(info) == VIRTUAL_MEM) {
513 struct cr4_32 * new_cr4 = (struct cr4_32 *)(dec_instr.src_operand.operand);
514 struct cr4_32 * cr4 = (struct cr4_32 *)&(info->shdw_pg_state.guest_cr4);
516 // if pse, pge, or pae have changed while PG (in any mode) is on
517 // the side effect is a TLB flush, which means we need to
518 // toss the current shadow page tables too
521 // TODO - PAE FLAG needs to be special cased
522 if ((cr4->pse != new_cr4->pse) ||
523 (cr4->pge != new_cr4->pge) ||
524 (cr4->pae != new_cr4->pae)) {
525 PrintDebug(info->vm_info, info, "Handling PSE/PGE/PAE -> TLBFlush case, flag set\n");
532 if ((cpu_mode == PROTECTED) || (cpu_mode == PROTECTED_PAE)) {
533 struct cr4_32 * new_cr4 = (struct cr4_32 *)(dec_instr.src_operand.operand);
534 struct cr4_32 * shadow_cr4 = (struct cr4_32 *)&(info->ctrl_regs.cr4);
535 struct cr4_32 * guest_cr4 = (struct cr4_32 *)&(info->shdw_pg_state.guest_cr4);
536 PrintDebug(info->vm_info, info, "OperandVal = %x, length = %d\n", *(uint_t *)new_cr4, dec_instr.src_operand.size);
537 PrintDebug(info->vm_info, info, "Old guest CR4=%x\n", *(uint_t *)guest_cr4);
539 if ((info->shdw_pg_mode == SHADOW_PAGING)) {
540 if (v3_get_vm_mem_mode(info) == PHYSICAL_MEM) {
542 if ((guest_cr4->pae == 0) && (new_cr4->pae == 1)) {
543 PrintDebug(info->vm_info, info, "Creating PAE passthrough tables\n");
545 // create 32 bit PAE direct map page table
546 if (v3_reset_passthrough_pts(info) == -1) {
547 PrintError(info->vm_info, info, "Could not create 32 bit PAE passthrough pages tables\n");
551 // reset cr3 to new page tables
552 info->ctrl_regs.cr3 = *(addr_t*)&(info->direct_map_pt);
554 } else if ((guest_cr4->pae == 1) && (new_cr4->pae == 0)) {
555 // Create passthrough standard 32bit pagetables
556 PrintError(info->vm_info, info, "Switching From PAE to Protected mode not supported\n");
562 *guest_cr4 = *new_cr4;
563 *shadow_cr4 = *guest_cr4;
564 shadow_cr4->pae = 1; // always on for the shadow pager
565 PrintDebug(info->vm_info, info, "New guest CR4=%x and shadow CR4=%x\n", *(uint_t *)guest_cr4,*(uint_t*)shadow_cr4);
567 } else if ((cpu_mode == LONG) || (cpu_mode == LONG_32_COMPAT)) {
568 struct cr4_64 * new_cr4 = (struct cr4_64 *)(dec_instr.src_operand.operand);
569 struct cr4_64 * cr4 = (struct cr4_64 *)&(info->ctrl_regs.cr4);
571 PrintDebug(info->vm_info, info, "Old CR4=%p\n", (void *)*(addr_t *)cr4);
572 PrintDebug(info->vm_info, info, "New CR4=%p\n", (void *)*(addr_t *)new_cr4);
574 if (new_cr4->pae == 0) {
575 // cannot turn off PAE in long mode GPF the guest
576 PrintError(info->vm_info, info, "Cannot disable PAE in long mode, should send GPF\n");
583 PrintError(info->vm_info, info, "CR4 write not supported in CPU_MODE: %s\n", v3_cpu_mode_to_str(cpu_mode));
587 if (info->shdw_pg_mode == SHADOW_PAGING) {
589 PrintDebug(info->vm_info, info, "Handling PSE/PGE/PAE -> TLBFlush (doing flush now!)\n");
590 if (v3_activate_shadow_pt(info) == -1) {
591 PrintError(info->vm_info, info, "Failed to activate shadow page tables when emulating TLB flush in handling cr4 write\n");
597 info->rip += dec_instr.instr_length;
603 The CR8 and APIC TPR interaction are kind of crazy.
605 CR8 mandates that the priority class is in bits 3:0
607 The interaction of CR8 and an actual APIC is somewhat implementation dependent, but
608 a basic current APIC has the priority class at 7:4 and the *subclass* at 3:0
610 The APIC TPR (both fields) can be written as the APIC register
611 A write to CR8 sets the priority class field, and should zero the subclass
612 A read from CR8 gets just the priority class field
614 In the apic_tpr storage location, we have:
616 zeros [class] [subclass]
618 Because of this, an APIC implementation should use apic_tpr to store its TPR
619 In fact, it *should* do this, otherwise its TPR may get out of sync with the architected TPR
621 On a CR8 read, we return just
625 On a CR8 write, we set the register to
631 int v3_handle_cr8_write(struct guest_info * info) {
634 struct x86_instr dec_instr;
636 if (info->mem_mode == PHYSICAL_MEM) {
637 ret = v3_read_gpa_memory(info, get_addr_linear(info, info->rip, &(info->segments.cs)), 15, instr);
639 ret = v3_read_gva_memory(info, get_addr_linear(info, info->rip, &(info->segments.cs)), 15, instr);
642 if (v3_decode(info, (addr_t)instr, &dec_instr) == -1) {
643 PrintError(info->vm_info, info, "Could not decode instruction\n");
647 if (dec_instr.op_type == V3_OP_MOV2CR) {
648 PrintDebug(info->vm_info, info, "MOV2CR8 (cpu_mode=%s)\n", v3_cpu_mode_to_str(info->cpu_mode));
650 if ((info->cpu_mode == LONG) ||
651 (info->cpu_mode == LONG_32_COMPAT)) {
652 uint64_t *val = (uint64_t *)(dec_instr.src_operand.operand);
654 info->ctrl_regs.apic_tpr = (*val & 0xf) << 4;
656 V3_Print(info->vm_info, info, "Write of CR8 sets apic_tpr to 0x%llx\n",info->ctrl_regs.apic_tpr);
659 // probably should raise exception here
662 PrintError(info->vm_info, info, "Unhandled opcode in handle_cr8_write\n");
666 info->rip += dec_instr.instr_length;
673 int v3_handle_cr8_read(struct guest_info * info) {
676 struct x86_instr dec_instr;
678 if (info->mem_mode == PHYSICAL_MEM) {
679 ret = v3_read_gpa_memory(info, get_addr_linear(info, info->rip, &(info->segments.cs)), 15, instr);
681 ret = v3_read_gva_memory(info, get_addr_linear(info, info->rip, &(info->segments.cs)), 15, instr);
684 if (v3_decode(info, (addr_t)instr, &dec_instr) == -1) {
685 PrintError(info->vm_info, info, "Could not decode instruction\n");
689 if (dec_instr.op_type == V3_OP_MOVCR2) {
690 PrintDebug(info->vm_info, info, "MOVCR82 (mode=%s)\n", v3_cpu_mode_to_str(info->cpu_mode));
692 if ((info->cpu_mode == LONG) ||
693 (info->cpu_mode == LONG_32_COMPAT)) {
694 uint64_t *dst_reg = (uint64_t *)(dec_instr.dst_operand.operand);
696 *dst_reg = (info->ctrl_regs.apic_tpr >> 4) & 0xf;
698 V3_Print(info->vm_info, info, "Read of CR8 (apic_tpr) returns 0x%llx\n",*dst_reg);
701 // probably should raise exception
705 PrintError(info->vm_info, info, "Unhandled opcode in handle_cr8_read\n");
709 info->rip += dec_instr.instr_length;
715 int v3_handle_efer_read(struct guest_info * core, uint_t msr, struct v3_msr * dst, void * priv_data) {
716 PrintDebug(core->vm_info, core, "EFER Read HI=%x LO=%x\n", core->shdw_pg_state.guest_efer.hi, core->shdw_pg_state.guest_efer.lo);
718 dst->value = core->shdw_pg_state.guest_efer.value;
724 int v3_handle_efer_write(struct guest_info * core, uint_t msr, struct v3_msr src, void * priv_data) {
725 struct v3_msr * vm_efer = &(core->shdw_pg_state.guest_efer);
726 struct efer_64 * hw_efer = (struct efer_64 *)&(core->ctrl_regs.efer);
727 struct efer_64 old_hw_efer = *((struct efer_64 *)&core->ctrl_regs.efer);
729 PrintDebug(core->vm_info, core, "EFER Write HI=%x LO=%x\n", src.hi, src.lo);
731 // Set EFER value seen by guest if it reads EFER
732 vm_efer->value = src.value;
734 // Set EFER value seen by hardware while the guest is running
735 *(uint64_t *)hw_efer = src.value;
737 // We have gotten here either because we are using
738 // shadow paging, or we are using nested paging on SVM
739 // In the latter case, we don't need to do anything
740 // like the following
741 if (core->shdw_pg_mode == SHADOW_PAGING) {
742 // Catch unsupported features
743 if ((old_hw_efer.lme == 1) && (hw_efer->lme == 0)) {
744 PrintError(core->vm_info, core, "Disabling long mode once it has been enabled is not supported\n");
748 // Set LME and LMA bits seen by hardware
749 if (old_hw_efer.lme == 0) {
750 // Long mode was not previously enabled, so the lme bit cannot
751 // be set yet. It will be set later when the guest sets CR0.PG
755 // Long mode was previously enabled. Ensure LMA bit is set.
756 // VMX does not automatically set LMA, and this should not affect SVM.
762 PrintDebug(core->vm_info, core, "RIP=%p\n", (void *)core->rip);
763 PrintDebug(core->vm_info, core, "New EFER value HW(hi=%p), VM(hi=%p)\n", (void *)*(uint64_t *)hw_efer, (void *)vm_efer->value);
769 int v3_handle_vm_cr_read(struct guest_info * core, uint_t msr, struct v3_msr * dst, void * priv_data) {
770 /* tell the guest that the BIOS disabled SVM, that way it doesn't get
771 * confused by the fact that CPUID reports SVM as available but it still
774 dst->value = SVM_VM_CR_MSR_lock | SVM_VM_CR_MSR_svmdis;
775 PrintDebug(core->vm_info, core, "VM_CR Read HI=%x LO=%x\n", dst->hi, dst->lo);
779 int v3_handle_vm_cr_write(struct guest_info * core, uint_t msr, struct v3_msr src, void * priv_data) {
780 PrintDebug(core->vm_info, core, "VM_CR Write\n");
781 PrintDebug(core->vm_info, core, "VM_CR Write Values: HI=%x LO=%x\n", src.hi, src.lo);
783 /* writes to LOCK and SVMDIS are silently ignored (according to the spec),
784 * other writes indicate the guest wants to use some feature we haven't
787 if (src.value & ~(SVM_VM_CR_MSR_lock | SVM_VM_CR_MSR_svmdis)) {
788 PrintDebug(core->vm_info, core, "VM_CR write sets unsupported bits: HI=%x LO=%x\n", src.hi, src.lo);