2 * This file is part of the Palacios Virtual Machine Monitor developed
3 * by the V3VEE Project with funding from the United States National
4 * Science Foundation and the Department of Energy.
6 * The V3VEE Project is a joint project between Northwestern University
7 * and the University of New Mexico. You can find out more at
10 * Copyright (c) 2008, Jack Lange <jarusl@cs.northwestern.edu>
11 * Copyright (c) 2008, The V3VEE Project <http://www.v3vee.org>
12 * All rights reserved.
14 * Author: Jack Lange <jarusl@cs.northwestern.edu>
16 * This is free software. You are permitted to use,
17 * redistribute, and modify it as specified in the file "V3VEE_LICENSE".
21 #include <palacios/svm.h>
22 #include <palacios/vmm.h>
24 #include <palacios/vmcb.h>
25 #include <palacios/vmm_mem.h>
26 #include <palacios/vmm_paging.h>
27 #include <palacios/svm_handler.h>
29 #include <palacios/vmm_debug.h>
30 #include <palacios/vm_guest_mem.h>
32 #include <palacios/vmm_decoder.h>
33 #include <palacios/vmm_string.h>
34 #include <palacios/vmm_lowlevel.h>
35 #include <palacios/svm_msr.h>
37 #include <palacios/vmm_rbtree.h>
39 #include <palacios/vmm_profiler.h>
41 #include <palacios/vmm_direct_paging.h>
43 #include <palacios/vmm_ctrl_regs.h>
44 #include <palacios/vmm_config.h>
45 #include <palacios/svm_io.h>
49 // This is a global pointer to the host's VMCB
50 static void * host_vmcb = NULL;
52 extern void v3_stgi();
53 extern void v3_clgi();
54 //extern int v3_svm_launch(vmcb_t * vmcb, struct v3_gprs * vm_regs, uint64_t * fs, uint64_t * gs);
55 extern int v3_svm_launch(vmcb_t * vmcb, struct v3_gprs * vm_regs, vmcb_t * host_vmcb);
58 static vmcb_t * Allocate_VMCB() {
59 vmcb_t * vmcb_page = (vmcb_t *)V3_VAddr(V3_AllocPages(1));
61 memset(vmcb_page, 0, 4096);
68 static void Init_VMCB_BIOS(vmcb_t * vmcb, struct guest_info *vm_info) {
69 vmcb_ctrl_t * ctrl_area = GET_VMCB_CTRL_AREA(vmcb);
70 vmcb_saved_state_t * guest_state = GET_VMCB_SAVE_STATE_AREA(vmcb);
75 guest_state->rsp = 0x00;
76 guest_state->rip = 0xfff0;
81 guest_state->efer |= EFER_MSR_svm_enable;
84 guest_state->rflags = 0x00000002; // The reserved bit is always 1
85 ctrl_area->svm_instrs.VMRUN = 1;
86 ctrl_area->svm_instrs.VMMCALL = 1;
87 ctrl_area->svm_instrs.VMLOAD = 1;
88 ctrl_area->svm_instrs.VMSAVE = 1;
89 ctrl_area->svm_instrs.STGI = 1;
90 ctrl_area->svm_instrs.CLGI = 1;
91 ctrl_area->svm_instrs.SKINIT = 1;
92 ctrl_area->svm_instrs.RDTSCP = 1;
93 ctrl_area->svm_instrs.ICEBP = 1;
94 ctrl_area->svm_instrs.WBINVD = 1;
95 ctrl_area->svm_instrs.MONITOR = 1;
96 ctrl_area->svm_instrs.MWAIT_always = 1;
97 ctrl_area->svm_instrs.MWAIT_if_armed = 1;
98 ctrl_area->instrs.INVLPGA = 1;
101 ctrl_area->instrs.HLT = 1;
102 // guest_state->cr0 = 0x00000001; // PE
105 ctrl_area->exceptions.de = 1;
106 ctrl_area->exceptions.df = 1;
108 ctrl_area->exceptions.ts = 1;
109 ctrl_area->exceptions.ss = 1;
110 ctrl_area->exceptions.ac = 1;
111 ctrl_area->exceptions.mc = 1;
112 ctrl_area->exceptions.gp = 1;
113 ctrl_area->exceptions.ud = 1;
114 ctrl_area->exceptions.np = 1;
115 ctrl_area->exceptions.of = 1;
117 ctrl_area->exceptions.nmi = 1;
121 ctrl_area->instrs.NMI = 1;
122 ctrl_area->instrs.SMI = 1;
123 ctrl_area->instrs.INIT = 1;
124 ctrl_area->instrs.PAUSE = 1;
125 ctrl_area->instrs.shutdown_evts = 1;
127 vm_info->vm_regs.rdx = 0x00000f00;
129 guest_state->cr0 = 0x60000010;
132 guest_state->cs.selector = 0xf000;
133 guest_state->cs.limit = 0xffff;
134 guest_state->cs.base = 0x0000000f0000LL;
135 guest_state->cs.attrib.raw = 0xf3;
138 /* DEBUG FOR RETURN CODE */
139 ctrl_area->exit_code = 1;
142 struct vmcb_selector *segregs [] = {&(guest_state->ss), &(guest_state->ds),
143 &(guest_state->es), &(guest_state->fs),
144 &(guest_state->gs), NULL};
146 for ( i = 0; segregs[i] != NULL; i++) {
147 struct vmcb_selector * seg = segregs[i];
149 seg->selector = 0x0000;
150 // seg->base = seg->selector << 4;
151 seg->base = 0x00000000;
152 seg->attrib.raw = 0xf3;
156 guest_state->gdtr.limit = 0x0000ffff;
157 guest_state->gdtr.base = 0x0000000000000000LL;
158 guest_state->idtr.limit = 0x0000ffff;
159 guest_state->idtr.base = 0x0000000000000000LL;
161 guest_state->ldtr.selector = 0x0000;
162 guest_state->ldtr.limit = 0x0000ffff;
163 guest_state->ldtr.base = 0x0000000000000000LL;
164 guest_state->tr.selector = 0x0000;
165 guest_state->tr.limit = 0x0000ffff;
166 guest_state->tr.base = 0x0000000000000000LL;
169 guest_state->dr6 = 0x00000000ffff0ff0LL;
170 guest_state->dr7 = 0x0000000000000400LL;
173 v3_init_svm_io_map(vm_info);
174 ctrl_area->IOPM_BASE_PA = (addr_t)V3_PAddr(vm_info->io_map.arch_data);
175 ctrl_area->instrs.IOIO_PROT = 1;
179 v3_init_svm_msr_map(vm_info);
180 ctrl_area->MSRPM_BASE_PA = (addr_t)V3_PAddr(vm_info->msr_map.arch_data);
181 ctrl_area->instrs.MSR_PROT = 1;
185 PrintDebug("Exiting on interrupts\n");
186 ctrl_area->guest_ctrl.V_INTR_MASKING = 1;
187 ctrl_area->instrs.INTR = 1;
190 if (vm_info->shdw_pg_mode == SHADOW_PAGING) {
191 PrintDebug("Creating initial shadow page table\n");
193 /* JRL: This is a performance killer, and a simplistic solution */
194 /* We need to fix this */
195 ctrl_area->TLB_CONTROL = 1;
196 ctrl_area->guest_ASID = 1;
199 if (v3_init_passthrough_pts(vm_info) == -1) {
200 PrintError("Could not initialize passthrough page tables\n");
205 vm_info->shdw_pg_state.guest_cr0 = 0x0000000000000010LL;
206 PrintDebug("Created\n");
208 guest_state->cr3 = vm_info->direct_map_pt;
210 ctrl_area->cr_reads.cr0 = 1;
211 ctrl_area->cr_writes.cr0 = 1;
212 //ctrl_area->cr_reads.cr4 = 1;
213 ctrl_area->cr_writes.cr4 = 1;
214 ctrl_area->cr_reads.cr3 = 1;
215 ctrl_area->cr_writes.cr3 = 1;
217 v3_hook_msr(vm_info, EFER_MSR,
218 &v3_handle_efer_read,
219 &v3_handle_efer_write,
222 ctrl_area->instrs.INVLPG = 1;
224 ctrl_area->exceptions.pf = 1;
226 guest_state->g_pat = 0x7040600070406ULL;
228 guest_state->cr0 |= 0x80000000;
230 } else if (vm_info->shdw_pg_mode == NESTED_PAGING) {
231 // Flush the TLB on entries/exits
232 ctrl_area->TLB_CONTROL = 1;
233 ctrl_area->guest_ASID = 1;
235 // Enable Nested Paging
236 ctrl_area->NP_ENABLE = 1;
238 PrintDebug("NP_Enable at 0x%p\n", (void *)&(ctrl_area->NP_ENABLE));
240 // Set the Nested Page Table pointer
241 if (v3_init_passthrough_pts(vm_info) == -1) {
242 PrintError("Could not initialize Nested page tables\n");
246 ctrl_area->N_CR3 = vm_info->direct_map_pt;
248 guest_state->g_pat = 0x7040600070406ULL;
253 static int init_svm_guest(struct guest_info * info, struct v3_vm_config * config_ptr) {
256 v3_pre_config_guest(info, config_ptr);
258 PrintDebug("Allocating VMCB\n");
259 info->vmm_data = (void*)Allocate_VMCB();
261 PrintDebug("Initializing VMCB (addr=%p)\n", (void *)info->vmm_data);
262 Init_VMCB_BIOS((vmcb_t*)(info->vmm_data), info);
264 v3_post_config_guest(info, config_ptr);
269 static int start_svm_guest(struct guest_info *info) {
270 // vmcb_saved_state_t * guest_state = GET_VMCB_SAVE_STATE_AREA((vmcb_t*)(info->vmm_data));
271 // vmcb_ctrl_t * guest_ctrl = GET_VMCB_CTRL_AREA((vmcb_t*)(info->vmm_data));
272 uint_t num_exits = 0;
276 PrintDebug("Launching SVM VM (vmcb=%p)\n", (void *)info->vmm_data);
277 //PrintDebugVMCB((vmcb_t*)(info->vmm_data));
279 info->run_state = VM_RUNNING;
286 PrintDebug("SVM Entry to CS=%p rip=%p...\n",
287 (void *)(addr_t)info->segments.cs.base,
288 (void *)(addr_t)info->rip);
291 // disable global interrupts for vm state transition
296 rdtscll(info->time_state.cached_host_tsc);
297 // guest_ctrl->TSC_OFFSET = info->time_state.guest_tsc - info->time_state.cached_host_tsc;
299 v3_svm_launch((vmcb_t*)V3_PAddr(info->vmm_data), &(info->vm_regs), (vmcb_t *)host_vmcb);
304 //PrintDebug("SVM Returned\n");
306 // reenable global interrupts after vm exit
309 v3_update_time(info, tmp_tsc - info->time_state.cached_host_tsc);
312 if ((num_exits % 5000) == 0) {
313 PrintDebug("SVM Exit number %d\n", num_exits);
315 if (info->enable_profiler) {
316 v3_print_profile(info);
321 if (v3_handle_svm_exit(info) != 0) {
322 vmcb_ctrl_t * guest_ctrl = GET_VMCB_CTRL_AREA((vmcb_t*)(info->vmm_data));
324 addr_t linear_addr = 0;
326 info->run_state = VM_ERROR;
328 PrintDebug("SVM ERROR!!\n");
330 v3_print_guest_state(info);
332 PrintDebug("SVM Exit Code: %p\n", (void *)(addr_t)guest_ctrl->exit_code);
334 PrintDebug("exit_info1 low = 0x%.8x\n", *(uint_t*)&(guest_ctrl->exit_info1));
335 PrintDebug("exit_info1 high = 0x%.8x\n", *(uint_t *)(((uchar_t *)&(guest_ctrl->exit_info1)) + 4));
337 PrintDebug("exit_info2 low = 0x%.8x\n", *(uint_t*)&(guest_ctrl->exit_info2));
338 PrintDebug("exit_info2 high = 0x%.8x\n", *(uint_t *)(((uchar_t *)&(guest_ctrl->exit_info2)) + 4));
340 linear_addr = get_addr_linear(info, info->rip, &(info->segments.cs));
342 if (info->mem_mode == PHYSICAL_MEM) {
343 guest_pa_to_host_va(info, linear_addr, &host_addr);
344 } else if (info->mem_mode == VIRTUAL_MEM) {
345 guest_va_to_host_va(info, linear_addr, &host_addr);
348 PrintDebug("Host Address of rip = 0x%p\n", (void *)host_addr);
350 PrintDebug("Instr (15 bytes) at %p:\n", (void *)host_addr);
351 PrintTraceMemDump((uchar_t *)host_addr, 15);
363 /* Checks machine SVM capability */
364 /* Implemented from: AMD Arch Manual 3, sect 15.4 */
365 int v3_is_svm_capable() {
367 uint_t vm_cr_low = 0, vm_cr_high = 0;
368 addr_t eax = 0, ebx = 0, ecx = 0, edx = 0;
370 v3_cpuid(CPUID_EXT_FEATURE_IDS, &eax, &ebx, &ecx, &edx);
372 PrintDebug("CPUID_EXT_FEATURE_IDS_ecx=%p\n", (void *)ecx);
374 if ((ecx & CPUID_EXT_FEATURE_IDS_ecx_svm_avail) == 0) {
375 PrintDebug("SVM Not Available\n");
378 v3_get_msr(SVM_VM_CR_MSR, &vm_cr_high, &vm_cr_low);
380 PrintDebug("SVM_VM_CR_MSR = 0x%x 0x%x\n", vm_cr_high, vm_cr_low);
382 if ((vm_cr_low & SVM_VM_CR_MSR_svmdis) == 1) {
383 PrintDebug("SVM is available but is disabled.\n");
385 v3_cpuid(CPUID_SVM_REV_AND_FEATURE_IDS, &eax, &ebx, &ecx, &edx);
387 PrintDebug("CPUID_SVM_REV_AND_FEATURE_IDS_edx=%p\n", (void *)edx);
389 if ((edx & CPUID_SVM_REV_AND_FEATURE_IDS_edx_svml) == 0) {
390 PrintDebug("SVM BIOS Disabled, not unlockable\n");
392 PrintDebug("SVM is locked with a key\n");
397 PrintDebug("SVM is available and enabled.\n");
399 v3_cpuid(CPUID_SVM_REV_AND_FEATURE_IDS, &eax, &ebx, &ecx, &edx);
400 PrintDebug("CPUID_SVM_REV_AND_FEATURE_IDS_eax=%p\n", (void *)eax);
401 PrintDebug("CPUID_SVM_REV_AND_FEATURE_IDS_ebx=%p\n", (void *)ebx);
402 PrintDebug("CPUID_SVM_REV_AND_FEATURE_IDS_ecx=%p\n", (void *)ecx);
403 PrintDebug("CPUID_SVM_REV_AND_FEATURE_IDS_edx=%p\n", (void *)edx);
406 if ((edx & CPUID_SVM_REV_AND_FEATURE_IDS_edx_np) == 0) {
407 PrintDebug("SVM Nested Paging not supported\n");
409 PrintDebug("SVM Nested Paging supported\n");
417 static int has_svm_nested_paging() {
418 addr_t eax = 0, ebx = 0, ecx = 0, edx = 0;
420 v3_cpuid(CPUID_SVM_REV_AND_FEATURE_IDS, &eax, &ebx, &ecx, &edx);
422 //PrintDebug("CPUID_EXT_FEATURE_IDS_edx=0x%x\n", edx);
424 if ((edx & CPUID_SVM_REV_AND_FEATURE_IDS_edx_np) == 0) {
425 PrintDebug("SVM Nested Paging not supported\n");
428 PrintDebug("SVM Nested Paging supported\n");
435 void v3_init_SVM(struct v3_ctrl_ops * vmm_ops) {
437 extern v3_cpu_arch_t v3_cpu_type;
439 // Enable SVM on the CPU
440 v3_get_msr(EFER_MSR, &(msr.e_reg.high), &(msr.e_reg.low));
441 msr.e_reg.low |= EFER_MSR_svm_enable;
442 v3_set_msr(EFER_MSR, 0, msr.e_reg.low);
444 PrintDebug("SVM Enabled\n");
446 // Setup the host state save area
447 host_vmcb = V3_AllocPages(4);
450 // msr.e_reg.high = 0;
451 //msr.e_reg.low = (uint_t)host_vmcb;
452 msr.r_reg = (addr_t)host_vmcb;
454 PrintDebug("Host State being saved at %p\n", (void *)(addr_t)host_vmcb);
455 v3_set_msr(SVM_VM_HSAVE_PA_MSR, msr.e_reg.high, msr.e_reg.low);
458 * Test VMSAVE/VMLOAD Latency
460 #define vmsave ".byte 0x0F,0x01,0xDB ; "
461 #define vmload ".byte 0x0F,0x01,0xDA ; "
463 uint32_t start_lo, start_hi;
464 uint32_t end_lo, end_hi;
467 __asm__ __volatile__ (
469 "movl %%eax, %%esi ; "
470 "movl %%edx, %%edi ; "
471 "movq %%rcx, %%rax ; "
474 : "=D"(start_hi), "=S"(start_lo), "=a"(end_lo),"=d"(end_hi)
475 : "c"(host_vmcb), "0"(0), "1"(0), "2"(0), "3"(0)
486 PrintDebug("VMSave Cycle Latency: %d\n", (uint32_t)(end - start));
488 __asm__ __volatile__ (
490 "movl %%eax, %%esi ; "
491 "movl %%edx, %%edi ; "
492 "movq %%rcx, %%rax ; "
495 : "=D"(start_hi), "=S"(start_lo), "=a"(end_lo),"=d"(end_hi)
496 : "c"(host_vmcb), "0"(0), "1"(0), "2"(0), "3"(0)
508 PrintDebug("VMLoad Cycle Latency: %d\n", (uint32_t)(end - start));
510 /* End Latency Test */
512 if (has_svm_nested_paging() == 1) {
513 v3_cpu_type = V3_SVM_REV3_CPU;
515 v3_cpu_type = V3_SVM_CPU;
518 // Setup the SVM specific vmm operations
519 vmm_ops->init_guest = &init_svm_guest;
520 vmm_ops->start_guest = &start_svm_guest;
521 vmm_ops->has_nested_paging = &has_svm_nested_paging;
577 /*static void Init_VMCB(vmcb_t * vmcb, struct guest_info vm_info) {
578 vmcb_ctrl_t * ctrl_area = GET_VMCB_CTRL_AREA(vmcb);
579 vmcb_saved_state_t * guest_state = GET_VMCB_SAVE_STATE_AREA(vmcb);
583 guest_state->rsp = vm_info.vm_regs.rsp;
584 guest_state->rip = vm_info.rip;
587 //ctrl_area->instrs.instrs.CR0 = 1;
588 ctrl_area->cr_reads.cr0 = 1;
589 ctrl_area->cr_writes.cr0 = 1;
591 guest_state->efer |= EFER_MSR_svm_enable;
592 guest_state->rflags = 0x00000002; // The reserved bit is always 1
593 ctrl_area->svm_instrs.VMRUN = 1;
594 // guest_state->cr0 = 0x00000001; // PE
595 ctrl_area->guest_ASID = 1;
598 ctrl_area->exceptions.de = 1;
599 ctrl_area->exceptions.df = 1;
600 ctrl_area->exceptions.pf = 1;
601 ctrl_area->exceptions.ts = 1;
602 ctrl_area->exceptions.ss = 1;
603 ctrl_area->exceptions.ac = 1;
604 ctrl_area->exceptions.mc = 1;
605 ctrl_area->exceptions.gp = 1;
606 ctrl_area->exceptions.ud = 1;
607 ctrl_area->exceptions.np = 1;
608 ctrl_area->exceptions.of = 1;
609 ctrl_area->exceptions.nmi = 1;
611 guest_state->cs.selector = 0x0000;
612 guest_state->cs.limit=~0u;
613 guest_state->cs.base = guest_state->cs.selector<<4;
614 guest_state->cs.attrib.raw = 0xf3;
617 struct vmcb_selector *segregs [] = {&(guest_state->ss), &(guest_state->ds), &(guest_state->es), &(guest_state->fs), &(guest_state->gs), NULL};
618 for ( i = 0; segregs[i] != NULL; i++) {
619 struct vmcb_selector * seg = segregs[i];
621 seg->selector = 0x0000;
622 seg->base = seg->selector << 4;
623 seg->attrib.raw = 0xf3;
627 if (vm_info.io_map.num_ports > 0) {
628 struct vmm_io_hook * iter;
629 addr_t io_port_bitmap;
631 io_port_bitmap = (addr_t)V3_AllocPages(3);
632 memset((uchar_t*)io_port_bitmap, 0, PAGE_SIZE * 3);
634 ctrl_area->IOPM_BASE_PA = io_port_bitmap;
636 //PrintDebug("Setting up IO Map at 0x%x\n", io_port_bitmap);
638 FOREACH_IO_HOOK(vm_info.io_map, iter) {
639 ushort_t port = iter->port;
640 uchar_t * bitmap = (uchar_t *)io_port_bitmap;
642 bitmap += (port / 8);
643 PrintDebug("Setting Bit in block %x\n", bitmap);
644 *bitmap |= 1 << (port % 8);
648 //PrintDebugMemDump((uchar_t*)io_port_bitmap, PAGE_SIZE *2);
650 ctrl_area->instrs.IOIO_PROT = 1;
653 ctrl_area->instrs.INTR = 1;
657 if (vm_info.page_mode == SHADOW_PAGING) {
658 PrintDebug("Creating initial shadow page table\n");
659 vm_info.shdw_pg_state.shadow_cr3 |= ((addr_t)create_passthrough_pts_32(&vm_info) & ~0xfff);
660 PrintDebug("Created\n");
662 guest_state->cr3 = vm_info.shdw_pg_state.shadow_cr3;
664 ctrl_area->cr_reads.cr3 = 1;
665 ctrl_area->cr_writes.cr3 = 1;
668 ctrl_area->instrs.INVLPG = 1;
669 ctrl_area->instrs.INVLPGA = 1;
671 guest_state->g_pat = 0x7040600070406ULL;
673 guest_state->cr0 |= 0x80000000;
674 } else if (vm_info.page_mode == NESTED_PAGING) {
675 // Flush the TLB on entries/exits
676 //ctrl_area->TLB_CONTROL = 1;
678 // Enable Nested Paging
679 //ctrl_area->NP_ENABLE = 1;
681 //PrintDebug("NP_Enable at 0x%x\n", &(ctrl_area->NP_ENABLE));
683 // Set the Nested Page Table pointer
684 // ctrl_area->N_CR3 = ((addr_t)vm_info.page_tables);
685 // ctrl_area->N_CR3 = (addr_t)(vm_info.page_tables);
687 // ctrl_area->N_CR3 = Get_CR3();
688 // guest_state->cr3 |= (Get_CR3() & 0xfffff000);
690 // guest_state->g_pat = 0x7040600070406ULL;
705 void Init_VMCB_pe(vmcb_t *vmcb, struct guest_info vm_info) {
706 vmcb_ctrl_t * ctrl_area = GET_VMCB_CTRL_AREA(vmcb);
707 vmcb_saved_state_t * guest_state = GET_VMCB_SAVE_STATE_AREA(vmcb);
711 guest_state->rsp = vm_info.vm_regs.rsp;
712 guest_state->rip = vm_info.rip;
715 /* I pretty much just gutted this from TVMM */
716 /* Note: That means its probably wrong */
718 // set the segment registers to mirror ours
719 guest_state->cs.selector = 1<<3;
720 guest_state->cs.attrib.fields.type = 0xa; // Code segment+read
721 guest_state->cs.attrib.fields.S = 1;
722 guest_state->cs.attrib.fields.P = 1;
723 guest_state->cs.attrib.fields.db = 1;
724 guest_state->cs.attrib.fields.G = 1;
725 guest_state->cs.limit = 0xfffff;
726 guest_state->cs.base = 0;
728 struct vmcb_selector *segregs [] = {&(guest_state->ss), &(guest_state->ds), &(guest_state->es), &(guest_state->fs), &(guest_state->gs), NULL};
729 for ( i = 0; segregs[i] != NULL; i++) {
730 struct vmcb_selector * seg = segregs[i];
732 seg->selector = 2<<3;
733 seg->attrib.fields.type = 0x2; // Data Segment+read/write
734 seg->attrib.fields.S = 1;
735 seg->attrib.fields.P = 1;
736 seg->attrib.fields.db = 1;
737 seg->attrib.fields.G = 1;
738 seg->limit = 0xfffff;
744 /* JRL THIS HAS TO GO */
746 // guest_state->tr.selector = GetTR_Selector();
747 guest_state->tr.attrib.fields.type = 0x9;
748 guest_state->tr.attrib.fields.P = 1;
749 // guest_state->tr.limit = GetTR_Limit();
750 //guest_state->tr.base = GetTR_Base();// - 0x2000;
758 guest_state->efer |= EFER_MSR_svm_enable;
759 guest_state->rflags = 0x00000002; // The reserved bit is always 1
760 ctrl_area->svm_instrs.VMRUN = 1;
761 guest_state->cr0 = 0x00000001; // PE
762 ctrl_area->guest_ASID = 1;
765 // guest_state->cpl = 0;
771 ctrl_area->cr_writes.cr4 = 1;
773 ctrl_area->exceptions.de = 1;
774 ctrl_area->exceptions.df = 1;
775 ctrl_area->exceptions.pf = 1;
776 ctrl_area->exceptions.ts = 1;
777 ctrl_area->exceptions.ss = 1;
778 ctrl_area->exceptions.ac = 1;
779 ctrl_area->exceptions.mc = 1;
780 ctrl_area->exceptions.gp = 1;
781 ctrl_area->exceptions.ud = 1;
782 ctrl_area->exceptions.np = 1;
783 ctrl_area->exceptions.of = 1;
784 ctrl_area->exceptions.nmi = 1;
788 ctrl_area->instrs.IOIO_PROT = 1;
789 ctrl_area->IOPM_BASE_PA = (uint_t)V3_AllocPages(3);
793 tmp_reg.r_reg = ctrl_area->IOPM_BASE_PA;
794 memset((void*)(tmp_reg.e_reg.low), 0xffffffff, PAGE_SIZE * 2);
797 ctrl_area->instrs.INTR = 1;
804 memset(gdt_buf, 0, 6);
805 memset(idt_buf, 0, 6);
808 uint_t gdt_base, idt_base;
809 ushort_t gdt_limit, idt_limit;
812 gdt_base = *(ulong_t*)((uchar_t*)gdt_buf + 2) & 0xffffffff;
813 gdt_limit = *(ushort_t*)(gdt_buf) & 0xffff;
814 PrintDebug("GDT: base: %x, limit: %x\n", gdt_base, gdt_limit);
817 idt_base = *(ulong_t*)(idt_buf + 2) & 0xffffffff;
818 idt_limit = *(ushort_t*)(idt_buf) & 0xffff;
819 PrintDebug("IDT: base: %x, limit: %x\n",idt_base, idt_limit);
822 // gdt_base -= 0x2000;
823 //idt_base -= 0x2000;
825 guest_state->gdtr.base = gdt_base;
826 guest_state->gdtr.limit = gdt_limit;
827 guest_state->idtr.base = idt_base;
828 guest_state->idtr.limit = idt_limit;
834 // also determine if CPU supports nested paging
836 if (vm_info.page_tables) {
838 // Flush the TLB on entries/exits
839 ctrl_area->TLB_CONTROL = 1;
841 // Enable Nested Paging
842 ctrl_area->NP_ENABLE = 1;
844 PrintDebug("NP_Enable at 0x%x\n", &(ctrl_area->NP_ENABLE));
846 // Set the Nested Page Table pointer
847 ctrl_area->N_CR3 |= ((addr_t)vm_info.page_tables & 0xfffff000);
850 // ctrl_area->N_CR3 = Get_CR3();
851 // guest_state->cr3 |= (Get_CR3() & 0xfffff000);
853 guest_state->g_pat = 0x7040600070406ULL;
855 PrintDebug("Set Nested CR3: lo: 0x%x hi: 0x%x\n", (uint_t)*(&(ctrl_area->N_CR3)), (uint_t)*((unsigned char *)&(ctrl_area->N_CR3) + 4));
856 PrintDebug("Set Guest CR3: lo: 0x%x hi: 0x%x\n", (uint_t)*(&(guest_state->cr3)), (uint_t)*((unsigned char *)&(guest_state->cr3) + 4));
858 // guest_state->cr0 |= 0x80000000;