2 * This file is part of the Palacios Virtual Machine Monitor developed
3 * by the V3VEE Project with funding from the United States National
4 * Science Foundation and the Department of Energy.
6 * The V3VEE Project is a joint project between Northwestern University
7 * and the University of New Mexico. You can find out more at
10 * Copyright (c) 2008, Jack Lange <jarusl@cs.northwestern.edu>
11 * Copyright (c) 2008, The V3VEE Project <http://www.v3vee.org>
12 * All rights reserved.
14 * Author: Jack Lange <jarusl@cs.northwestern.edu>
16 * This is free software. You are permitted to use,
17 * redistribute, and modify it as specified in the file "V3VEE_LICENSE".
21 #include <palacios/svm.h>
22 #include <palacios/vmm.h>
24 #include <palacios/vmcb.h>
25 #include <palacios/vmm_mem.h>
26 #include <palacios/vmm_paging.h>
27 #include <palacios/svm_handler.h>
29 #include <palacios/vmm_debug.h>
30 #include <palacios/vm_guest_mem.h>
32 #include <palacios/vmm_decoder.h>
33 #include <palacios/vmm_string.h>
34 #include <palacios/vmm_lowlevel.h>
35 #include <palacios/svm_msr.h>
37 #include <palacios/vmm_rbtree.h>
39 #include <palacios/vmm_direct_paging.h>
41 #include <palacios/vmm_ctrl_regs.h>
42 #include <palacios/vmm_config.h>
43 #include <palacios/svm_io.h>
47 // This is a global pointer to the host's VMCB
48 static void * host_vmcb = NULL;
50 extern void v3_stgi();
51 extern void v3_clgi();
52 //extern int v3_svm_launch(vmcb_t * vmcb, struct v3_gprs * vm_regs, uint64_t * fs, uint64_t * gs);
53 extern int v3_svm_launch(vmcb_t * vmcb, struct v3_gprs * vm_regs, vmcb_t * host_vmcb);
56 static vmcb_t * Allocate_VMCB() {
57 vmcb_t * vmcb_page = (vmcb_t *)V3_VAddr(V3_AllocPages(1));
59 memset(vmcb_page, 0, 4096);
66 static void Init_VMCB_BIOS(vmcb_t * vmcb, struct guest_info *vm_info) {
67 vmcb_ctrl_t * ctrl_area = GET_VMCB_CTRL_AREA(vmcb);
68 vmcb_saved_state_t * guest_state = GET_VMCB_SAVE_STATE_AREA(vmcb);
73 guest_state->rsp = 0x00;
74 guest_state->rip = 0xfff0;
79 guest_state->efer |= EFER_MSR_svm_enable;
82 guest_state->rflags = 0x00000002; // The reserved bit is always 1
83 ctrl_area->svm_instrs.VMRUN = 1;
84 ctrl_area->svm_instrs.VMMCALL = 1;
85 ctrl_area->svm_instrs.VMLOAD = 1;
86 ctrl_area->svm_instrs.VMSAVE = 1;
87 ctrl_area->svm_instrs.STGI = 1;
88 ctrl_area->svm_instrs.CLGI = 1;
89 ctrl_area->svm_instrs.SKINIT = 1;
90 ctrl_area->svm_instrs.RDTSCP = 1;
91 ctrl_area->svm_instrs.ICEBP = 1;
92 ctrl_area->svm_instrs.WBINVD = 1;
93 ctrl_area->svm_instrs.MONITOR = 1;
94 ctrl_area->svm_instrs.MWAIT_always = 1;
95 ctrl_area->svm_instrs.MWAIT_if_armed = 1;
96 ctrl_area->instrs.INVLPGA = 1;
99 ctrl_area->instrs.HLT = 1;
100 // guest_state->cr0 = 0x00000001; // PE
103 ctrl_area->exceptions.de = 1;
104 ctrl_area->exceptions.df = 1;
106 ctrl_area->exceptions.ts = 1;
107 ctrl_area->exceptions.ss = 1;
108 ctrl_area->exceptions.ac = 1;
109 ctrl_area->exceptions.mc = 1;
110 ctrl_area->exceptions.gp = 1;
111 ctrl_area->exceptions.ud = 1;
112 ctrl_area->exceptions.np = 1;
113 ctrl_area->exceptions.of = 1;
115 ctrl_area->exceptions.nmi = 1;
119 ctrl_area->instrs.NMI = 1;
120 ctrl_area->instrs.SMI = 1;
121 ctrl_area->instrs.INIT = 1;
122 ctrl_area->instrs.PAUSE = 1;
123 ctrl_area->instrs.shutdown_evts = 1;
125 vm_info->vm_regs.rdx = 0x00000f00;
128 guest_state->cr0 = 0x60010010; // Set the WP flag so the memory hooks work in real-mode
131 guest_state->cs.selector = 0xf000;
132 guest_state->cs.limit = 0xffff;
133 guest_state->cs.base = 0x0000000f0000LL;
134 guest_state->cs.attrib.raw = 0xf3;
137 /* DEBUG FOR RETURN CODE */
138 ctrl_area->exit_code = 1;
141 struct vmcb_selector *segregs [] = {&(guest_state->ss), &(guest_state->ds),
142 &(guest_state->es), &(guest_state->fs),
143 &(guest_state->gs), NULL};
145 for ( i = 0; segregs[i] != NULL; i++) {
146 struct vmcb_selector * seg = segregs[i];
148 seg->selector = 0x0000;
149 // seg->base = seg->selector << 4;
150 seg->base = 0x00000000;
151 seg->attrib.raw = 0xf3;
155 guest_state->gdtr.limit = 0x0000ffff;
156 guest_state->gdtr.base = 0x0000000000000000LL;
157 guest_state->idtr.limit = 0x0000ffff;
158 guest_state->idtr.base = 0x0000000000000000LL;
160 guest_state->ldtr.selector = 0x0000;
161 guest_state->ldtr.limit = 0x0000ffff;
162 guest_state->ldtr.base = 0x0000000000000000LL;
163 guest_state->tr.selector = 0x0000;
164 guest_state->tr.limit = 0x0000ffff;
165 guest_state->tr.base = 0x0000000000000000LL;
168 guest_state->dr6 = 0x00000000ffff0ff0LL;
169 guest_state->dr7 = 0x0000000000000400LL;
172 v3_init_svm_io_map(vm_info);
173 ctrl_area->IOPM_BASE_PA = (addr_t)V3_PAddr(vm_info->io_map.arch_data);
174 ctrl_area->instrs.IOIO_PROT = 1;
178 v3_init_svm_msr_map(vm_info);
179 ctrl_area->MSRPM_BASE_PA = (addr_t)V3_PAddr(vm_info->msr_map.arch_data);
180 ctrl_area->instrs.MSR_PROT = 1;
184 PrintDebug("Exiting on interrupts\n");
185 ctrl_area->guest_ctrl.V_INTR_MASKING = 1;
186 ctrl_area->instrs.INTR = 1;
189 if (vm_info->shdw_pg_mode == SHADOW_PAGING) {
190 PrintDebug("Creating initial shadow page table\n");
192 /* JRL: This is a performance killer, and a simplistic solution */
193 /* We need to fix this */
194 ctrl_area->TLB_CONTROL = 1;
195 ctrl_area->guest_ASID = 1;
198 if (v3_init_passthrough_pts(vm_info) == -1) {
199 PrintError("Could not initialize passthrough page tables\n");
204 vm_info->shdw_pg_state.guest_cr0 = 0x0000000000000010LL;
205 PrintDebug("Created\n");
207 guest_state->cr3 = vm_info->direct_map_pt;
209 ctrl_area->cr_reads.cr0 = 1;
210 ctrl_area->cr_writes.cr0 = 1;
211 //ctrl_area->cr_reads.cr4 = 1;
212 ctrl_area->cr_writes.cr4 = 1;
213 ctrl_area->cr_reads.cr3 = 1;
214 ctrl_area->cr_writes.cr3 = 1;
216 v3_hook_msr(vm_info, EFER_MSR,
217 &v3_handle_efer_read,
218 &v3_handle_efer_write,
221 ctrl_area->instrs.INVLPG = 1;
223 ctrl_area->exceptions.pf = 1;
225 guest_state->g_pat = 0x7040600070406ULL;
227 guest_state->cr0 |= 0x80000000;
229 } else if (vm_info->shdw_pg_mode == NESTED_PAGING) {
230 // Flush the TLB on entries/exits
231 ctrl_area->TLB_CONTROL = 1;
232 ctrl_area->guest_ASID = 1;
234 // Enable Nested Paging
235 ctrl_area->NP_ENABLE = 1;
237 PrintDebug("NP_Enable at 0x%p\n", (void *)&(ctrl_area->NP_ENABLE));
239 // Set the Nested Page Table pointer
240 if (v3_init_passthrough_pts(vm_info) == -1) {
241 PrintError("Could not initialize Nested page tables\n");
245 ctrl_area->N_CR3 = vm_info->direct_map_pt;
247 guest_state->g_pat = 0x7040600070406ULL;
252 static int init_svm_guest(struct guest_info * info, struct v3_vm_config * config_ptr) {
255 v3_pre_config_guest(info, config_ptr);
257 PrintDebug("Allocating VMCB\n");
258 info->vmm_data = (void*)Allocate_VMCB();
260 PrintDebug("Initializing VMCB (addr=%p)\n", (void *)info->vmm_data);
261 Init_VMCB_BIOS((vmcb_t*)(info->vmm_data), info);
263 v3_post_config_guest(info, config_ptr);
268 static int start_svm_guest(struct guest_info *info) {
269 // vmcb_saved_state_t * guest_state = GET_VMCB_SAVE_STATE_AREA((vmcb_t*)(info->vmm_data));
270 // vmcb_ctrl_t * guest_ctrl = GET_VMCB_CTRL_AREA((vmcb_t*)(info->vmm_data));
271 uint_t num_exits = 0;
275 PrintDebug("Launching SVM VM (vmcb=%p)\n", (void *)info->vmm_data);
276 //PrintDebugVMCB((vmcb_t*)(info->vmm_data));
278 info->run_state = VM_RUNNING;
279 rdtscll(info->yield_start_cycle);
285 // Conditionally yield the CPU if the timeslice has expired
289 PrintDebug("SVM Entry to CS=%p rip=%p...\n",
290 (void *)(addr_t)info->segments.cs.base,
291 (void *)(addr_t)info->rip);
294 // disable global interrupts for vm state transition
299 rdtscll(info->time_state.cached_host_tsc);
300 // guest_ctrl->TSC_OFFSET = info->time_state.guest_tsc - info->time_state.cached_host_tsc;
302 v3_svm_launch((vmcb_t*)V3_PAddr(info->vmm_data), &(info->vm_regs), (vmcb_t *)host_vmcb);
307 //PrintDebug("SVM Returned\n");
309 // reenable global interrupts after vm exit
313 // Conditionally yield the CPU if the timeslice has expired
317 v3_update_time(info, tmp_tsc - info->time_state.cached_host_tsc);
320 if ((num_exits % 5000) == 0) {
321 PrintDebug("SVM Exit number %d\n", num_exits);
324 if (v3_handle_svm_exit(info) != 0) {
325 vmcb_ctrl_t * guest_ctrl = GET_VMCB_CTRL_AREA((vmcb_t*)(info->vmm_data));
327 addr_t linear_addr = 0;
329 info->run_state = VM_ERROR;
331 PrintDebug("SVM ERROR!!\n");
333 v3_print_guest_state(info);
335 PrintDebug("SVM Exit Code: %p\n", (void *)(addr_t)guest_ctrl->exit_code);
337 PrintDebug("exit_info1 low = 0x%.8x\n", *(uint_t*)&(guest_ctrl->exit_info1));
338 PrintDebug("exit_info1 high = 0x%.8x\n", *(uint_t *)(((uchar_t *)&(guest_ctrl->exit_info1)) + 4));
340 PrintDebug("exit_info2 low = 0x%.8x\n", *(uint_t*)&(guest_ctrl->exit_info2));
341 PrintDebug("exit_info2 high = 0x%.8x\n", *(uint_t *)(((uchar_t *)&(guest_ctrl->exit_info2)) + 4));
343 linear_addr = get_addr_linear(info, info->rip, &(info->segments.cs));
345 if (info->mem_mode == PHYSICAL_MEM) {
346 guest_pa_to_host_va(info, linear_addr, &host_addr);
347 } else if (info->mem_mode == VIRTUAL_MEM) {
348 guest_va_to_host_va(info, linear_addr, &host_addr);
351 PrintDebug("Host Address of rip = 0x%p\n", (void *)host_addr);
353 PrintDebug("Instr (15 bytes) at %p:\n", (void *)host_addr);
354 v3_dump_mem((uint8_t *)host_addr, 15);
366 /* Checks machine SVM capability */
367 /* Implemented from: AMD Arch Manual 3, sect 15.4 */
368 int v3_is_svm_capable() {
370 uint_t vm_cr_low = 0, vm_cr_high = 0;
371 addr_t eax = 0, ebx = 0, ecx = 0, edx = 0;
373 v3_cpuid(CPUID_EXT_FEATURE_IDS, &eax, &ebx, &ecx, &edx);
375 PrintDebug("CPUID_EXT_FEATURE_IDS_ecx=%p\n", (void *)ecx);
377 if ((ecx & CPUID_EXT_FEATURE_IDS_ecx_svm_avail) == 0) {
378 PrintDebug("SVM Not Available\n");
381 v3_get_msr(SVM_VM_CR_MSR, &vm_cr_high, &vm_cr_low);
383 PrintDebug("SVM_VM_CR_MSR = 0x%x 0x%x\n", vm_cr_high, vm_cr_low);
385 if ((vm_cr_low & SVM_VM_CR_MSR_svmdis) == 1) {
386 PrintDebug("SVM is available but is disabled.\n");
388 v3_cpuid(CPUID_SVM_REV_AND_FEATURE_IDS, &eax, &ebx, &ecx, &edx);
390 PrintDebug("CPUID_SVM_REV_AND_FEATURE_IDS_edx=%p\n", (void *)edx);
392 if ((edx & CPUID_SVM_REV_AND_FEATURE_IDS_edx_svml) == 0) {
393 PrintDebug("SVM BIOS Disabled, not unlockable\n");
395 PrintDebug("SVM is locked with a key\n");
400 PrintDebug("SVM is available and enabled.\n");
402 v3_cpuid(CPUID_SVM_REV_AND_FEATURE_IDS, &eax, &ebx, &ecx, &edx);
403 PrintDebug("CPUID_SVM_REV_AND_FEATURE_IDS_eax=%p\n", (void *)eax);
404 PrintDebug("CPUID_SVM_REV_AND_FEATURE_IDS_ebx=%p\n", (void *)ebx);
405 PrintDebug("CPUID_SVM_REV_AND_FEATURE_IDS_ecx=%p\n", (void *)ecx);
406 PrintDebug("CPUID_SVM_REV_AND_FEATURE_IDS_edx=%p\n", (void *)edx);
409 if ((edx & CPUID_SVM_REV_AND_FEATURE_IDS_edx_np) == 0) {
410 PrintDebug("SVM Nested Paging not supported\n");
412 PrintDebug("SVM Nested Paging supported\n");
420 static int has_svm_nested_paging() {
421 addr_t eax = 0, ebx = 0, ecx = 0, edx = 0;
423 v3_cpuid(CPUID_SVM_REV_AND_FEATURE_IDS, &eax, &ebx, &ecx, &edx);
425 //PrintDebug("CPUID_EXT_FEATURE_IDS_edx=0x%x\n", edx);
427 if ((edx & CPUID_SVM_REV_AND_FEATURE_IDS_edx_np) == 0) {
428 PrintDebug("SVM Nested Paging not supported\n");
431 PrintDebug("SVM Nested Paging supported\n");
438 void v3_init_SVM(struct v3_ctrl_ops * vmm_ops) {
440 extern v3_cpu_arch_t v3_cpu_type;
442 // Enable SVM on the CPU
443 v3_get_msr(EFER_MSR, &(msr.e_reg.high), &(msr.e_reg.low));
444 msr.e_reg.low |= EFER_MSR_svm_enable;
445 v3_set_msr(EFER_MSR, 0, msr.e_reg.low);
447 PrintDebug("SVM Enabled\n");
449 // Setup the host state save area
450 host_vmcb = V3_AllocPages(4);
453 // msr.e_reg.high = 0;
454 //msr.e_reg.low = (uint_t)host_vmcb;
455 msr.r_reg = (addr_t)host_vmcb;
457 PrintDebug("Host State being saved at %p\n", (void *)(addr_t)host_vmcb);
458 v3_set_msr(SVM_VM_HSAVE_PA_MSR, msr.e_reg.high, msr.e_reg.low);
463 if (has_svm_nested_paging() == 1) {
464 v3_cpu_type = V3_SVM_REV3_CPU;
466 v3_cpu_type = V3_SVM_CPU;
469 // Setup the SVM specific vmm operations
470 vmm_ops->init_guest = &init_svm_guest;
471 vmm_ops->start_guest = &start_svm_guest;
472 vmm_ops->has_nested_paging = &has_svm_nested_paging;
530 * Test VMSAVE/VMLOAD Latency
532 #define vmsave ".byte 0x0F,0x01,0xDB ; "
533 #define vmload ".byte 0x0F,0x01,0xDA ; "
535 uint32_t start_lo, start_hi;
536 uint32_t end_lo, end_hi;
539 __asm__ __volatile__ (
541 "movl %%eax, %%esi ; "
542 "movl %%edx, %%edi ; "
543 "movq %%rcx, %%rax ; "
546 : "=D"(start_hi), "=S"(start_lo), "=a"(end_lo),"=d"(end_hi)
547 : "c"(host_vmcb), "0"(0), "1"(0), "2"(0), "3"(0)
558 PrintDebug("VMSave Cycle Latency: %d\n", (uint32_t)(end - start));
560 __asm__ __volatile__ (
562 "movl %%eax, %%esi ; "
563 "movl %%edx, %%edi ; "
564 "movq %%rcx, %%rax ; "
567 : "=D"(start_hi), "=S"(start_lo), "=a"(end_lo),"=d"(end_hi)
568 : "c"(host_vmcb), "0"(0), "1"(0), "2"(0), "3"(0)
580 PrintDebug("VMLoad Cycle Latency: %d\n", (uint32_t)(end - start));
582 /* End Latency Test */
593 void Init_VMCB_pe(vmcb_t *vmcb, struct guest_info vm_info) {
594 vmcb_ctrl_t * ctrl_area = GET_VMCB_CTRL_AREA(vmcb);
595 vmcb_saved_state_t * guest_state = GET_VMCB_SAVE_STATE_AREA(vmcb);
599 guest_state->rsp = vm_info.vm_regs.rsp;
600 guest_state->rip = vm_info.rip;
603 /* I pretty much just gutted this from TVMM */
604 /* Note: That means its probably wrong */
606 // set the segment registers to mirror ours
607 guest_state->cs.selector = 1<<3;
608 guest_state->cs.attrib.fields.type = 0xa; // Code segment+read
609 guest_state->cs.attrib.fields.S = 1;
610 guest_state->cs.attrib.fields.P = 1;
611 guest_state->cs.attrib.fields.db = 1;
612 guest_state->cs.attrib.fields.G = 1;
613 guest_state->cs.limit = 0xfffff;
614 guest_state->cs.base = 0;
616 struct vmcb_selector *segregs [] = {&(guest_state->ss), &(guest_state->ds), &(guest_state->es), &(guest_state->fs), &(guest_state->gs), NULL};
617 for ( i = 0; segregs[i] != NULL; i++) {
618 struct vmcb_selector * seg = segregs[i];
620 seg->selector = 2<<3;
621 seg->attrib.fields.type = 0x2; // Data Segment+read/write
622 seg->attrib.fields.S = 1;
623 seg->attrib.fields.P = 1;
624 seg->attrib.fields.db = 1;
625 seg->attrib.fields.G = 1;
626 seg->limit = 0xfffff;
632 /* JRL THIS HAS TO GO */
634 // guest_state->tr.selector = GetTR_Selector();
635 guest_state->tr.attrib.fields.type = 0x9;
636 guest_state->tr.attrib.fields.P = 1;
637 // guest_state->tr.limit = GetTR_Limit();
638 //guest_state->tr.base = GetTR_Base();// - 0x2000;
646 guest_state->efer |= EFER_MSR_svm_enable;
647 guest_state->rflags = 0x00000002; // The reserved bit is always 1
648 ctrl_area->svm_instrs.VMRUN = 1;
649 guest_state->cr0 = 0x00000001; // PE
650 ctrl_area->guest_ASID = 1;
653 // guest_state->cpl = 0;
659 ctrl_area->cr_writes.cr4 = 1;
661 ctrl_area->exceptions.de = 1;
662 ctrl_area->exceptions.df = 1;
663 ctrl_area->exceptions.pf = 1;
664 ctrl_area->exceptions.ts = 1;
665 ctrl_area->exceptions.ss = 1;
666 ctrl_area->exceptions.ac = 1;
667 ctrl_area->exceptions.mc = 1;
668 ctrl_area->exceptions.gp = 1;
669 ctrl_area->exceptions.ud = 1;
670 ctrl_area->exceptions.np = 1;
671 ctrl_area->exceptions.of = 1;
672 ctrl_area->exceptions.nmi = 1;
676 ctrl_area->instrs.IOIO_PROT = 1;
677 ctrl_area->IOPM_BASE_PA = (uint_t)V3_AllocPages(3);
681 tmp_reg.r_reg = ctrl_area->IOPM_BASE_PA;
682 memset((void*)(tmp_reg.e_reg.low), 0xffffffff, PAGE_SIZE * 2);
685 ctrl_area->instrs.INTR = 1;
692 memset(gdt_buf, 0, 6);
693 memset(idt_buf, 0, 6);
696 uint_t gdt_base, idt_base;
697 ushort_t gdt_limit, idt_limit;
700 gdt_base = *(ulong_t*)((uchar_t*)gdt_buf + 2) & 0xffffffff;
701 gdt_limit = *(ushort_t*)(gdt_buf) & 0xffff;
702 PrintDebug("GDT: base: %x, limit: %x\n", gdt_base, gdt_limit);
705 idt_base = *(ulong_t*)(idt_buf + 2) & 0xffffffff;
706 idt_limit = *(ushort_t*)(idt_buf) & 0xffff;
707 PrintDebug("IDT: base: %x, limit: %x\n",idt_base, idt_limit);
710 // gdt_base -= 0x2000;
711 //idt_base -= 0x2000;
713 guest_state->gdtr.base = gdt_base;
714 guest_state->gdtr.limit = gdt_limit;
715 guest_state->idtr.base = idt_base;
716 guest_state->idtr.limit = idt_limit;
722 // also determine if CPU supports nested paging
724 if (vm_info.page_tables) {
726 // Flush the TLB on entries/exits
727 ctrl_area->TLB_CONTROL = 1;
729 // Enable Nested Paging
730 ctrl_area->NP_ENABLE = 1;
732 PrintDebug("NP_Enable at 0x%x\n", &(ctrl_area->NP_ENABLE));
734 // Set the Nested Page Table pointer
735 ctrl_area->N_CR3 |= ((addr_t)vm_info.page_tables & 0xfffff000);
738 // ctrl_area->N_CR3 = Get_CR3();
739 // guest_state->cr3 |= (Get_CR3() & 0xfffff000);
741 guest_state->g_pat = 0x7040600070406ULL;
743 PrintDebug("Set Nested CR3: lo: 0x%x hi: 0x%x\n", (uint_t)*(&(ctrl_area->N_CR3)), (uint_t)*((unsigned char *)&(ctrl_area->N_CR3) + 4));
744 PrintDebug("Set Guest CR3: lo: 0x%x hi: 0x%x\n", (uint_t)*(&(guest_state->cr3)), (uint_t)*((unsigned char *)&(guest_state->cr3) + 4));
746 // guest_state->cr0 |= 0x80000000;