2 * This file is part of the Palacios Virtual Machine Monitor developed
3 * by the V3VEE Project with funding from the United States National
4 * Science Foundation and the Department of Energy.
6 * The V3VEE Project is a joint project between Northwestern University
7 * and the University of New Mexico. You can find out more at
10 * Copyright (c) 2008, Jack Lange <jarusl@cs.northwestern.edu>
11 * Copyright (c) 2008, The V3VEE Project <http://www.v3vee.org>
12 * All rights reserved.
14 * Author: Jack Lange <jarusl@cs.northwestern.edu>
16 * This is free software. You are permitted to use,
17 * redistribute, and modify it as specified in the file "V3VEE_LICENSE".
21 /* This is the generic passthrough PCI virtual device */
24 * The basic idea is that we do not change the hardware PCI configuration
25 * Instead we modify the guest environment to map onto the physical configuration
27 * The pci subsystem handles most of the configuration space, except for the bar registers.
28 * We handle them here, by either letting them go directly to hardware or remapping through virtual hooks
30 * Memory Bars are always remapped via the shadow map,
31 * IO Bars are selectively remapped through hooks if the guest changes them
34 #include <palacios/vmm.h>
35 #include <palacios/vmm_dev_mgr.h>
36 #include <palacios/vmm_sprintf.h>
37 #include <palacios/vmm_lowlevel.h>
40 #include <devices/pci.h>
41 #include <devices/pci_types.h>
42 #include <devices/pci_passthrough.h>
45 // Hardcoded... Are these standard??
46 #define PCI_CFG_ADDR 0xcf8
47 #define PCI_CFG_DATA 0xcfc
50 #define PCI_DEV_MAX 32
53 #define PCI_DEVICE 0x0
54 #define PCI_PCI_BRIDGE 0x1
55 #define PCI_CARDBUS_BRIDGE 0x2
57 #define PCI_HDR_SIZE 256
70 } __attribute__((packed));
71 } __attribute__((packed));
74 typedef enum { PT_BAR_NONE,
79 PT_BAR_MEM64_HIGH } pt_bar_type_t;
91 uint8_t config_space[256];
92 struct pci_config_header real_hdr;
93 } __attribute__((packed));
95 struct pt_bar phys_bars[6];
96 struct pt_bar virt_bars[6];
99 struct vm_device * pci_bus;
100 struct pci_device * pci_dev;
102 union pci_addr_reg phys_pci_addr;
108 static inline uint32_t pci_cfg_read32(uint32_t addr) {
109 v3_outdw(PCI_CFG_ADDR, addr);
110 return v3_indw(PCI_CFG_DATA);
115 static inline void pci_cfg_write32(uint32_t addr, uint32_t val) {
116 v3_outdw(PCI_CFG_ADDR, addr);
117 v3_outdw(PCI_CFG_DATA, val);
122 static inline uint16_t pci_cfg_read16(uint32_t addr) {
123 v3_outw(PCI_CFG_ADDR, addr);
124 return v3_inw(PCI_CFG_DATA);
129 static inline void pci_cfg_write16(uint32_t addr, uint16_t val) {
130 v3_outw(PCI_CFG_ADDR, addr);
131 v3_outw(PCI_CFG_DATA, val);
136 static inline uint8_t pci_cfg_read8(uint32_t addr) {
137 v3_outb(PCI_CFG_ADDR, addr);
138 return v3_inb(PCI_CFG_DATA);
143 static inline void pci_cfg_write8(uint32_t addr, uint8_t val) {
144 v3_outb(PCI_CFG_ADDR, addr);
145 v3_outb(PCI_CFG_DATA, val);
149 // We initialize this
150 static int pci_bar_init(int bar_num, uint32_t * dst,void * private_data) {
151 struct vm_device * dev = (struct vm_device *)private_data;
152 struct pt_dev_state * state = (struct pt_dev_state *)dev->private_data;
153 const uint32_t bar_base_reg = 4;
154 union pci_addr_reg pci_addr = {state->phys_pci_addr.value};
155 uint32_t bar_val = 0;
156 uint32_t max_val = 0;
157 //addr_t irq_state = 0;
158 struct pt_bar * pbar = &(state->phys_bars[bar_num]);
161 // should read from cached header
162 pci_addr.reg = bar_base_reg + bar_num;
164 PrintDebug("PCI Address = 0x%x\n", pci_addr.value);
166 bar_val = pci_cfg_read32(pci_addr.value);
169 if ((bar_val & 0x3) == 0x1) {
173 pbar->type = PT_BAR_IO;
174 pbar->addr = PCI_IO_BASE(bar_val);
176 max_val = bar_val | PCI_IO_MASK;
178 // Cycle the physical bar, to determine the actual size
179 // Disable irqs, to try to prevent accesses to the space via a interrupt handler
180 // This is not SMP safe!!
181 // What we probably want to do is write a 0 to the command register
182 //irq_state = v3_irq_save();
184 pci_cfg_write32(pci_addr.value, max_val);
185 max_val = pci_cfg_read32(pci_addr.value);
186 pci_cfg_write32(pci_addr.value, bar_val);
188 //v3_irq_restore(irq_state);
190 pbar->size = ~PCI_IO_BASE(max_val) + 1;
193 // setup a set of null io hooks
194 // This allows the guest to do passthrough IO to these ports
195 // While still reserving them in the IO map
196 for (i = 0; i < pbar->size; i++) {
197 v3_hook_io_port(dev->vm, pbar->addr + i, NULL, NULL, NULL);
202 // might be memory, might be nothing
204 max_val = bar_val | PCI_MEM_MASK;
206 // Cycle the physical bar, to determine the actual size
207 // Disable irqs, to try to prevent accesses to the space via a interrupt handler
208 // This is not SMP safe!!
209 // What we probably want to do is write a 0 to the command register
210 //irq_state = v3_irq_save();
212 pci_cfg_write32(pci_addr.value, max_val);
213 max_val = pci_cfg_read32(pci_addr.value);
214 pci_cfg_write32(pci_addr.value, bar_val);
216 //v3_irq_restore(irq_state);
220 pbar->type = PT_BAR_NONE;
223 // if its a memory region, setup passthrough mem mapping
225 if ((bar_val & 0x6) == 0x0) {
227 pbar->type = PT_BAR_MEM32;
228 pbar->addr = PCI_MEM32_BASE(bar_val);
229 pbar->size = ~PCI_MEM32_BASE(max_val) + 1;
231 PrintDebug("Adding 32 bit PCI mem region: start=0x%x, end=0x%x\n",
232 pbar->addr, pbar->addr + pbar->size);
234 v3_add_shadow_mem(dev->vm,
236 pbar->addr + pbar->size - 1,
239 } else if ((bar_val & 0x6) == 0x2) {
241 pbar->type = PT_BAR_MEM24;
242 pbar->addr = PCI_MEM24_BASE(bar_val);
243 pbar->size = ~PCI_MEM24_BASE(max_val) + 1;
245 v3_add_shadow_mem(dev->vm,
247 pbar->addr + pbar->size - 1,
250 } else if ((bar_val & 0x6) == 0x4) {
252 PrintError("64 Bit PCI bars not supported\n");
255 PrintError("Invalid Memory bar type\n");
265 // Initially the virtual bars match the physical ones
266 memcpy(&(state->virt_bars[bar_num]), &(state->phys_bars[bar_num]), sizeof(struct pt_bar));
268 PrintDebug("bar_num=%d, bar_val=0x%x\n", bar_num, bar_val);
270 PrintDebug("phys bar type=%d, addr=0x%x, size=%d\n",
271 pbar->type, pbar->addr,
274 PrintDebug("virt bar type=%d, addr=0x%x, size=%d\n",
275 state->virt_bars[bar_num].type, state->virt_bars[bar_num].addr,
276 state->virt_bars[bar_num].size);
280 // Update the pci subsystem versions
286 static int pt_io_read(uint16_t port, void * dst, uint_t length, void * priv_data) {
287 struct pt_bar * pbar = (struct pt_bar *)priv_data;
288 int port_offset = port % pbar->size;
291 *(uint8_t *)dst = v3_inb(pbar->addr + port_offset);
292 } else if (length == 2) {
293 *(uint16_t *)dst = v3_inw(pbar->addr + port_offset);
294 } else if (length == 4) {
295 *(uint32_t *)dst = v3_indw(pbar->addr + port_offset);
297 PrintError("Invalid PCI passthrough IO Redirection size read\n");
305 static int pt_io_write(uint16_t port, void * src, uint_t length, void * priv_data) {
306 struct pt_bar * pbar = (struct pt_bar *)priv_data;
307 int port_offset = port % pbar->size;
310 v3_outb(pbar->addr + port_offset, *(uint8_t *)src);
311 } else if (length == 2) {
312 v3_outw(pbar->addr + port_offset, *(uint16_t *)src);
313 } else if (length == 4) {
314 v3_outdw(pbar->addr + port_offset, *(uint32_t *)src);
316 PrintError("Invalid PCI passthrough IO Redirection size write\n");
328 static int pci_bar_write(int bar_num, uint32_t * src, void * private_data) {
329 struct vm_device * dev = (struct vm_device *)private_data;
330 struct pt_dev_state * state = (struct pt_dev_state *)dev->private_data;
332 struct pt_bar * pbar = &(state->phys_bars[bar_num]);
333 struct pt_bar * vbar = &(state->virt_bars[bar_num]);
335 PrintDebug("Bar update src=0x%x\n", *src);
337 if (vbar->type == PT_BAR_NONE) {
339 } else if (vbar->type == PT_BAR_IO) {
343 for (i = 0; i < vbar->size; i++) {
344 if (v3_unhook_io_port(dev->vm, vbar->addr + i) == -1) {
345 PrintError("Could not unhook previously hooked port.... %d (0x%x)\n",
346 vbar->addr + i, vbar->addr + i);
351 PrintDebug("Setting IO Port range size=%d\n", pbar->size);
353 // clear the low bits to match the size
354 *src &= ~(pbar->size - 1);
357 *src |= (pbar->val & ~PCI_IO_MASK);
359 vbar->addr = PCI_IO_BASE(*src);
361 PrintDebug("Cooked src=0x%x\n", *src);
363 PrintDebug("Rehooking passthrough IO ports starting at %d (0x%x)\n",
364 vbar->addr, vbar->addr);
366 if (vbar->addr == pbar->addr) {
367 // Map the io ports as passthrough
368 for (i = 0; i < pbar->size; i++) {
369 v3_hook_io_port(dev->vm, pbar->addr + i, NULL, NULL, NULL);
372 // We have to manually handle the io redirection
373 for (i = 0; i < vbar->size; i++) {
374 v3_hook_io_port(dev->vm, vbar->addr + i, pt_io_read, pt_io_write, pbar);
377 } else if (vbar->type == PT_BAR_MEM32) {
378 // remove old mapping
379 struct v3_shadow_region * old_reg = v3_get_shadow_region(dev->vm, vbar->addr);
381 if (old_reg == NULL) {
383 PrintError("Could not find PCI Passthrough memory redirection region (addr=0x%x)\n", vbar->addr);
387 v3_delete_shadow_region(dev->vm, old_reg);
389 // clear the low bits to match the size
390 *src &= ~(pbar->size - 1);
393 *src |= (pbar->val & ~PCI_MEM_MASK);
395 PrintDebug("Cooked src=0x%x\n", *src);
397 vbar->addr = PCI_MEM32_BASE(*src);
399 PrintDebug("Adding pci Passthrough remapping: start=0x%x, size=%d, end=0x%x\n",
400 vbar->addr, vbar->size, vbar->addr + vbar->size);
402 v3_add_shadow_mem(dev->vm,
404 vbar->addr + vbar->size - 1,
408 PrintError("Unhandled Pasthrough PCI Bar type %d\n", vbar->type);
420 static int pt_config_update(uint_t reg_num, void * src, uint_t length, void * private_data) {
421 struct vm_device * dev = (struct vm_device *)private_data;
422 struct pt_dev_state * state = (struct pt_dev_state *)dev->private_data;
423 union pci_addr_reg pci_addr = {state->phys_pci_addr.value};
425 pci_addr.reg = reg_num;
428 pci_cfg_write8(pci_addr.value, *(uint8_t *)src);
429 } else if (length == 2) {
430 pci_cfg_write16(pci_addr.value, *(uint16_t *)src);
431 } else if (length == 4) {
432 pci_cfg_write32(pci_addr.value, *(uint32_t *)src);
441 static int find_real_pci_dev(uint16_t vendor_id, uint16_t device_id, struct pt_dev_state * state) {
442 union pci_addr_reg pci_addr = {0x80000000};
450 } __attribute__((packed));
451 } __attribute__((packed)) pci_hdr = {0};
455 for (i = 0, pci_addr.bus = 0; i < PCI_BUS_MAX; i++, pci_addr.bus++) {
456 for (j = 0, pci_addr.dev = 0; j < PCI_DEV_MAX; j++, pci_addr.dev++) {
457 for (k = 0, pci_addr.func = 0; k < PCI_FN_MAX; k++, pci_addr.func++) {
459 v3_outdw(PCI_CFG_ADDR, pci_addr.value);
460 pci_hdr.value = v3_indw(PCI_CFG_DATA);
462 if ((pci_hdr.vendor == vendor_id) && (pci_hdr.device == device_id)) {
463 uint32_t * cfg_space = (uint32_t *)&state->real_hdr;
465 state->phys_pci_addr = pci_addr;
467 // Copy the configuration space to the local cached version
468 for (m = 0, pci_addr.reg = 0; m < PCI_HDR_SIZE; m += 4, pci_addr.reg++) {
469 cfg_space[pci_addr.reg] = pci_cfg_read32(pci_addr.value);
473 PrintDebug("Found device %x:%x (bus=%d, dev=%d, func=%d)\n",
474 vendor_id, device_id,
475 pci_addr.bus, pci_addr.dev, pci_addr.func);
488 static int setup_virt_pci_dev(struct guest_info * info, struct vm_device * dev) {
489 struct pt_dev_state * state = (struct pt_dev_state *)dev->private_data;
490 struct pci_device * pci_dev = NULL;
491 struct v3_pci_bar bars[6];
495 for (i = 0; i < 6; i++) {
496 bars[i].type = PCI_BAR_PASSTHROUGH;
497 bars[i].private_data = dev;
498 bars[i].bar_init = pci_bar_init;
499 bars[i].bar_write = pci_bar_write;
502 pci_dev = v3_pci_register_device(state->pci_bus,
506 pt_config_update, NULL, NULL,
509 // This will overwrite the bar registers.. but that should be ok.
510 memcpy(pci_dev->config_space, (uint8_t *)&(state->real_hdr), sizeof(struct pci_config_header));
512 state->pci_dev = pci_dev;
518 static struct v3_device_ops dev_ops = {
527 static int irq_handler(struct guest_info * info, struct v3_interrupt * intr, void * private_data) {
528 struct vm_device * dev = (struct vm_device *)private_data;
529 struct pt_dev_state * state = (struct pt_dev_state *)dev->private_data;
531 PrintDebug("Handling E1000 IRQ %d\n", intr->irq);
533 v3_pci_raise_irq(state->pci_bus, 0, state->pci_dev);
535 V3_ACK_IRQ(intr->irq);
543 static int passthrough_init(struct guest_info * info, void * cfg_data) {
544 struct pci_passthrough_cfg * cfg = (struct pci_passthrough_cfg *)cfg_data;
545 struct pt_dev_state * state = V3_Malloc(sizeof(struct pt_dev_state));
546 struct vm_device * dev = NULL;
547 struct vm_device * pci = v3_find_dev(info, cfg->pci_bus_name);
550 memset(state, 0, sizeof(struct pt_dev_state));
553 PrintError("Could not find PCI device\n");
557 state->pci_bus = pci;
558 strncpy(state->name, cfg->name, 32);
563 dev = v3_allocate_device("PCI_PASSTHROUGH", &dev_ops, state);
565 if (v3_attach_device(info, dev) == -1) {
566 PrintError("Could not attach device %s\n", "PCI_PASSTHROUGH");
571 if (find_real_pci_dev(cfg->vendor_id, cfg->device_id, state) == -1) {
572 PrintError("Could not find PCI Device %x:%x\n", cfg->vendor_id, cfg->device_id);
576 setup_virt_pci_dev(info, dev);
578 v3_hook_irq(info, 59, irq_handler, dev);
586 device_register("PCI_PASSTHROUGH", passthrough_init)