2 * This file is part of the Palacios Virtual Machine Monitor developed
3 * by the V3VEE Project with funding from the United States National
4 * Science Foundation and the Department of Energy.
6 * The V3VEE Project is a joint project between Northwestern University
7 * and the University of New Mexico. You can find out more at
10 * Copyright (c) 2009, Lei Xia <lxia@northwestern.edu>
11 * Copyright (c) 2009, Chang Seok Bae <jhuell@gmail.com>
12 * Copyright (c) 2009, Jack Lange <jarusl@cs.northwestern.edu>
13 * Copyright (c) 2009, The V3VEE Project <http://www.v3vee.org>
14 * All rights reserved.
16 * Author: Lei Xia <lxia@northwestern.edu>
17 * Chang Seok Bae <jhuell@gmail.com>
18 * Jack Lange <jarusl@cs.northwestern.edu>
20 * This is free software. You are permitted to use,
21 * redistribute, and modify it as specified in the file "V3VEE_LICENSE".
26 #include <palacios/vmm.h>
27 #include <palacios/vmm_types.h>
28 #include <palacios/vmm_io.h>
29 #include <palacios/vmm_intr.h>
30 #include <palacios/vmm_rbtree.h>
32 #include <devices/pci.h>
33 #include <devices/pci_types.h>
37 #define PrintDebug(fmt, args...)
41 #define CONFIG_ADDR_PORT 0x0cf8
42 #define CONFIG_DATA_PORT 0x0cfc
45 #define PCI_BUS_COUNT 1
47 // This must always be a multiple of 8
48 #define MAX_BUS_DEVICES 32
61 } __attribute__((packed));
62 } __attribute__((packed));
63 } __attribute__((packed));
72 // Red Black tree containing all attached devices
73 struct rb_root devices;
75 // Bitmap of the allocated device numbers
76 uint8_t dev_map[MAX_BUS_DEVICES / 8];
82 // Configuration address register
83 struct pci_addr_reg addr_reg;
86 struct pci_bus bus_list[PCI_BUS_COUNT];
95 static void pci_dump_state(struct pci_internal * pci_state) {
96 struct rb_node * node = v3_rb_first(&(pci_state->bus_list[0].devices));
97 struct pci_device * tmp_dev = NULL;
99 PrintDebug("===PCI: Dumping state Begin ==========\n");
102 tmp_dev = rb_entry(node, struct pci_device, dev_tree_node);
104 PrintDebug("PCI Device Number: %d (%s):\n", tmp_dev->dev_num, tmp_dev->name);
105 PrintDebug("irq = %d\n", tmp_dev->config_header.intr_line);
106 PrintDebug("Vend ID: 0x%x\n", tmp_dev->config_header.vendor_id);
107 PrintDebug("Device ID: 0x%x\n", tmp_dev->config_header.device_id);
109 } while ((node = v3_rb_next(node)));
111 PrintDebug("====PCI: Dumping state End==========\n");
119 // Scan the dev_map bitmap for the first '0' bit
120 static int get_free_dev_num(struct pci_bus * bus) {
123 for (i = 0; i < sizeof(bus->dev_map); i++) {
124 if (bus->dev_map[i] != 0xff) {
126 for (j = 0; j < 8; j++) {
127 if (!(bus->dev_map[i] & (0x1 << j))) {
128 return ((i * 8) + j);
137 static void allocate_dev_num(struct pci_bus * bus, int dev_num) {
138 int major = (dev_num / 8);
139 int minor = dev_num % 8;
141 bus->dev_map[major] |= (0x1 << minor);
147 struct pci_device * __add_device_to_bus(struct pci_bus * bus, struct pci_device * dev) {
149 struct rb_node ** p = &(bus->devices.rb_node);
150 struct rb_node * parent = NULL;
151 struct pci_device * tmp_dev = NULL;
155 tmp_dev = rb_entry(parent, struct pci_device, dev_tree_node);
157 if (dev->devfn < tmp_dev->devfn) {
159 } else if (dev->devfn > tmp_dev->devfn) {
166 rb_link_node(&(dev->dev_tree_node), parent, p);
173 struct pci_device * add_device_to_bus(struct pci_bus * bus, struct pci_device * dev) {
175 struct pci_device * ret = NULL;
177 if ((ret = __add_device_to_bus(bus, dev))) {
181 v3_rb_insert_color(&(dev->dev_tree_node), &(bus->devices));
183 allocate_dev_num(bus, dev->dev_num);
189 static struct pci_device * get_device(struct pci_bus * bus, uint8_t dev_num, uint8_t fn_num) {
190 struct rb_node * n = bus->devices.rb_node;
191 struct pci_device * dev = NULL;
192 uint8_t devfn = ((dev_num & 0x1f) << 3) | (fn_num & 0x7);
195 dev = rb_entry(n, struct pci_device, dev_tree_node);
197 if (devfn < dev->devfn) {
199 } else if (devfn > dev->devfn) {
215 static int addr_port_read(ushort_t port, void * dst, uint_t length, struct vm_device * dev) {
216 struct pci_internal * pci_state = (struct pci_internal *)dev->private_data;
217 int reg_offset = port & 0x3;
218 uint8_t * reg_addr = ((uint8_t *)&(pci_state->addr_reg.val)) + reg_offset;
220 PrintDebug("Reading PCI Address Port (%x): %x len=%d\n", port, pci_state->addr_reg.val, length);
223 if (reg_offset != 0) {
224 PrintError("Invalid Address Port Read\n");
227 *(uint32_t *)dst = *(uint32_t *)reg_addr;
228 } else if (length == 2) {
229 if (reg_offset > 2) {
230 PrintError("Invalid Address Port Read\n");
233 *(uint16_t *)dst = *(uint16_t *)reg_addr;
234 } else if (length == 1) {
235 *(uint8_t *)dst = *(uint8_t *)reg_addr;
237 PrintError("Invalid read length (%d) for PCI address register\n", length);
246 static int addr_port_write(ushort_t port, void * src, uint_t length, struct vm_device * dev) {
247 struct pci_internal * pci_state = (struct pci_internal *)dev->private_data;
248 int reg_offset = port & 0x3;
249 uint8_t * reg_addr = ((uint8_t *)&(pci_state->addr_reg.val)) + reg_offset;
253 if (reg_offset != 0) {
254 PrintError("Invalid Address Port Write\n");
258 PrintDebug("Writing PCI 4 bytes Val=%x\n", *(uint32_t *)src);
260 *(uint32_t *)reg_addr = *(uint32_t *)src;
261 } else if (length == 2) {
262 if (reg_offset > 2) {
263 PrintError("Invalid Address Port Write\n");
267 PrintDebug("Writing PCI 2 byte Val=%x\n", *(uint16_t *)src);
269 *(uint16_t *)reg_addr = *(uint16_t *)src;
270 } else if (length == 1) {
271 PrintDebug("Writing PCI 1 byte Val=%x\n", *(uint8_t *)src);
272 *(uint8_t *)reg_addr = *(uint8_t *)src;
274 PrintError("Invalid write length (%d) for PCI address register\n", length);
278 PrintDebug("Writing PCI Address Port(%x): %x\n", port, pci_state->addr_reg.val);
284 static int data_port_read(ushort_t port, void * dst, uint_t length, struct vm_device * vmdev) {
285 struct pci_internal * pci_state = (struct pci_internal *)(vmdev->private_data);
286 struct pci_device * pci_dev = NULL;
287 uint_t reg_num = (pci_state->addr_reg.reg_num << 2) + (port & 0x3);
290 if (pci_state->addr_reg.bus_num != 0) {
292 for (i = 0; i < length; i++) {
293 *((uint8_t *)dst + i) = 0xff;
299 PrintDebug("Reading PCI Data register. bus = %d, dev = %d, reg = %d (%x), cfg_reg = %x\n",
300 pci_state->addr_reg.bus_num,
301 pci_state->addr_reg.dev_num,
303 pci_state->addr_reg.val);
305 pci_dev = get_device(&(pci_state->bus_list[0]), pci_state->addr_reg.dev_num, pci_state->addr_reg.fn_num);
307 if (pci_dev == NULL) {
308 for (i = 0; i < length; i++) {
309 *(uint8_t *)((uint8_t *)dst + i) = 0xff;
315 for (i = 0; i < length; i++) {
316 *(uint8_t *)((uint8_t *)dst + i) = pci_dev->config_space[reg_num + i];
319 PrintDebug("\tVal=%x, len=%d\n", *(uint32_t *)dst, length);
325 static inline int is_cfg_reg_writable(uchar_t header_type, int reg_num) {
326 if (header_type == 0x00) {
344 } else if (header_type == 0x80) {
363 // PCI to PCI Bridge = 0x01
364 // CardBus Bridge = 0x02
367 PrintError("Invalid PCI Header type (0x%.2x)\n", header_type);
374 static int bar_update(struct pci_device * pci, int bar_num, uint32_t new_val) {
375 struct v3_pci_bar * bar = &(pci->bar[bar_num]);
377 PrintDebug("Updating BAR Register (Dev=%s) (bar=%d) (old_val=%x) (new_val=%x)\n",
378 pci->name, bar_num, bar->val, new_val);
384 PrintDebug("\tRehooking %d IO ports from base %x to %x\n",
385 bar->num_ports, PCI_IO_BASE(bar->val), PCI_IO_BASE(new_val));
387 // only do this if pci device is enabled....
388 for (i = 0; i < bar->num_ports; i++) {
390 v3_dev_unhook_io(pci->vm_dev, PCI_IO_BASE(bar->val) + i);
392 v3_dev_hook_io(pci->vm_dev, PCI_IO_BASE(new_val) + i,
393 bar->io_read, bar->io_write);
400 case PCI_BAR_MEM32: {
401 v3_unhook_mem(pci->vm_dev->vm, (addr_t)(bar->val));
404 v3_hook_full_mem(pci->vm_dev->vm, PCI_MEM32_BASE(new_val),
405 PCI_MEM32_BASE(new_val) + (bar->num_pages * PAGE_SIZE_4KB),
406 bar->mem_read, bar->mem_write, pci->vm_dev);
408 PrintError("Write hooks not supported for PCI\n");
417 PrintDebug("Reprogramming an unsupported BAR register (Dev=%s) (bar=%d) (val=%x)\n",
418 pci->name, bar_num, new_val);
422 PrintError("Invalid Bar Reg updated (bar=%d)\n", bar_num);
430 static int data_port_write(ushort_t port, void * src, uint_t length, struct vm_device * vmdev) {
431 struct pci_internal * pci_state = (struct pci_internal *)vmdev->private_data;
432 struct pci_device * pci_dev = NULL;
433 uint_t reg_num = (pci_state->addr_reg.reg_num << 2) + (port & 0x3);
437 if (pci_state->addr_reg.bus_num != 0) {
441 PrintDebug("Writing PCI Data register. bus = %d, dev = %d, reg = %d (%x) addr_reg = %x (val=%x, len=%d)\n",
442 pci_state->addr_reg.bus_num,
443 pci_state->addr_reg.dev_num,
445 pci_state->addr_reg.val,
446 *(uint32_t *)src, length);
449 pci_dev = get_device(&(pci_state->bus_list[0]), pci_state->addr_reg.dev_num, pci_state->addr_reg.fn_num);
451 if (pci_dev == NULL) {
452 PrintError("Writing configuration space for non-present device (dev_num=%d)\n",
453 pci_state->addr_reg.dev_num);
458 for (i = 0; i < length; i++) {
459 uint_t cur_reg = reg_num + i;
460 int writable = is_cfg_reg_writable(pci_dev->config_header.header_type, cur_reg);
462 if (writable == -1) {
463 PrintError("Invalid PCI configuration space\n");
468 pci_dev->config_space[cur_reg] = *(uint8_t *)((uint8_t *)src + i);
470 if ((cur_reg >= 0x10) && (cur_reg < 0x28)) {
471 // BAR Register Update
472 int bar_reg = ((cur_reg & ~0x3) - 0x10) / 4;
474 pci_dev->bar_update_flag = 1;
475 pci_dev->bar[bar_reg].updated = 1;
477 // PrintDebug("Updating BAR register %d\n", bar_reg);
479 } else if ((cur_reg >= 0x30) && (cur_reg < 0x34)) {
480 // Extension ROM update
482 pci_dev->ext_rom_update_flag = 1;
483 } else if (cur_reg == 0x04) {
485 uint8_t command = *((uint8_t *)src + i);
487 PrintError("command update for %s old=%x new=%x\n",
489 pci_dev->config_space[cur_reg],command);
491 pci_dev->config_space[cur_reg] = command;
493 if (pci_dev->cmd_update) {
494 pci_dev->cmd_update(pci_dev, (command & 0x01), (command & 0x02));
497 } else if (cur_reg == 0x0f) {
499 pci_dev->config_header.BIST = 0x00;
504 if (pci_dev->config_update) {
505 pci_dev->config_update(pci_dev, reg_num, length);
508 // Scan for BAR updated
509 if (pci_dev->bar_update_flag) {
510 for (i = 0; i < 6; i++) {
511 if (pci_dev->bar[i].updated) {
512 int bar_offset = 0x10 + 4 * i;
514 *(uint32_t *)(pci_dev->config_space + bar_offset) &= pci_dev->bar[i].mask;
515 // check special flags....
518 if (bar_update(pci_dev, i, *(uint32_t *)(pci_dev->config_space + bar_offset)) == -1) {
519 PrintError("PCI Device %s: Bar update Error Bar=%d\n", pci_dev->name, i);
523 pci_dev->bar[i].updated = 0;
526 pci_dev->bar_update_flag = 0;
529 if ((pci_dev->ext_rom_update_flag) && (pci_dev->ext_rom_update)) {
530 pci_dev->ext_rom_update(pci_dev);
531 pci_dev->ext_rom_update_flag = 0;
540 static int pci_reset_device(struct vm_device * dev) {
541 PrintDebug("pci: reset device\n");
546 static int pci_start_device(struct vm_device * dev) {
547 PrintDebug("pci: start device\n");
552 static int pci_stop_device(struct vm_device * dev) {
553 PrintDebug("pci: stop device\n");
559 static int pci_deinit_device(struct vm_device * dev) {
562 for (i = 0; i < 4; i++){
563 v3_dev_unhook_io(dev, CONFIG_ADDR_PORT + i);
564 v3_dev_unhook_io(dev, CONFIG_DATA_PORT + i);
572 static void init_pci_busses(struct pci_internal * pci_state) {
575 for (i = 0; i < PCI_BUS_COUNT; i++) {
576 pci_state->bus_list[i].bus_num = i;
577 pci_state->bus_list[i].devices.rb_node = NULL;
578 memset(pci_state->bus_list[i].dev_map, 0, sizeof(pci_state->bus_list[i].dev_map));
584 static int pci_init_device(struct vm_device * dev) {
585 struct pci_internal * pci_state = (struct pci_internal *)dev->private_data;
588 PrintDebug("pci: init_device\n");
591 // dev->vm->pci = dev; //should be in vmm_config.c
593 pci_state->addr_reg.val = 0;
595 init_pci_busses(pci_state);
597 PrintDebug("Sizeof config header=%d\n", (int)sizeof(struct pci_config_header));
599 for (i = 0; i < 4; i++) {
600 v3_dev_hook_io(dev, CONFIG_ADDR_PORT + i, &addr_port_read, &addr_port_write);
601 v3_dev_hook_io(dev, CONFIG_DATA_PORT + i, &data_port_read, &data_port_write);
608 static struct vm_device_ops dev_ops = {
609 .init = pci_init_device,
610 .deinit = pci_deinit_device,
611 .reset = pci_reset_device,
612 .start = pci_start_device,
613 .stop = pci_stop_device,
617 struct vm_device * v3_create_pci() {
618 struct pci_internal * pci_state = V3_Malloc(sizeof(struct pci_internal));
620 PrintDebug("PCI internal at %p\n",(void *)pci_state);
622 struct vm_device * device = v3_create_device("PCI", &dev_ops, pci_state);
629 static inline int init_bars(struct pci_device * pci_dev) {
632 for (i = 0; i < 6; i++) {
633 int bar_offset = 0x10 + (4 * i);
635 if (pci_dev->bar[i].type == PCI_BAR_IO) {
637 pci_dev->bar[i].mask = (~((pci_dev->bar[i].num_ports) - 1)) | 0x01;
639 pci_dev->bar[i].val = pci_dev->bar[i].default_base_port & pci_dev->bar[i].mask;
640 pci_dev->bar[i].val |= 0x00000001;
642 for (j = 0; j < pci_dev->bar[i].num_ports; j++) {
644 if (v3_dev_hook_io(pci_dev->vm_dev, pci_dev->bar[i].default_base_port + j,
645 pci_dev->bar[i].io_read, pci_dev->bar[i].io_write) == -1) {
646 PrintError("Could not hook default io port %x\n", pci_dev->bar[i].default_base_port + j);
651 *(uint32_t *)(pci_dev->config_space + bar_offset) = pci_dev->bar[i].val;
653 } else if (pci_dev->bar[i].type == PCI_BAR_MEM32) {
654 pci_dev->bar[i].mask = ~((pci_dev->bar[i].num_pages << 12) - 1);
655 pci_dev->bar[i].mask |= 0xf; // preserve the configuration flags
657 pci_dev->bar[i].val = pci_dev->bar[i].default_base_addr & pci_dev->bar[i].mask;
660 if (pci_dev->bar[i].mem_read) {
662 v3_hook_full_mem(pci_dev->vm_dev->vm, pci_dev->bar[i].default_base_addr,
663 pci_dev->bar[i].default_base_addr + (pci_dev->bar[i].num_pages * PAGE_SIZE_4KB),
664 pci_dev->bar[i].mem_read, pci_dev->bar[i].mem_write, pci_dev->vm_dev);
665 } else if (pci_dev->bar[i].mem_write) {
667 PrintError("Write hooks not supported for PCI devices\n");
670 v3_hook_write_mem(pci_dev->vm_dev->vm, pci_dev->bar[i].default_base_addr,
671 pci_dev->bar[i].default_base_addr + (pci_dev->bar[i].num_pages * PAGE_SIZE_4KB),
672 pci_dev->bar[i].mem_write, pci_dev->vm_dev);
675 // set the prefetchable flag...
676 pci_dev->bar[i].val |= 0x00000008;
680 *(uint32_t *)(pci_dev->config_space + bar_offset) = pci_dev->bar[i].val;
682 } else if (pci_dev->bar[i].type == PCI_BAR_MEM16) {
683 PrintError("16 Bit memory ranges not supported (reg: %d)\n", i);
685 } else if (pci_dev->bar[i].type == PCI_BAR_NONE) {
686 pci_dev->bar[i].val = 0x00000000;
687 pci_dev->bar[i].mask = 0x00000000; // This ensures that all updates will be dropped
688 *(uint32_t *)(pci_dev->config_space + bar_offset) = pci_dev->bar[i].val;
690 PrintError("Invalid BAR type for bar #%d\n", i);
699 // if dev_num == -1, auto assign
700 struct pci_device * v3_pci_register_device(struct vm_device * pci,
701 pci_device_type_t dev_type,
706 struct v3_pci_bar * bars,
707 int (*config_update)(struct pci_device * pci_dev, uint_t reg_num, int length),
708 int (*cmd_update)(struct pci_device *pci_dev, uchar_t io_enabled, uchar_t mem_enabled),
709 int (*ext_rom_update)(struct pci_device * pci_dev),
710 struct vm_device * dev) {
712 struct pci_internal * pci_state = (struct pci_internal *)pci->private_data;
713 struct pci_bus * bus = &(pci_state->bus_list[bus_num]);
714 struct pci_device * pci_dev = NULL;
717 if (dev_num > MAX_BUS_DEVICES) {
718 PrintError("Requested Invalid device number (%d)\n", dev_num);
723 if ((dev_num = get_free_dev_num(bus)) == -1) {
724 PrintError("No more available PCI slots on bus %d\n", bus->bus_num);
729 if (get_device(bus, dev_num, fn_num) != NULL) {
730 PrintError("PCI Device already registered at slot %d on bus %d\n",
731 dev_num, bus->bus_num);
736 pci_dev = (struct pci_device *)V3_Malloc(sizeof(struct pci_device));
738 if (pci_dev == NULL) {
739 PrintError("Could not allocate pci device\n");
743 memset(pci_dev, 0, sizeof(struct pci_device));
748 pci_dev->config_header.header_type = 0x00;
750 case PCI_MULTIFUNCTION:
751 pci_dev->config_header.header_type = 0x80;
754 PrintError("Unhandled PCI Device Type: %d\n", dev_type);
758 pci_dev->bus_num = bus_num;
759 pci_dev->dev_num = dev_num;
760 pci_dev->fn_num = fn_num;
762 strncpy(pci_dev->name, name, sizeof(pci_dev->name));
763 pci_dev->vm_dev = dev;
765 // register update callbacks
766 pci_dev->config_update = config_update;
767 pci_dev->cmd_update = cmd_update;
768 pci_dev->ext_rom_update = ext_rom_update;
772 for (i = 0; i < 6; i ++) {
773 pci_dev->bar[i].type = bars[i].type;
775 if (pci_dev->bar[i].type == PCI_BAR_IO) {
776 pci_dev->bar[i].num_ports = bars[i].num_ports;
777 pci_dev->bar[i].default_base_port = bars[i].default_base_port;
778 pci_dev->bar[i].io_read = bars[i].io_read;
779 pci_dev->bar[i].io_write = bars[i].io_write;
780 } else if (pci_dev->bar[i].type == PCI_BAR_MEM32) {
781 pci_dev->bar[i].num_pages = bars[i].num_pages;
782 pci_dev->bar[i].default_base_addr = bars[i].default_base_addr;
783 pci_dev->bar[i].mem_read = bars[i].mem_read;
784 pci_dev->bar[i].mem_write = bars[i].mem_write;
786 pci_dev->bar[i].num_pages = 0;
787 pci_dev->bar[i].default_base_addr = 0;
788 pci_dev->bar[i].mem_read = NULL;
789 pci_dev->bar[i].mem_write = NULL;
793 if (init_bars(pci_dev) == -1) {
794 PrintError("could not initialize bar registers\n");
799 add_device_to_bus(bus, pci_dev);
802 pci_dump_state(pci_state);