2 * This file is part of the Palacios Virtual Machine Monitor developed
3 * by the V3VEE Project with funding from the United States National
4 * Science Foundation and the Department of Energy.
6 * The V3VEE Project is a joint project between Northwestern University
7 * and the University of New Mexico. You can find out more at
10 * Copyright (c) 2009, Jack Lange <jarusl@cs.northwestern.edu>
11 * Copyright (c) 2009, Lei Xia <lxia@northwestern.edu>
12 * Copyright (c) 2009, Chang Seok Bae <jhuell@gmail.com>
13 * Copyright (c) 2009, The V3VEE Project <http://www.v3vee.org>
14 * All rights reserved.
16 * Author: Jack Lange <jarusl@cs.northwestern.edu>
17 * Lei Xia <lxia@northwestern.edu>
18 * Chang Seok Bae <jhuell@gmail.com>
20 * This is free software. You are permitted to use,
21 * redistribute, and modify it as specified in the file "V3VEE_LICENSE".
26 #include <palacios/vmm.h>
27 #include <palacios/vmm_types.h>
28 #include <palacios/vmm_io.h>
29 #include <palacios/vmm_intr.h>
30 #include <palacios/vmm_rbtree.h>
32 #include <devices/pci.h>
33 #include <devices/pci_types.h>
35 #ifndef CONFIG_DEBUG_PCI
37 #define PrintDebug(fmt, args...)
41 #define CONFIG_ADDR_PORT 0x0cf8
42 #define CONFIG_DATA_PORT 0x0cfc
44 #define PCI_DEV_IO_PORT_BASE 0xc000
46 #define PCI_BUS_COUNT 1
48 // This must always be a multiple of 8
49 #define MAX_BUS_DEVICES 32
62 } __attribute__((packed));
63 } __attribute__((packed));
64 } __attribute__((packed));
73 // Red Black tree containing all attached devices
74 struct rb_root devices;
76 // Bitmap of the allocated device numbers
77 uint8_t dev_map[MAX_BUS_DEVICES / 8];
80 int (*raise_pci_irq)(struct vm_device * dev, struct pci_device * pci_dev);
81 int (*lower_pci_irq)(struct vm_device * dev, struct pci_device * pci_dev);
82 struct vm_device * irq_bridge_dev;
88 // Configuration address register
89 struct pci_addr_reg addr_reg;
91 // Base IO Port which PCI devices will register with...
95 struct pci_bus bus_list[PCI_BUS_COUNT];
102 #ifdef CONFIG_DEBUG_PCI
104 static void pci_dump_state(struct pci_internal * pci_state) {
105 struct rb_node * node = v3_rb_first(&(pci_state->bus_list[0].devices));
106 struct pci_device * tmp_dev = NULL;
108 PrintDebug("===PCI: Dumping state Begin ==========\n");
111 tmp_dev = rb_entry(node, struct pci_device, dev_tree_node);
113 PrintDebug("PCI Device Number: %d (%s):\n", tmp_dev->dev_num, tmp_dev->name);
114 PrintDebug("irq = %d\n", tmp_dev->config_header.intr_line);
115 PrintDebug("Vend ID: 0x%x\n", tmp_dev->config_header.vendor_id);
116 PrintDebug("Device ID: 0x%x\n", tmp_dev->config_header.device_id);
118 } while ((node = v3_rb_next(node)));
120 PrintDebug("====PCI: Dumping state End==========\n");
128 // Scan the dev_map bitmap for the first '0' bit
129 static int get_free_dev_num(struct pci_bus * bus) {
132 for (i = 0; i < sizeof(bus->dev_map); i++) {
133 PrintDebug("i=%d\n", i);
134 if (bus->dev_map[i] != 0xff) {
136 for (j = 0; j < 8; j++) {
137 PrintDebug("\tj=%d\n", j);
138 if (!(bus->dev_map[i] & (0x1 << j))) {
139 return ((i * 8) + j);
148 static void allocate_dev_num(struct pci_bus * bus, int dev_num) {
149 int major = (dev_num / 8);
150 int minor = dev_num % 8;
152 bus->dev_map[major] |= (0x1 << minor);
158 struct pci_device * __add_device_to_bus(struct pci_bus * bus, struct pci_device * dev) {
160 struct rb_node ** p = &(bus->devices.rb_node);
161 struct rb_node * parent = NULL;
162 struct pci_device * tmp_dev = NULL;
166 tmp_dev = rb_entry(parent, struct pci_device, dev_tree_node);
168 if (dev->devfn < tmp_dev->devfn) {
170 } else if (dev->devfn > tmp_dev->devfn) {
177 rb_link_node(&(dev->dev_tree_node), parent, p);
184 struct pci_device * add_device_to_bus(struct pci_bus * bus, struct pci_device * dev) {
186 struct pci_device * ret = NULL;
188 if ((ret = __add_device_to_bus(bus, dev))) {
192 v3_rb_insert_color(&(dev->dev_tree_node), &(bus->devices));
194 allocate_dev_num(bus, dev->dev_num);
200 static struct pci_device * get_device(struct pci_bus * bus, uint8_t dev_num, uint8_t fn_num) {
201 struct rb_node * n = bus->devices.rb_node;
202 struct pci_device * dev = NULL;
203 uint8_t devfn = ((dev_num & 0x1f) << 3) | (fn_num & 0x7);
206 dev = rb_entry(n, struct pci_device, dev_tree_node);
208 if (devfn < dev->devfn) {
210 } else if (devfn > dev->devfn) {
226 static int addr_port_read(ushort_t port, void * dst, uint_t length, struct vm_device * dev) {
227 struct pci_internal * pci_state = (struct pci_internal *)dev->private_data;
228 int reg_offset = port & 0x3;
229 uint8_t * reg_addr = ((uint8_t *)&(pci_state->addr_reg.val)) + reg_offset;
231 PrintDebug("Reading PCI Address Port (%x): %x len=%d\n", port, pci_state->addr_reg.val, length);
234 if (reg_offset != 0) {
235 PrintError("Invalid Address Port Read\n");
238 *(uint32_t *)dst = *(uint32_t *)reg_addr;
239 } else if (length == 2) {
240 if (reg_offset > 2) {
241 PrintError("Invalid Address Port Read\n");
244 *(uint16_t *)dst = *(uint16_t *)reg_addr;
245 } else if (length == 1) {
246 *(uint8_t *)dst = *(uint8_t *)reg_addr;
248 PrintError("Invalid read length (%d) for PCI address register\n", length);
257 static int addr_port_write(ushort_t port, void * src, uint_t length, struct vm_device * dev) {
258 struct pci_internal * pci_state = (struct pci_internal *)dev->private_data;
259 int reg_offset = port & 0x3;
260 uint8_t * reg_addr = ((uint8_t *)&(pci_state->addr_reg.val)) + reg_offset;
264 if (reg_offset != 0) {
265 PrintError("Invalid Address Port Write\n");
269 PrintDebug("Writing PCI 4 bytes Val=%x\n", *(uint32_t *)src);
271 *(uint32_t *)reg_addr = *(uint32_t *)src;
272 } else if (length == 2) {
273 if (reg_offset > 2) {
274 PrintError("Invalid Address Port Write\n");
278 PrintDebug("Writing PCI 2 byte Val=%x\n", *(uint16_t *)src);
280 *(uint16_t *)reg_addr = *(uint16_t *)src;
281 } else if (length == 1) {
282 PrintDebug("Writing PCI 1 byte Val=%x\n", *(uint8_t *)src);
283 *(uint8_t *)reg_addr = *(uint8_t *)src;
285 PrintError("Invalid write length (%d) for PCI address register\n", length);
289 PrintDebug("Writing PCI Address Port(%x): %x\n", port, pci_state->addr_reg.val);
295 static int data_port_read(ushort_t port, void * dst, uint_t length, struct vm_device * vmdev) {
296 struct pci_internal * pci_state = (struct pci_internal *)(vmdev->private_data);
297 struct pci_device * pci_dev = NULL;
298 uint_t reg_num = (pci_state->addr_reg.reg_num << 2) + (port & 0x3);
301 if (pci_state->addr_reg.bus_num != 0) {
303 for (i = 0; i < length; i++) {
304 *((uint8_t *)dst + i) = 0xff;
310 PrintDebug("Reading PCI Data register. bus = %d, dev = %d, reg = %d (%x), cfg_reg = %x\n",
311 pci_state->addr_reg.bus_num,
312 pci_state->addr_reg.dev_num,
314 pci_state->addr_reg.val);
316 pci_dev = get_device(&(pci_state->bus_list[0]), pci_state->addr_reg.dev_num, pci_state->addr_reg.fn_num);
318 if (pci_dev == NULL) {
319 for (i = 0; i < length; i++) {
320 *(uint8_t *)((uint8_t *)dst + i) = 0xff;
326 if (pci_dev->type == PCI_PASSTHROUGH) {
327 if (pci_dev->config_read(reg_num, dst, length, pci_dev->priv_data) == -1) {
328 PrintError("Failed to handle configuration update for passthrough pci_device\n");
335 for (i = 0; i < length; i++) {
336 *(uint8_t *)((uint8_t *)dst + i) = pci_dev->config_space[reg_num + i];
339 PrintDebug("\tVal=%x, len=%d\n", *(uint32_t *)dst, length);
345 static inline int is_cfg_reg_writable(uchar_t header_type, int reg_num) {
346 if (header_type == 0x00) {
364 } else if (header_type == 0x80) {
383 // PCI to PCI Bridge = 0x01
384 // CardBus Bridge = 0x02
387 PrintError("Invalid PCI Header type (0x%.2x)\n", header_type);
394 static int bar_update(struct guest_info * info, struct pci_device * pci, int bar_num, uint32_t new_val) {
395 struct v3_pci_bar * bar = &(pci->bar[bar_num]);
397 PrintDebug("Updating BAR Register (Dev=%s) (bar=%d) (old_val=0x%x) (new_val=0x%x)\n",
398 pci->name, bar_num, bar->val, new_val);
404 PrintDebug("\tRehooking %d IO ports from base 0x%x to 0x%x for %d ports\n",
405 bar->num_ports, PCI_IO_BASE(bar->val), PCI_IO_BASE(new_val),
408 // only do this if pci device is enabled....
409 if (!(pci->config_header.status & 0x1)) {
410 PrintError("PCI Device IO space not enabled\n");
413 for (i = 0; i < bar->num_ports; i++) {
415 PrintDebug("Rehooking PCI IO port (old port=%u) (new port=%u)\n",
416 PCI_IO_BASE(bar->val) + i, PCI_IO_BASE(new_val) + i);
418 v3_unhook_io_port(info, PCI_IO_BASE(bar->val) + i);
420 if (v3_hook_io_port(info, PCI_IO_BASE(new_val) + i,
421 bar->io_read, bar->io_write,
422 bar->private_data) == -1) {
424 PrintError("Could not hook PCI IO port (old port=%u) (new port=%u)\n",
425 PCI_IO_BASE(bar->val) + i, PCI_IO_BASE(new_val) + i);
426 v3_print_io_map(info);
435 case PCI_BAR_MEM32: {
436 v3_unhook_mem(info, (addr_t)(bar->val));
439 v3_hook_full_mem(info, PCI_MEM32_BASE(new_val),
440 PCI_MEM32_BASE(new_val) + (bar->num_pages * PAGE_SIZE_4KB),
441 bar->mem_read, bar->mem_write, pci->priv_data);
443 PrintError("Write hooks not supported for PCI\n");
452 PrintDebug("Reprogramming an unsupported BAR register (Dev=%s) (bar=%d) (val=%x)\n",
453 pci->name, bar_num, new_val);
457 PrintError("Invalid Bar Reg updated (bar=%d)\n", bar_num);
465 static int data_port_write(ushort_t port, void * src, uint_t length, struct vm_device * vmdev) {
466 struct pci_internal * pci_state = (struct pci_internal *)vmdev->private_data;
467 struct pci_device * pci_dev = NULL;
468 uint_t reg_num = (pci_state->addr_reg.reg_num << 2) + (port & 0x3);
472 if (pci_state->addr_reg.bus_num != 0) {
476 PrintDebug("Writing PCI Data register. bus = %d, dev = %d, fn = %d, reg = %d (0x%x) addr_reg = 0x%x (val=0x%x, len=%d)\n",
477 pci_state->addr_reg.bus_num,
478 pci_state->addr_reg.dev_num,
479 pci_state->addr_reg.fn_num,
481 pci_state->addr_reg.val,
482 *(uint32_t *)src, length);
485 pci_dev = get_device(&(pci_state->bus_list[0]), pci_state->addr_reg.dev_num, pci_state->addr_reg.fn_num);
487 if (pci_dev == NULL) {
488 PrintError("Writing configuration space for non-present device (dev_num=%d)\n",
489 pci_state->addr_reg.dev_num);
493 if (pci_dev->type == PCI_PASSTHROUGH) {
494 if (pci_dev->config_write(reg_num, src, length, pci_dev->priv_data) == -1) {
495 PrintError("Failed to handle configuration update for passthrough pci_device\n");
503 for (i = 0; i < length; i++) {
504 uint_t cur_reg = reg_num + i;
505 int writable = is_cfg_reg_writable(pci_dev->config_header.header_type, cur_reg);
507 if (writable == -1) {
508 PrintError("Invalid PCI configuration space\n");
513 pci_dev->config_space[cur_reg] = *(uint8_t *)((uint8_t *)src + i);
515 if ((cur_reg >= 0x10) && (cur_reg < 0x28)) {
516 // BAR Register Update
517 int bar_reg = ((cur_reg & ~0x3) - 0x10) / 4;
519 pci_dev->bar_update_flag = 1;
520 pci_dev->bar[bar_reg].updated = 1;
522 // PrintDebug("Updating BAR register %d\n", bar_reg);
524 } else if ((cur_reg >= 0x30) && (cur_reg < 0x34)) {
525 // Extension ROM update
527 pci_dev->ext_rom_update_flag = 1;
528 } else if (cur_reg == 0x04) {
530 uint8_t command = *((uint8_t *)src + i);
532 PrintError("command update for %s old=%x new=%x\n",
534 pci_dev->config_space[cur_reg],command);
536 pci_dev->config_space[cur_reg] = command;
538 if (pci_dev->cmd_update) {
539 pci_dev->cmd_update(pci_dev, (command & 0x01), (command & 0x02));
542 } else if (cur_reg == 0x0f) {
544 pci_dev->config_header.BIST = 0x00;
547 PrintError("PCI Write to read only register %d\n", cur_reg);
551 if (pci_dev->config_update) {
552 pci_dev->config_update(reg_num, src, length, pci_dev->priv_data);
555 // Scan for BAR updated
556 if (pci_dev->bar_update_flag) {
557 for (i = 0; i < 6; i++) {
558 if (pci_dev->bar[i].updated) {
559 int bar_offset = 0x10 + 4 * i;
562 if (pci_dev->bar[i].type == PCI_BAR_PASSTHROUGH) {
563 if (pci_dev->bar[i].bar_write(i, (uint32_t *)(pci_dev->config_space + bar_offset), pci_dev->bar[i].private_data) == -1) {
564 PrintError("Error in passthrough bar write operation\n");
569 *(uint32_t *)(pci_dev->config_space + bar_offset) &= pci_dev->bar[i].mask;
570 // check special flags....
573 if (bar_update(vmdev->vm, pci_dev, i, *(uint32_t *)(pci_dev->config_space + bar_offset)) == -1) {
574 PrintError("PCI Device %s: Bar update Error Bar=%d\n", pci_dev->name, i);
579 pci_dev->bar[i].updated = 0;
582 pci_dev->bar_update_flag = 0;
585 if ((pci_dev->ext_rom_update_flag) && (pci_dev->ext_rom_update)) {
586 pci_dev->ext_rom_update(pci_dev);
587 pci_dev->ext_rom_update_flag = 0;
596 static int pci_reset_device(struct vm_device * dev) {
597 PrintDebug("pci: reset device\n");
602 static int pci_start_device(struct vm_device * dev) {
603 PrintDebug("pci: start device\n");
608 static int pci_stop_device(struct vm_device * dev) {
609 PrintDebug("pci: stop device\n");
615 static int pci_free(struct vm_device * dev) {
618 for (i = 0; i < 4; i++){
619 v3_dev_unhook_io(dev, CONFIG_ADDR_PORT + i);
620 v3_dev_unhook_io(dev, CONFIG_DATA_PORT + i);
628 static void init_pci_busses(struct pci_internal * pci_state) {
631 for (i = 0; i < PCI_BUS_COUNT; i++) {
632 pci_state->bus_list[i].bus_num = i;
633 pci_state->bus_list[i].devices.rb_node = NULL;
634 memset(pci_state->bus_list[i].dev_map, 0, sizeof(pci_state->bus_list[i].dev_map));
641 static struct v3_device_ops dev_ops = {
643 .reset = pci_reset_device,
644 .start = pci_start_device,
645 .stop = pci_stop_device,
651 static int pci_init(struct guest_info * vm, void * cfg_data) {
652 struct pci_internal * pci_state = V3_Malloc(sizeof(struct pci_internal));
655 PrintDebug("PCI internal at %p\n",(void *)pci_state);
657 struct vm_device * dev = v3_allocate_device("PCI", &dev_ops, pci_state);
659 if (v3_attach_device(vm, dev) == -1) {
660 PrintError("Could not attach device %s\n", "PCI");
665 pci_state->addr_reg.val = 0;
666 pci_state->dev_io_base = PCI_DEV_IO_PORT_BASE;
668 init_pci_busses(pci_state);
670 PrintDebug("Sizeof config header=%d\n", (int)sizeof(struct pci_config_header));
672 for (i = 0; i < 4; i++) {
673 v3_dev_hook_io(dev, CONFIG_ADDR_PORT + i, &addr_port_read, &addr_port_write);
674 v3_dev_hook_io(dev, CONFIG_DATA_PORT + i, &data_port_read, &data_port_write);
681 device_register("PCI", pci_init)
684 static inline int init_bars(struct guest_info * info, struct pci_device * pci_dev) {
687 for (i = 0; i < 6; i++) {
688 int bar_offset = 0x10 + (4 * i);
690 if (pci_dev->bar[i].type == PCI_BAR_IO) {
692 pci_dev->bar[i].mask = (~((pci_dev->bar[i].num_ports) - 1)) | 0x01;
694 if (pci_dev->bar[i].default_base_port != 0xffff) {
695 pci_dev->bar[i].val = pci_dev->bar[i].default_base_port & pci_dev->bar[i].mask;
697 pci_dev->bar[i].val = 0;
700 pci_dev->bar[i].val |= 0x00000001;
702 for (j = 0; j < pci_dev->bar[i].num_ports; j++) {
704 if (pci_dev->bar[i].default_base_port != 0xffff) {
705 if (v3_hook_io_port(info, pci_dev->bar[i].default_base_port + j,
706 pci_dev->bar[i].io_read, pci_dev->bar[i].io_write,
707 pci_dev->bar[i].private_data) == -1) {
708 PrintError("Could not hook default io port %x\n", pci_dev->bar[i].default_base_port + j);
714 *(uint32_t *)(pci_dev->config_space + bar_offset) = pci_dev->bar[i].val;
716 } else if (pci_dev->bar[i].type == PCI_BAR_MEM32) {
717 pci_dev->bar[i].mask = ~((pci_dev->bar[i].num_pages << 12) - 1);
718 pci_dev->bar[i].mask |= 0xf; // preserve the configuration flags
720 if (pci_dev->bar[i].default_base_addr != 0xffffffff) {
721 pci_dev->bar[i].val = pci_dev->bar[i].default_base_addr & pci_dev->bar[i].mask;
723 pci_dev->bar[i].val = 0;
727 if (pci_dev->bar[i].mem_read) {
729 v3_hook_full_mem(info, pci_dev->bar[i].default_base_addr,
730 pci_dev->bar[i].default_base_addr + (pci_dev->bar[i].num_pages * PAGE_SIZE_4KB),
731 pci_dev->bar[i].mem_read, pci_dev->bar[i].mem_write, pci_dev->priv_data);
732 } else if (pci_dev->bar[i].mem_write) {
734 PrintError("Write hooks not supported for PCI devices\n");
737 v3_hook_write_mem(pci_dev->vm_dev->vm, pci_dev->bar[i].default_base_addr,
738 pci_dev->bar[i].default_base_addr + (pci_dev->bar[i].num_pages * PAGE_SIZE_4KB),
739 pci_dev->bar[i].mem_write, pci_dev->vm_dev);
742 // set the prefetchable flag...
743 pci_dev->bar[i].val |= 0x00000008;
747 *(uint32_t *)(pci_dev->config_space + bar_offset) = pci_dev->bar[i].val;
749 } else if (pci_dev->bar[i].type == PCI_BAR_MEM24) {
750 PrintError("16 Bit memory ranges not supported (reg: %d)\n", i);
752 } else if (pci_dev->bar[i].type == PCI_BAR_NONE) {
753 pci_dev->bar[i].val = 0x00000000;
754 pci_dev->bar[i].mask = 0x00000000; // This ensures that all updates will be dropped
755 *(uint32_t *)(pci_dev->config_space + bar_offset) = pci_dev->bar[i].val;
756 } else if (pci_dev->bar[i].type == PCI_BAR_PASSTHROUGH) {
758 // Call the bar init function to get the local cached value
759 pci_dev->bar[i].bar_init(i, &(pci_dev->bar[i].val), pci_dev->bar[i].private_data);
762 PrintError("Invalid BAR type for bar #%d\n", i);
771 int v3_pci_set_irq_bridge(struct vm_device * pci_bus, int bus_num,
772 int (*raise_pci_irq)(struct vm_device * dev, struct pci_device * pci_dev),
773 int (*lower_pci_irq)(struct vm_device * dev, struct pci_device * pci_dev),
774 struct vm_device * bridge_dev) {
775 struct pci_internal * pci_state = (struct pci_internal *)pci_bus->private_data;
778 pci_state->bus_list[bus_num].raise_pci_irq = raise_pci_irq;
779 pci_state->bus_list[bus_num].lower_pci_irq = lower_pci_irq;
780 pci_state->bus_list[bus_num].irq_bridge_dev = bridge_dev;
785 int v3_pci_raise_irq(struct vm_device * pci_bus, int bus_num, struct pci_device * dev) {
786 struct pci_internal * pci_state = (struct pci_internal *)pci_bus->private_data;
787 struct pci_bus * bus = &(pci_state->bus_list[bus_num]);
789 return bus->raise_pci_irq(bus->irq_bridge_dev, dev);
792 int v3_pci_lower_irq(struct vm_device * pci_bus, int bus_num, struct pci_device * dev) {
793 struct pci_internal * pci_state = (struct pci_internal *)pci_bus->private_data;
794 struct pci_bus * bus = &(pci_state->bus_list[bus_num]);
796 return bus->lower_pci_irq(bus->irq_bridge_dev, dev);
799 // if dev_num == -1, auto assign
800 struct pci_device * v3_pci_register_device(struct vm_device * pci,
801 pci_device_type_t dev_type,
806 struct v3_pci_bar * bars,
807 int (*config_update)(uint_t reg_num, void * src, uint_t length, void * priv_data),
808 int (*cmd_update)(struct pci_device *pci_dev, uchar_t io_enabled, uchar_t mem_enabled),
809 int (*ext_rom_update)(struct pci_device * pci_dev),
812 struct pci_internal * pci_state = (struct pci_internal *)pci->private_data;
813 struct pci_bus * bus = &(pci_state->bus_list[bus_num]);
814 struct pci_device * pci_dev = NULL;
817 if (dev_num > MAX_BUS_DEVICES) {
818 PrintError("Requested Invalid device number (%d)\n", dev_num);
822 if (dev_num == PCI_AUTO_DEV_NUM) {
823 PrintDebug("Searching for free device number\n");
824 if ((dev_num = get_free_dev_num(bus)) == -1) {
825 PrintError("No more available PCI slots on bus %d\n", bus->bus_num);
830 PrintDebug("Checking for PCI Device\n");
832 if (get_device(bus, dev_num, fn_num) != NULL) {
833 PrintError("PCI Device already registered at slot %d on bus %d\n",
834 dev_num, bus->bus_num);
839 pci_dev = (struct pci_device *)V3_Malloc(sizeof(struct pci_device));
841 if (pci_dev == NULL) {
842 PrintError("Could not allocate pci device\n");
846 memset(pci_dev, 0, sizeof(struct pci_device));
849 pci_dev->type = dev_type;
851 switch (pci_dev->type) {
853 pci_dev->config_header.header_type = 0x00;
855 case PCI_MULTIFUNCTION:
856 pci_dev->config_header.header_type = 0x80;
859 PrintError("Unhandled PCI Device Type: %d\n", dev_type);
865 pci_dev->bus_num = bus_num;
866 pci_dev->dev_num = dev_num;
867 pci_dev->fn_num = fn_num;
869 strncpy(pci_dev->name, name, sizeof(pci_dev->name));
870 pci_dev->priv_data = priv_data;
872 // register update callbacks
873 pci_dev->config_update = config_update;
874 pci_dev->cmd_update = cmd_update;
875 pci_dev->ext_rom_update = ext_rom_update;
879 for (i = 0; i < 6; i ++) {
880 pci_dev->bar[i].type = bars[i].type;
881 pci_dev->bar[i].private_data = bars[i].private_data;
883 if (pci_dev->bar[i].type == PCI_BAR_IO) {
884 pci_dev->bar[i].num_ports = bars[i].num_ports;
886 // This is a horrible HACK becaues the BIOS is supposed to set the PCI base ports
887 // And if the BIOS doesn't, Linux just happily overlaps device port assignments
888 if (bars[i].default_base_port != (uint16_t)-1) {
889 pci_dev->bar[i].default_base_port = bars[i].default_base_port;
891 pci_dev->bar[i].default_base_port = pci_state->dev_io_base;
892 pci_state->dev_io_base += ( 0x100 * ((bars[i].num_ports / 0x100) + 1) );
895 pci_dev->bar[i].io_read = bars[i].io_read;
896 pci_dev->bar[i].io_write = bars[i].io_write;
897 } else if (pci_dev->bar[i].type == PCI_BAR_MEM32) {
898 pci_dev->bar[i].num_pages = bars[i].num_pages;
899 pci_dev->bar[i].default_base_addr = bars[i].default_base_addr;
900 pci_dev->bar[i].mem_read = bars[i].mem_read;
901 pci_dev->bar[i].mem_write = bars[i].mem_write;
902 } else if (pci_dev->bar[i].type == PCI_BAR_PASSTHROUGH) {
903 pci_dev->bar[i].bar_init = bars[i].bar_init;
904 pci_dev->bar[i].bar_write = bars[i].bar_write;
906 pci_dev->bar[i].num_pages = 0;
907 pci_dev->bar[i].default_base_addr = 0;
908 pci_dev->bar[i].mem_read = NULL;
909 pci_dev->bar[i].mem_write = NULL;
913 if (init_bars(pci->vm, pci_dev) == -1) {
914 PrintError("could not initialize bar registers\n");
919 add_device_to_bus(bus, pci_dev);
921 #ifdef CONFIG_DEBUG_PCI
922 pci_dump_state(pci_state);
930 // if dev_num == -1, auto assign
931 struct pci_device * v3_pci_register_passthrough_device(struct vm_device * pci,
936 int (*config_write)(uint_t reg_num, void * src, uint_t length, void * private_data),
937 int (*config_read)(uint_t reg_num, void * dst, uint_t length, void * private_data),
938 void * private_data) {
940 struct pci_internal * pci_state = (struct pci_internal *)pci->private_data;
941 struct pci_bus * bus = &(pci_state->bus_list[bus_num]);
942 struct pci_device * pci_dev = NULL;
944 if (dev_num > MAX_BUS_DEVICES) {
945 PrintError("Requested Invalid device number (%d)\n", dev_num);
949 if (dev_num == PCI_AUTO_DEV_NUM) {
950 PrintDebug("Searching for free device number\n");
951 if ((dev_num = get_free_dev_num(bus)) == -1) {
952 PrintError("No more available PCI slots on bus %d\n", bus->bus_num);
957 PrintDebug("Checking for PCI Device\n");
959 if (get_device(bus, dev_num, fn_num) != NULL) {
960 PrintError("PCI Device already registered at slot %d on bus %d\n",
961 dev_num, bus->bus_num);
966 pci_dev = (struct pci_device *)V3_Malloc(sizeof(struct pci_device));
968 if (pci_dev == NULL) {
969 PrintError("Could not allocate pci device\n");
973 memset(pci_dev, 0, sizeof(struct pci_device));
975 pci_dev->bus_num = bus_num;
976 pci_dev->dev_num = dev_num;
977 pci_dev->fn_num = fn_num;
979 strncpy(pci_dev->name, name, sizeof(pci_dev->name));
980 pci_dev->priv_data = private_data;
982 // register update callbacks
983 pci_dev->config_write = config_write;
984 pci_dev->config_read = config_read;
987 add_device_to_bus(bus, pci_dev);
989 #ifdef CONFIG_DEBUG_PCI
990 pci_dump_state(pci_state);