2 * This file is part of the Palacios Virtual Machine Monitor developed
3 * by the V3VEE Project with funding from the United States National
4 * Science Foundation and the Department of Energy.
6 * The V3VEE Project is a joint project between Northwestern University
7 * and the University of New Mexico. You can find out more at
10 * Copyright (c) 2008, Jack Lange <jarusl@cs.northwestern.edu>
11 * Copyright (c) 2008, The V3VEE Project <http://www.v3vee.org>
12 * All rights reserved.
14 * Author: Jack Lange <jarusl@cs.northwestern.edu>
16 * This is free software. You are permitted to use,
17 * redistribute, and modify it as specified in the file "V3VEE_LICENSE".
20 #include <palacios/vmm.h>
21 #include <palacios/vm_guest_mem.h>
22 #include <devices/ide.h>
23 #include <devices/pci.h>
24 #include "ide-types.h"
25 #include "atapi-types.h"
27 #define PRI_DEFAULT_IRQ 14
28 #define SEC_DEFAULT_IRQ 15
31 #define PRI_DATA_PORT 0x1f0
32 #define PRI_FEATURES_PORT 0x1f1
33 #define PRI_SECT_CNT_PORT 0x1f2
34 #define PRI_SECT_NUM_PORT 0x1f3
35 #define PRI_CYL_LOW_PORT 0x1f4
36 #define PRI_CYL_HIGH_PORT 0x1f5
37 #define PRI_DRV_SEL_PORT 0x1f6
38 #define PRI_CMD_PORT 0x1f7
39 #define PRI_CTRL_PORT 0x3f6
40 #define PRI_ADDR_REG_PORT 0x3f7
42 #define SEC_DATA_PORT 0x170
43 #define SEC_FEATURES_PORT 0x171
44 #define SEC_SECT_CNT_PORT 0x172
45 #define SEC_SECT_NUM_PORT 0x173
46 #define SEC_CYL_LOW_PORT 0x174
47 #define SEC_CYL_HIGH_PORT 0x175
48 #define SEC_DRV_SEL_PORT 0x176
49 #define SEC_CMD_PORT 0x177
50 #define SEC_CTRL_PORT 0x376
51 #define SEC_ADDR_REG_PORT 0x377
54 #define PRI_DEFAULT_DMA_PORT 0xc000
55 #define SEC_DEFAULT_DMA_PORT 0xc008
57 #define DATA_BUFFER_SIZE 2048
59 static const char * ide_pri_port_strs[] = {"PRI_DATA", "PRI_FEATURES", "PRI_SECT_CNT", "PRI_SECT_NUM",
60 "PRI_CYL_LOW", "PRI_CYL_HIGH", "PRI_DRV_SEL", "PRI_CMD",
61 "PRI_CTRL", "PRI_ADDR_REG"};
64 static const char * ide_sec_port_strs[] = {"SEC_DATA", "SEC_FEATURES", "SEC_SECT_CNT", "SEC_SECT_NUM",
65 "SEC_CYL_LOW", "SEC_CYL_HIGH", "SEC_DRV_SEL", "SEC_CMD",
66 "SEC_CTRL", "SEC_ADDR_REG"};
68 static const char * ide_dma_port_strs[] = {"DMA_CMD", NULL, "DMA_STATUS", NULL,
69 "DMA_PRD0", "DMA_PRD1", "DMA_PRD2", "DMA_PRD3"};
73 static inline const char * io_port_to_str(uint16_t port) {
74 if ((port >= PRI_DATA_PORT) && (port <= PRI_CMD_PORT)) {
75 return ide_pri_port_strs[port - PRI_DATA_PORT];
76 } else if ((port >= SEC_DATA_PORT) && (port <= SEC_CMD_PORT)) {
77 return ide_sec_port_strs[port - SEC_DATA_PORT];
78 } else if ((port == PRI_CTRL_PORT) || (port == PRI_ADDR_REG_PORT)) {
79 return ide_pri_port_strs[port - PRI_CTRL_PORT + 8];
80 } else if ((port == SEC_CTRL_PORT) || (port == SEC_ADDR_REG_PORT)) {
81 return ide_sec_port_strs[port - SEC_CTRL_PORT + 8];
87 static inline const char * dma_port_to_str(uint16_t port) {
88 return ide_dma_port_strs[port & 0x7];
92 static const char * ide_dev_type_strs[] = {"NONE", "HARDDISK", "CDROM" };
95 static inline const char * device_type_to_str(v3_ide_dev_type_t type) {
100 return ide_dev_type_strs[type];
105 struct ide_cd_state {
106 struct atapi_sense_data sense;
109 struct atapi_error_recovery err_recovery;
112 struct ide_hd_state {
115 /* this is the multiple sector transfer size as configured for read/write multiple sectors*/
116 uint_t mult_sector_num;
118 /* This is the current op sector size:
119 * for multiple sector ops this equals mult_sector_num
120 * for standard ops this equals 1
122 uint_t cur_sector_num;
128 v3_ide_dev_type_t drive_type;
131 struct v3_ide_cd_ops * cd_ops;
132 struct v3_ide_hd_ops * hd_ops;
137 struct ide_cd_state cd_state;
138 struct ide_hd_state hd_state;
143 // Where we are in the data transfer
144 uint_t transfer_index;
146 // the length of a transfer
147 // calculated for easy access
148 uint_t transfer_length;
150 uint64_t current_lba;
152 // We have a local data buffer that we use for IO port accesses
153 uint8_t data_buf[DATA_BUFFER_SIZE];
159 uint8_t sector_count; // 0x1f2,0x172
160 struct atapi_irq_flags irq_flags;
161 } __attribute__((packed));
164 uint8_t sector_num; // 0x1f3,0x173
166 } __attribute__((packed));
173 uint8_t cylinder_low; // 0x1f4,0x174
174 uint8_t cylinder_high; // 0x1f5,0x175
175 } __attribute__((packed));
180 } __attribute__((packed));
183 // The transfer length requested by the CPU
185 } __attribute__((packed));
192 struct ide_drive drives[2];
195 struct ide_error_reg error_reg; // [read] 0x1f1,0x171
197 struct ide_features_reg features;
199 struct ide_drive_head_reg drive_head; // 0x1f6,0x176
201 struct ide_status_reg status; // [read] 0x1f7,0x177
202 uint8_t cmd_reg; // [write] 0x1f7,0x177
204 int irq; // this is temporary until we add PCI support
206 struct pci_device * pci_dev;
209 struct ide_ctrl_reg ctrl_reg; // [write] 0x3f6,0x376
211 struct ide_dma_cmd_reg dma_cmd;
212 struct ide_dma_status_reg dma_status;
213 uint32_t dma_prd_addr;
214 uint_t dma_tbl_index;
219 struct ide_internal {
220 struct ide_channel channels[2];
221 struct vm_device * pci;
222 struct pci_device * busmaster_pci;
229 /* Utility functions */
231 static inline uint16_t be_to_le_16(const uint16_t val) {
232 uint8_t * buf = (uint8_t *)&val;
233 return (buf[0] << 8) | (buf[1]) ;
236 static inline uint16_t le_to_be_16(const uint16_t val) {
237 return be_to_le_16(val);
241 static inline uint32_t be_to_le_32(const uint32_t val) {
242 uint8_t * buf = (uint8_t *)&val;
243 return (buf[0] << 24) | (buf[1] << 16) | (buf[2] << 8) | buf[3];
246 static inline uint32_t le_to_be_32(const uint32_t val) {
247 return be_to_le_32(val);
251 static inline int get_channel_index(ushort_t port) {
252 if (((port & 0xfff8) == 0x1f0) ||
253 ((port & 0xfffe) == 0x3f6) ||
254 ((port & 0xfff8) == 0xc000)) {
256 } else if (((port & 0xfff8) == 0x170) ||
257 ((port & 0xfffe) == 0x376) ||
258 ((port & 0xfff8) == 0xc008)) {
265 static inline struct ide_channel * get_selected_channel(struct ide_internal * ide, ushort_t port) {
266 int channel_idx = get_channel_index(port);
267 return &(ide->channels[channel_idx]);
270 static inline struct ide_drive * get_selected_drive(struct ide_channel * channel) {
271 return &(channel->drives[channel->drive_head.drive_sel]);
275 static inline int is_lba_enabled(struct ide_channel * channel) {
276 return channel->drive_head.lba_mode;
281 static void ide_raise_irq(struct vm_device * dev, struct ide_channel * channel) {
282 if (channel->ctrl_reg.irq_disable == 0) {
283 PrintDebug("Raising IDE Interrupt %d\n", channel->irq);
284 channel->dma_status.int_gen = 1;
285 v3_raise_irq(dev->vm, channel->irq);
290 static void drive_reset(struct ide_drive * drive) {
291 drive->sector_count = 0x01;
292 drive->sector_num = 0x01;
294 PrintDebug("Resetting drive %s\n", drive->model);
296 if (drive->drive_type == IDE_CDROM) {
297 drive->cylinder = 0xeb14;
299 drive->cylinder = 0x0000;
300 //drive->hd_state.accessed = 0;
304 memset(drive->data_buf, 0, sizeof(drive->data_buf));
305 drive->transfer_index = 0;
307 // Send the reset signal to the connected device callbacks
308 // channel->drives[0].reset();
309 // channel->drives[1].reset();
312 static void channel_reset(struct ide_channel * channel) {
314 // set busy and seek complete flags
315 channel->status.val = 0x90;
318 channel->error_reg.val = 0x01;
321 channel->cmd_reg = 0x00;
323 channel->ctrl_reg.irq_disable = 0;
326 static void channel_reset_complete(struct ide_channel * channel) {
327 channel->status.busy = 0;
328 channel->status.ready = 1;
330 channel->drive_head.head_num = 0;
332 drive_reset(&(channel->drives[0]));
333 drive_reset(&(channel->drives[1]));
337 static void ide_abort_command(struct vm_device * dev, struct ide_channel * channel) {
338 channel->status.val = 0x41; // Error + ready
339 channel->error_reg.val = 0x04; // No idea...
341 ide_raise_irq(dev, channel);
349 /* ATAPI functions */
358 static int dma_read(struct vm_device * dev, struct ide_channel * channel) {
359 struct ide_drive * drive = get_selected_drive(channel);
360 struct ide_dma_prd prd_entry;
361 uint32_t prd_entry_addr = channel->dma_prd_addr + (sizeof(struct ide_dma_prd) * channel->dma_tbl_index);
364 PrintDebug("PRD table address = %x\n", channel->dma_prd_addr);
366 ret = read_guest_pa_memory(dev->vm, prd_entry_addr, sizeof(struct ide_dma_prd), (void *)&prd_entry);
368 if (ret != sizeof(struct ide_dma_prd)) {
369 PrintError("Could not read PRD\n");
373 PrintDebug("PRD Addr: %x, PDR Len: %d, EOT: %d\n", prd_entry.base_addr, prd_entry.size, prd_entry.end_of_table);
375 ret = write_guest_pa_memory(dev->vm, prd_entry.base_addr, prd_entry.size, drive->data_buf);
377 if (ret != prd_entry.size) {
378 PrintError("Failed to copy data into guest memory... (ret=%d)\n", ret);
385 drive->irq_flags.io_dir = 1;
386 drive->irq_flags.c_d = 1;
387 drive->irq_flags.rel = 0;
393 if (prd_entry.end_of_table) {
394 channel->dma_status.active = 0;
395 channel->dma_status.err = 0;
396 channel->dma_status.int_gen = 1;
398 channel->status.busy = 0;
399 channel->status.ready = 1;
400 channel->status.data_req = 0;
401 channel->status.error = 0;
402 channel->status.seek_complete = 1;
405 ide_raise_irq(dev, channel);
411 static int dma_write(struct vm_device * dev, struct ide_channel * channel) {
413 PrintError("DMA writes currently not supported\n");
419 * This is an ugly ugly ugly way to differentiate between the first and second DMA channels
422 static int write_dma_port(ushort_t port_offset, void * src, uint_t length, struct vm_device * dev, struct ide_channel * channel);
423 static int read_dma_port(ushort_t port_offset, void * dst, uint_t length, struct vm_device * dev, struct ide_channel * channel);
426 static int write_pri_dma_port(ushort_t port, void * src, uint_t length, struct vm_device * dev) {
427 struct ide_internal * ide = (struct ide_internal *)(dev->private_data);
428 PrintDebug("IDE: Writing PRI DMA Port %x (%s) (val=%x)\n", port, dma_port_to_str(port & 0x7), *(uint32_t *)src);
429 return write_dma_port(port & 0x7, src, length, dev, &(ide->channels[0]));
432 static int write_sec_dma_port(ushort_t port, void * src, uint_t length, struct vm_device * dev) {
433 struct ide_internal * ide = (struct ide_internal *)(dev->private_data);
434 PrintDebug("IDE: Writing SEC DMA Port %x (%s) (val=%x)\n", port, dma_port_to_str(port & 0x7), *(uint32_t *)src);
435 return write_dma_port(port & 0x7, src, length, dev, &(ide->channels[1]));
439 static int read_pri_dma_port(ushort_t port, void * dst, uint_t length, struct vm_device * dev) {
440 struct ide_internal * ide = (struct ide_internal *)(dev->private_data);
441 PrintDebug("IDE: Reading PRI DMA Port %x (%s)\n", port, dma_port_to_str(port & 0x7));
442 return read_dma_port(port & 0x7, dst, length, dev, &(ide->channels[0]));
445 static int read_sec_dma_port(ushort_t port, void * dst, uint_t length, struct vm_device * dev) {
446 struct ide_internal * ide = (struct ide_internal *)(dev->private_data);
447 PrintDebug("IDE: Reading SEC DMA Port %x (%s)\n", port, dma_port_to_str(port & 0x7));
448 return read_dma_port(port & 0x7, dst, length, dev, &(ide->channels[1]));
452 #define DMA_CMD_PORT 0x00
453 #define DMA_STATUS_PORT 0x02
454 #define DMA_PRD_PORT0 0x04
455 #define DMA_PRD_PORT1 0x05
456 #define DMA_PRD_PORT2 0x06
457 #define DMA_PRD_PORT3 0x07
460 static int write_dma_port(ushort_t port_offset, void * src, uint_t length,
461 struct vm_device * dev, struct ide_channel * channel) {
463 switch (port_offset) {
465 channel->dma_cmd.val = *(uint8_t *)src;
467 if (channel->dma_cmd.start == 0) {
468 channel->dma_tbl_index = 0;
470 channel->dma_status.active = 1;
472 if (channel->dma_cmd.read == 1) {
474 if (dma_read(dev, channel) == -1) {
475 PrintError("Failed DMA Read\n");
480 if (dma_write(dev, channel) == -1) {
481 PrintError("Failed DMA Write\n");
486 channel->dma_cmd.val &= 0x09;
491 case DMA_STATUS_PORT:
493 PrintError("Invalid read length for DMA status port\n");
497 channel->dma_status.val = *(uint8_t *)src;
503 case DMA_PRD_PORT3: {
504 uint_t addr_index = port_offset & 0x3;
505 uint8_t * addr_buf = (uint8_t *)&(channel->dma_prd_addr);
508 if (addr_index + length > 4) {
509 PrintError("DMA Port space overrun port=%x len=%d\n", port_offset, length);
513 for (i = 0; i < length; i++) {
514 addr_buf[addr_index + i] = *((uint8_t *)src + i);
517 PrintDebug("Writing PRD Port %x (val=%x)\n", port_offset, channel->dma_prd_addr);
522 PrintError("IDE: Invalid DMA Port (%s)\n", dma_port_to_str(port_offset));
530 static int read_dma_port(ushort_t port_offset, void * dst, uint_t length,
531 struct vm_device * dev, struct ide_channel * channel) {
533 switch (port_offset) {
535 *(uint8_t *)dst = channel->dma_cmd.val;
538 case DMA_STATUS_PORT:
540 PrintError("Invalid read length for DMA status port\n");
544 *(uint8_t *)dst = channel->dma_status.val;
550 case DMA_PRD_PORT3: {
551 uint_t addr_index = port_offset & 0x3;
552 uint8_t * addr_buf = (uint8_t *)&(channel->dma_prd_addr);
555 if (addr_index + length > 4) {
556 PrintError("DMA Port space overrun port=%x len=%d\n", port_offset, length);
560 for (i = 0; i < length; i++) {
561 *((uint8_t *)dst + i) = addr_buf[addr_index + i];
567 PrintError("IDE: Invalid DMA Port (%s)\n", dma_port_to_str(port_offset));
571 PrintDebug("\tval=%x\n", *(uint32_t *)dst);
578 static int write_cmd_port(ushort_t port, void * src, uint_t length, struct vm_device * dev) {
579 struct ide_internal * ide = (struct ide_internal *)(dev->private_data);
580 struct ide_channel * channel = get_selected_channel(ide, port);
581 struct ide_drive * drive = get_selected_drive(channel);
584 PrintError("Invalid Write Length on IDE command Port %x\n", port);
588 PrintDebug("IDE: Writing Command Port %x (%s) (val=%x)\n", port, io_port_to_str(port), *(uint8_t *)src);
590 channel->cmd_reg = *(uint8_t *)src;
592 switch (channel->cmd_reg) {
594 case 0xa1: // ATAPI Identify Device Packet
595 if (drive->drive_type != IDE_CDROM) {
598 // JRL: Should we abort here?
599 ide_abort_command(dev, channel);
602 atapi_identify_device(drive);
604 channel->error_reg.val = 0;
605 channel->status.val = 0x58; // ready, data_req, seek_complete
607 ide_raise_irq(dev, channel);
610 case 0xec: // Identify Device
611 if (drive->drive_type != IDE_DISK) {
614 // JRL: Should we abort here?
615 ide_abort_command(dev, channel);
617 ata_identify_device(drive);
619 channel->error_reg.val = 0;
620 channel->status.val = 0x58;
622 ide_raise_irq(dev, channel);
626 case 0xa0: // ATAPI Command Packet
627 if (drive->drive_type != IDE_CDROM) {
628 ide_abort_command(dev, channel);
631 drive->sector_count = 1;
633 channel->status.busy = 0;
634 channel->status.write_fault = 0;
635 channel->status.data_req = 1;
636 channel->status.error = 0;
638 // reset the data buffer...
639 drive->transfer_length = ATAPI_PACKET_SIZE;
640 drive->transfer_index = 0;
644 case 0x20: // Read Sectors with Retry
645 case 0x21: // Read Sectors without Retry
646 drive->hd_state.cur_sector_num = 1;
648 if (ata_read_sectors(dev, channel) == -1) {
649 PrintError("Error reading sectors\n");
654 case 0x24: // Read Sectors Extended
655 drive->hd_state.cur_sector_num = 1;
657 if (ata_read_sectors_ext(dev, channel) == -1) {
658 PrintError("Error reading extended sectors\n");
663 case 0xc8: // Read DMA with retry
664 case 0xc9: // Read DMA
665 drive->hd_state.cur_sector_num = 1;
668 case 0xef: // Set Features
669 // Prior to this the features register has been written to.
670 // This command tells the drive to check if the new value is supported (the value is drive specific)
671 // Common is that bit0=DMA enable
672 // If valid the drive raises an interrupt, if not it aborts.
674 // Do some checking here...
676 channel->status.busy = 0;
677 channel->status.write_fault = 0;
678 channel->status.error = 0;
679 channel->status.ready = 1;
680 channel->status.seek_complete = 1;
682 ide_raise_irq(dev, channel);
685 case 0x91: // Initialize Drive Parameters
686 case 0x10: // recalibrate?
687 channel->status.error = 0;
688 channel->status.ready = 1;
689 channel->status.seek_complete = 1;
690 ide_raise_irq(dev, channel);
692 case 0xc6: { // Set multiple mode (IDE Block mode)
693 // This makes the drive transfer multiple sectors before generating an interrupt
694 uint32_t tmp_sect_num = drive->sector_num; // GCC SUCKS
696 if (tmp_sect_num > MAX_MULT_SECTORS) {
697 ide_abort_command(dev, channel);
701 if (drive->sector_count == 0) {
702 drive->hd_state.mult_sector_num= 1;
704 drive->hd_state.mult_sector_num = drive->sector_count;
707 channel->status.ready = 1;
708 channel->status.error = 0;
710 ide_raise_irq(dev, channel);
714 case 0xc4: // read multiple sectors
715 drive->hd_state.cur_sector_num = drive->hd_state.mult_sector_num;
717 PrintError("Unimplemented IDE command (%x)\n", channel->cmd_reg);
725 static int write_data_port(ushort_t port, void * src, uint_t length, struct vm_device * dev) {
726 struct ide_internal * ide = (struct ide_internal *)(dev->private_data);
727 struct ide_channel * channel = get_selected_channel(ide, port);
728 struct ide_drive * drive = get_selected_drive(channel);
730 // PrintDebug("IDE: Writing Data Port %x (val=%x, len=%d)\n",
731 // port, *(uint32_t *)src, length);
733 memcpy(drive->data_buf + drive->transfer_index, src, length);
734 drive->transfer_index += length;
736 // Transfer is complete, dispatch the command
737 if (drive->transfer_index >= drive->transfer_length) {
738 switch (channel->cmd_reg) {
739 case 0x30: // Write Sectors
740 PrintError("Writing Data not yet implemented\n");
743 case 0xa0: // ATAPI packet command
744 if (atapi_handle_packet(dev, channel) == -1) {
745 PrintError("Error handling ATAPI packet\n");
750 PrintError("Unhandld IDE Command %x\n", channel->cmd_reg);
759 static int read_hd_data(uint8_t * dst, uint_t length, struct vm_device * dev, struct ide_channel * channel) {
760 struct ide_drive * drive = get_selected_drive(channel);
761 int data_offset = drive->transfer_index % IDE_SECTOR_SIZE;
765 if (drive->transfer_index >= drive->transfer_length) {
766 PrintError("Buffer overrun... (xfer_len=%d) (cur_idx=%x) (post_idx=%d)\n",
767 drive->transfer_length, drive->transfer_index,
768 drive->transfer_index + length);
773 if ((data_offset == 0) && (drive->transfer_index > 0)) {
774 drive->current_lba++;
776 if (ata_read(dev, channel, drive->data_buf, 1) == -1) {
777 PrintError("Could not read next disk sector\n");
783 PrintDebug("Reading HD Data (Val=%x), (len=%d) (offset=%d)\n",
784 *(uint32_t *)(drive->data_buf + data_offset),
785 length, data_offset);
787 memcpy(dst, drive->data_buf + data_offset, length);
789 drive->transfer_index += length;
792 /* This is the trigger for interrupt injection.
793 * For read single sector commands we interrupt after every sector
794 * For multi sector reads we interrupt only at end of the cluster size (mult_sector_num)
795 * cur_sector_num is configured depending on the operation we are currently running
796 * We also trigger an interrupt if this is the last byte to transfer, regardless of sector count
798 if (((drive->transfer_index % (IDE_SECTOR_SIZE * drive->hd_state.cur_sector_num)) == 0) ||
799 (drive->transfer_index == drive->transfer_length)) {
800 if (drive->transfer_index < drive->transfer_length) {
801 // An increment is complete, but there is still more data to be transferred...
802 PrintDebug("Integral Complete, still transferring more sectors\n");
803 channel->status.data_req = 1;
805 drive->irq_flags.c_d = 0;
807 PrintDebug("Final Sector Transferred\n");
808 // This was the final read of the request
809 channel->status.data_req = 0;
812 drive->irq_flags.c_d = 1;
813 drive->irq_flags.rel = 0;
816 channel->status.ready = 1;
817 drive->irq_flags.io_dir = 1;
818 channel->status.busy = 0;
820 ide_raise_irq(dev, channel);
829 static int read_cd_data(uint8_t * dst, uint_t length, struct vm_device * dev, struct ide_channel * channel) {
830 struct ide_drive * drive = get_selected_drive(channel);
831 int data_offset = drive->transfer_index % ATAPI_BLOCK_SIZE;
832 int req_offset = drive->transfer_index % drive->req_len;
834 if (drive->cd_state.atapi_cmd != 0x28) {
835 PrintDebug("IDE: Reading CD Data (len=%d) (req_len=%d)\n", length, drive->req_len);
838 if (drive->transfer_index >= drive->transfer_length) {
839 PrintError("Buffer Overrun... (xfer_len=%d) (cur_idx=%d) (post_idx=%d)\n",
840 drive->transfer_length, drive->transfer_index,
841 drive->transfer_index + length);
847 if ((data_offset == 0) && (drive->transfer_index > 0)) {
848 if (atapi_update_data_buf(dev, channel) == -1) {
849 PrintError("Could not update CDROM data buffer\n");
854 memcpy(dst, drive->data_buf + data_offset, length);
856 drive->transfer_index += length;
859 // Should the req_offset be recalculated here?????
860 if ((req_offset == 0) && (drive->transfer_index > 0)) {
861 if (drive->transfer_index < drive->transfer_length) {
862 // An increment is complete, but there is still more data to be transferred...
864 channel->status.data_req = 1;
866 drive->irq_flags.c_d = 0;
868 // Update the request length in the cylinder regs
869 if (atapi_update_req_len(dev, channel, drive->transfer_length - drive->transfer_index) == -1) {
870 PrintError("Could not update request length after completed increment\n");
874 // This was the final read of the request
875 channel->status.data_req = 0;
876 channel->status.ready = 1;
878 drive->irq_flags.c_d = 1;
879 drive->irq_flags.rel = 0;
882 drive->irq_flags.io_dir = 1;
883 channel->status.busy = 0;
885 ide_raise_irq(dev, channel);
892 static int read_drive_id(uint8_t * dst, uint_t length, struct vm_device * dev, struct ide_channel * channel) {
893 struct ide_drive * drive = get_selected_drive(channel);
895 channel->status.busy = 0;
896 channel->status.ready = 1;
897 channel->status.write_fault = 0;
898 channel->status.seek_complete = 1;
899 channel->status.corrected = 0;
900 channel->status.error = 0;
903 memcpy(dst, drive->data_buf + drive->transfer_index, length);
904 drive->transfer_index += length;
906 if (drive->transfer_index >= drive->transfer_length) {
907 channel->status.data_req = 0;
914 static int ide_read_data_port(ushort_t port, void * dst, uint_t length, struct vm_device * dev) {
915 struct ide_internal * ide = (struct ide_internal *)(dev->private_data);
916 struct ide_channel * channel = get_selected_channel(ide, port);
917 struct ide_drive * drive = get_selected_drive(channel);
919 // PrintDebug("IDE: Reading Data Port %x (len=%d)\n", port, length);
921 if ((channel->cmd_reg == 0xec) ||
922 (channel->cmd_reg == 0xa1)) {
923 return read_drive_id((uint8_t *)dst, length, dev, channel);
926 if (drive->drive_type == IDE_CDROM) {
927 if (read_cd_data((uint8_t *)dst, length, dev, channel) == -1) {
928 PrintError("IDE: Could not read CD Data\n");
931 } else if (drive->drive_type == IDE_DISK) {
932 if (read_hd_data((uint8_t *)dst, length, dev, channel) == -1) {
933 PrintError("IDE: Could not read HD Data\n");
937 memset((uint8_t *)dst, 0, length);
943 static int write_port_std(ushort_t port, void * src, uint_t length, struct vm_device * dev) {
944 struct ide_internal * ide = (struct ide_internal *)(dev->private_data);
945 struct ide_channel * channel = get_selected_channel(ide, port);
946 struct ide_drive * drive = get_selected_drive(channel);
949 PrintError("Invalid Write length on IDE port %x\n", port);
953 PrintDebug("IDE: Writing Standard Port %x (%s) (val=%x)\n", port, io_port_to_str(port), *(uint8_t *)src);
956 // reset and interrupt enable
958 case SEC_CTRL_PORT: {
959 struct ide_ctrl_reg * tmp_ctrl = (struct ide_ctrl_reg *)src;
961 // only reset channel on a 0->1 reset bit transition
962 if ((!channel->ctrl_reg.soft_reset) && (tmp_ctrl->soft_reset)) {
963 channel_reset(channel);
964 } else if ((channel->ctrl_reg.soft_reset) && (!tmp_ctrl->soft_reset)) {
965 channel_reset_complete(channel);
968 channel->ctrl_reg.val = tmp_ctrl->val;
971 case PRI_FEATURES_PORT:
972 case SEC_FEATURES_PORT:
973 channel->features.val = *(uint8_t *)src;
976 case PRI_SECT_CNT_PORT:
977 case SEC_SECT_CNT_PORT:
978 channel->drives[0].sector_count = *(uint8_t *)src;
979 channel->drives[1].sector_count = *(uint8_t *)src;
982 case PRI_SECT_NUM_PORT:
983 case SEC_SECT_NUM_PORT:
984 channel->drives[0].sector_num = *(uint8_t *)src;
985 channel->drives[1].sector_num = *(uint8_t *)src;
987 case PRI_CYL_LOW_PORT:
988 case SEC_CYL_LOW_PORT:
989 channel->drives[0].cylinder_low = *(uint8_t *)src;
990 channel->drives[1].cylinder_low = *(uint8_t *)src;
993 case PRI_CYL_HIGH_PORT:
994 case SEC_CYL_HIGH_PORT:
995 channel->drives[0].cylinder_high = *(uint8_t *)src;
996 channel->drives[1].cylinder_high = *(uint8_t *)src;
999 case PRI_DRV_SEL_PORT:
1000 case SEC_DRV_SEL_PORT: {
1001 channel->drive_head.val = *(uint8_t *)src;
1003 // make sure the reserved bits are ok..
1004 // JRL TODO: check with new ramdisk to make sure this is right...
1005 channel->drive_head.val |= 0xa0;
1007 drive = get_selected_drive(channel);
1009 // Selecting a non-present device is a no-no
1010 if (drive->drive_type == IDE_NONE) {
1011 PrintDebug("Attempting to select a non-present drive\n");
1012 channel->error_reg.abort = 1;
1013 channel->status.error = 1;
1019 PrintError("IDE: Write to unknown Port %x\n", port);
1026 static int read_port_std(ushort_t port, void * dst, uint_t length, struct vm_device * dev) {
1027 struct ide_internal * ide = (struct ide_internal *)(dev->private_data);
1028 struct ide_channel * channel = get_selected_channel(ide, port);
1029 struct ide_drive * drive = get_selected_drive(channel);
1032 PrintError("Invalid Read length on IDE port %x\n", port);
1036 PrintDebug("IDE: Reading Standard Port %x (%s)\n", port, io_port_to_str(port));
1038 if ((port == PRI_ADDR_REG_PORT) ||
1039 (port == SEC_ADDR_REG_PORT)) {
1040 // unused, return 0xff
1041 *(uint8_t *)dst = 0xff;
1046 // if no drive is present just return 0 + reserved bits
1047 if (drive->drive_type == IDE_NONE) {
1048 if ((port == PRI_DRV_SEL_PORT) ||
1049 (port == SEC_DRV_SEL_PORT)) {
1050 *(uint8_t *)dst = 0xa0;
1052 *(uint8_t *)dst = 0;
1060 // This is really the error register.
1061 case PRI_FEATURES_PORT:
1062 case SEC_FEATURES_PORT:
1063 *(uint8_t *)dst = channel->error_reg.val;
1066 case PRI_SECT_CNT_PORT:
1067 case SEC_SECT_CNT_PORT:
1068 *(uint8_t *)dst = drive->sector_count;
1071 case PRI_SECT_NUM_PORT:
1072 case SEC_SECT_NUM_PORT:
1073 *(uint8_t *)dst = drive->sector_num;
1076 case PRI_CYL_LOW_PORT:
1077 case SEC_CYL_LOW_PORT:
1078 *(uint8_t *)dst = drive->cylinder_low;
1082 case PRI_CYL_HIGH_PORT:
1083 case SEC_CYL_HIGH_PORT:
1084 *(uint8_t *)dst = drive->cylinder_high;
1087 case PRI_DRV_SEL_PORT:
1088 case SEC_DRV_SEL_PORT: // hard disk drive and head register 0x1f6
1089 *(uint8_t *)dst = channel->drive_head.val;
1096 // Something about lowering interrupts here....
1097 *(uint8_t *)dst = channel->status.val;
1101 PrintError("Invalid Port: %x\n", port);
1105 PrintDebug("\tVal=%x\n", *(uint8_t *)dst);
1112 static void init_drive(struct ide_drive * drive) {
1114 drive->sector_count = 0x01;
1115 drive->sector_num = 0x01;
1116 drive->cylinder = 0x0000;
1118 drive->drive_type = IDE_NONE;
1120 memset(drive->model, 0, sizeof(drive->model));
1122 drive->transfer_index = 0;
1123 drive->transfer_length = 0;
1124 memset(drive->data_buf, 0, sizeof(drive->data_buf));
1127 drive->private_data = NULL;
1128 drive->cd_ops = NULL;
1131 static void init_channel(struct ide_channel * channel) {
1134 channel->error_reg.val = 0x01;
1135 channel->drive_head.val = 0x00;
1136 channel->status.val = 0x00;
1137 channel->cmd_reg = 0x00;
1138 channel->ctrl_reg.val = 0x08;
1141 channel->dma_cmd.val = 0;
1142 channel->dma_status.val = 0;
1143 channel->dma_prd_addr = 0;
1144 channel->dma_tbl_index = 0;
1146 for (i = 0; i < 2; i++) {
1147 init_drive(&(channel->drives[i]));
1153 static int pci_config_update(struct pci_device * pci_dev, uint_t reg_num, int length) {
1154 PrintDebug("PCI Config Update\n");
1155 PrintDebug("\t\tInterupt register (Dev=%s), irq=%d\n", pci_dev->name, pci_dev->config_header.intr_line);
1160 static int init_ide_state(struct vm_device * dev) {
1161 struct ide_internal * ide = (struct ide_internal *)(dev->private_data);
1162 struct v3_pci_bar bars[6];
1163 struct pci_device * pci_dev = NULL;
1166 for (i = 0; i < 2; i++) {
1167 init_channel(&(ide->channels[i]));
1169 // JRL: this is a terrible hack...
1170 ide->channels[i].irq = PRI_DEFAULT_IRQ + i;
1172 for (j = 0; j < 6; j++) {
1173 bars[j].type = PCI_BAR_NONE;
1177 bars[4].type = PCI_BAR_IO;
1178 bars[4].default_base_port = PRI_DEFAULT_DMA_PORT + (i * 0x8);
1179 bars[4].num_ports = 8;
1182 bars[4].io_read = read_pri_dma_port;
1183 bars[4].io_write = write_pri_dma_port;
1185 bars[4].io_read = read_sec_dma_port;
1186 bars[4].io_write = write_sec_dma_port;
1189 pci_dev = v3_pci_register_device(ide->pci, PCI_STD_DEVICE, 0, "V3_IDE", -1, bars,
1190 pci_config_update, NULL, NULL, dev);
1192 if (pci_dev == NULL) {
1193 PrintError("Failed to register IDE BUS %d with PCI\n", i);
1197 ide->channels[i].pci_dev = pci_dev;
1199 pci_dev->config_header.vendor_id = 0x1095;
1200 pci_dev->config_header.device_id = 0x0646;
1201 pci_dev->config_header.revision = 0x8f07;
1202 pci_dev->config_header.subclass = 0x01;
1203 pci_dev->config_header.class = 0x01;
1205 pci_dev->config_header.intr_line = PRI_DEFAULT_IRQ + i;
1206 pci_dev->config_header.intr_pin = 1;
1211 /* Register PIIX3 Busmaster PCI device */
1212 for (j = 0; j < 6; j++) {
1213 bars[j].type = PCI_BAR_NONE;
1216 pci_dev = v3_pci_register_device(ide->pci, PCI_STD_DEVICE, 0, "PIIX3 IDE", -1, bars,
1217 NULL, NULL, NULL, dev);
1220 ide->busmaster_pci = pci_dev;
1222 pci_dev->config_header.vendor_id = 0x8086;
1223 pci_dev->config_header.device_id = 0x7010;
1224 pci_dev->config_header.revision = 0x80;
1225 pci_dev->config_header.subclass = 0x01;
1226 pci_dev->config_header.class = 0x01;
1234 static int init_ide(struct vm_device * dev) {
1235 //struct ide_internal * ide = (struct ide_internal *)(dev->private_data);
1237 PrintDebug("IDE: Initializing IDE\n");
1239 if (init_ide_state(dev) == -1) {
1240 PrintError("Failed to initialize IDE state\n");
1245 v3_dev_hook_io(dev, PRI_DATA_PORT,
1246 &ide_read_data_port, &write_data_port);
1247 v3_dev_hook_io(dev, PRI_FEATURES_PORT,
1248 &read_port_std, &write_port_std);
1249 v3_dev_hook_io(dev, PRI_SECT_CNT_PORT,
1250 &read_port_std, &write_port_std);
1251 v3_dev_hook_io(dev, PRI_SECT_NUM_PORT,
1252 &read_port_std, &write_port_std);
1253 v3_dev_hook_io(dev, PRI_CYL_LOW_PORT,
1254 &read_port_std, &write_port_std);
1255 v3_dev_hook_io(dev, PRI_CYL_HIGH_PORT,
1256 &read_port_std, &write_port_std);
1257 v3_dev_hook_io(dev, PRI_DRV_SEL_PORT,
1258 &read_port_std, &write_port_std);
1259 v3_dev_hook_io(dev, PRI_CMD_PORT,
1260 &read_port_std, &write_cmd_port);
1262 v3_dev_hook_io(dev, SEC_DATA_PORT,
1263 &ide_read_data_port, &write_data_port);
1264 v3_dev_hook_io(dev, SEC_FEATURES_PORT,
1265 &read_port_std, &write_port_std);
1266 v3_dev_hook_io(dev, SEC_SECT_CNT_PORT,
1267 &read_port_std, &write_port_std);
1268 v3_dev_hook_io(dev, SEC_SECT_NUM_PORT,
1269 &read_port_std, &write_port_std);
1270 v3_dev_hook_io(dev, SEC_CYL_LOW_PORT,
1271 &read_port_std, &write_port_std);
1272 v3_dev_hook_io(dev, SEC_CYL_HIGH_PORT,
1273 &read_port_std, &write_port_std);
1274 v3_dev_hook_io(dev, SEC_DRV_SEL_PORT,
1275 &read_port_std, &write_port_std);
1276 v3_dev_hook_io(dev, SEC_CMD_PORT,
1277 &read_port_std, &write_cmd_port);
1280 v3_dev_hook_io(dev, PRI_CTRL_PORT,
1281 &read_port_std, &write_port_std);
1283 v3_dev_hook_io(dev, SEC_CTRL_PORT,
1284 &read_port_std, &write_port_std);
1287 v3_dev_hook_io(dev, SEC_ADDR_REG_PORT,
1288 &read_port_std, &write_port_std);
1290 v3_dev_hook_io(dev, PRI_ADDR_REG_PORT,
1291 &read_port_std, &write_port_std);
1297 static int deinit_ide(struct vm_device * dev) {
1298 // unhook io ports....
1299 // deregister from PCI?
1304 static struct vm_device_ops dev_ops = {
1306 .deinit = deinit_ide,
1313 struct vm_device * v3_create_ide(struct vm_device * pci) {
1314 struct ide_internal * ide = (struct ide_internal *)V3_Malloc(sizeof(struct ide_internal));
1315 struct vm_device * device = v3_create_device("IDE", &dev_ops, ide);
1319 PrintDebug("IDE: Creating IDE bus x 2\n");
1328 int v3_ide_register_cdrom(struct vm_device * ide_dev,
1332 struct v3_ide_cd_ops * ops,
1333 void * private_data) {
1335 struct ide_internal * ide = (struct ide_internal *)(ide_dev->private_data);
1336 struct ide_channel * channel = NULL;
1337 struct ide_drive * drive = NULL;
1339 V3_ASSERT((bus_num >= 0) && (bus_num < 2));
1340 V3_ASSERT((drive_num >= 0) && (drive_num < 2));
1342 channel = &(ide->channels[bus_num]);
1343 drive = &(channel->drives[drive_num]);
1345 if (drive->drive_type != IDE_NONE) {
1346 PrintError("Device slot (bus=%d, drive=%d) already occupied\n", bus_num, drive_num);
1350 strncpy(drive->model, dev_name, sizeof(drive->model) - 1);
1352 while (strlen((char *)(drive->model)) < 40) {
1353 strcat((char*)(drive->model), " ");
1357 drive->drive_type = IDE_CDROM;
1359 drive->cd_ops = ops;
1361 drive->private_data = private_data;
1367 int v3_ide_register_harddisk(struct vm_device * ide_dev,
1371 struct v3_ide_hd_ops * ops,
1372 void * private_data) {
1374 struct ide_internal * ide = (struct ide_internal *)(ide_dev->private_data);
1375 struct ide_channel * channel = NULL;
1376 struct ide_drive * drive = NULL;
1378 V3_ASSERT((bus_num >= 0) && (bus_num < 2));
1379 V3_ASSERT((drive_num >= 0) && (drive_num < 2));
1381 channel = &(ide->channels[bus_num]);
1382 drive = &(channel->drives[drive_num]);
1384 if (drive->drive_type != IDE_NONE) {
1385 PrintError("Device slot (bus=%d, drive=%d) already occupied\n", bus_num, drive_num);
1389 strncpy(drive->model, dev_name, sizeof(drive->model) - 1);
1391 drive->drive_type = IDE_DISK;
1393 drive->hd_state.accessed = 0;
1394 drive->hd_state.mult_sector_num = 1;
1396 drive->hd_ops = ops;
1398 drive->private_data = private_data;