2 * This file is part of the Palacios Virtual Machine Monitor developed
3 * by the V3VEE Project with funding from the United States National
4 * Science Foundation and the Department of Energy.
6 * The V3VEE Project is a joint project between Northwestern University
7 * and the University of New Mexico. You can find out more at
10 * Copyright (c) 2008, Jack Lange <jarusl@cs.northwestern.edu>
11 * Copyright (c) 2008, The V3VEE Project <http://www.v3vee.org>
12 * All rights reserved.
14 * Author: Jack Lange <jarusl@cs.northwestern.edu>
16 * This is free software. You are permitted to use,
17 * redistribute, and modify it as specified in the file "V3VEE_LICENSE".
20 #include <palacios/vmm.h>
21 #include <palacios/vm_guest_mem.h>
22 #include <devices/ide.h>
23 #include <devices/pci.h>
24 #include "ide-types.h"
25 #include "atapi-types.h"
27 #define PRI_DEFAULT_IRQ 14
28 #define SEC_DEFAULT_IRQ 15
31 #define PRI_DATA_PORT 0x1f0
32 #define PRI_FEATURES_PORT 0x1f1
33 #define PRI_SECT_CNT_PORT 0x1f2
34 #define PRI_SECT_NUM_PORT 0x1f3
35 #define PRI_CYL_LOW_PORT 0x1f4
36 #define PRI_CYL_HIGH_PORT 0x1f5
37 #define PRI_DRV_SEL_PORT 0x1f6
38 #define PRI_CMD_PORT 0x1f7
39 #define PRI_CTRL_PORT 0x3f6
40 #define PRI_ADDR_REG_PORT 0x3f7
42 #define SEC_DATA_PORT 0x170
43 #define SEC_FEATURES_PORT 0x171
44 #define SEC_SECT_CNT_PORT 0x172
45 #define SEC_SECT_NUM_PORT 0x173
46 #define SEC_CYL_LOW_PORT 0x174
47 #define SEC_CYL_HIGH_PORT 0x175
48 #define SEC_DRV_SEL_PORT 0x176
49 #define SEC_CMD_PORT 0x177
50 #define SEC_CTRL_PORT 0x376
51 #define SEC_ADDR_REG_PORT 0x377
54 #define PRI_DEFAULT_DMA_PORT 0xc000
55 #define SEC_DEFAULT_DMA_PORT 0xc008
58 #define DATA_BUFFER_SIZE 2048
60 static const char * ide_pri_port_strs[] = {"PRI_DATA", "PRI_FEATURES", "PRI_SECT_CNT", "PRI_SECT_NUM",
61 "PRI_CYL_LOW", "PRI_CYL_HIGH", "PRI_DRV_SEL", "PRI_CMD",
62 "PRI_CTRL", "PRI_ADDR_REG"};
65 static const char * ide_sec_port_strs[] = {"SEC_DATA", "SEC_FEATURES", "SEC_SECT_CNT", "SEC_SECT_NUM",
66 "SEC_CYL_LOW", "SEC_CYL_HIGH", "SEC_DRV_SEL", "SEC_CMD",
67 "SEC_CTRL", "SEC_ADDR_REG"};
69 static const char * ide_dma_port_strs[] = {"DMA_CMD", NULL, "DMA_STATUS", NULL,
70 "DMA_PRD0", "DMA_PRD1", "DMA_PRD2", "DMA_PRD3"};
74 static inline const char * io_port_to_str(uint16_t port) {
75 if ((port >= PRI_DATA_PORT) && (port <= PRI_CMD_PORT)) {
76 return ide_pri_port_strs[port - PRI_DATA_PORT];
77 } else if ((port >= SEC_DATA_PORT) && (port <= SEC_CMD_PORT)) {
78 return ide_sec_port_strs[port - SEC_DATA_PORT];
79 } else if ((port == PRI_CTRL_PORT) || (port == PRI_ADDR_REG_PORT)) {
80 return ide_pri_port_strs[port - PRI_CTRL_PORT + 8];
81 } else if ((port == SEC_CTRL_PORT) || (port == SEC_ADDR_REG_PORT)) {
82 return ide_sec_port_strs[port - SEC_CTRL_PORT + 8];
88 static inline const char * dma_port_to_str(uint16_t port) {
89 return ide_dma_port_strs[port & 0x7];
93 static const char * ide_dev_type_strs[] = {"HARDDISK", "CDROM", "NONE"};
96 static inline const char * device_type_to_str(v3_ide_dev_type_t type) {
101 return ide_dev_type_strs[type];
106 struct ide_cd_state {
107 struct atapi_sense_data sense;
110 struct atapi_error_recovery err_recovery;
113 struct ide_hd_state {
120 v3_ide_dev_type_t drive_type;
123 struct v3_ide_cd_ops * cd_ops;
124 struct v3_ide_hd_ops * hd_ops;
129 struct ide_cd_state cd_state;
130 struct ide_hd_state hd_state;
135 // Where we are in the data transfer
136 uint_t transfer_index;
138 // the length of a transfer
139 // calculated for easy access
140 uint_t transfer_length;
143 // We have a local data buffer that we use for IO port accesses
144 uint8_t data_buf[DATA_BUFFER_SIZE];
150 uint8_t sector_count; // 0x1f2,0x172
151 struct atapi_irq_flags irq_flags;
152 } __attribute__((packed));
155 uint8_t sector_num; // 0x1f3,0x173
165 uint8_t cylinder_low; // 0x1f4,0x174
166 uint8_t cylinder_high; // 0x1f5,0x175
167 } __attribute__((packed));
172 } __attribute__((packed));
175 // The transfer length requested by the CPU
177 } __attribute__((packed));
184 struct ide_drive drives[2];
187 struct ide_error_reg error_reg; // [read] 0x1f1,0x171
189 struct ide_features_reg features;
191 struct ide_drive_head_reg drive_head; // 0x1f6,0x176
193 struct ide_status_reg status; // [read] 0x1f7,0x177
194 uint8_t cmd_reg; // [write] 0x1f7,0x177
196 int irq; // this is temporary until we add PCI support
198 struct pci_device * pci_dev;
201 struct ide_ctrl_reg ctrl_reg; // [write] 0x3f6,0x376
203 struct ide_dma_cmd_reg dma_cmd;
204 struct ide_dma_status_reg dma_status;
205 uint32_t dma_prd_addr;
206 uint_t dma_tbl_index;
211 struct ide_internal {
212 struct ide_channel channels[2];
213 struct vm_device * pci;
214 struct pci_device * busmaster_pci;
221 /* Utility functions */
223 static inline uint16_t be_to_le_16(const uint16_t val) {
224 uint8_t * buf = (uint8_t *)&val;
225 return (buf[0] << 8) | (buf[1]) ;
228 static inline uint16_t le_to_be_16(const uint16_t val) {
229 return be_to_le_16(val);
233 static inline uint32_t be_to_le_32(const uint32_t val) {
234 uint8_t * buf = (uint8_t *)&val;
235 return (buf[0] << 24) | (buf[1] << 16) | (buf[2] << 8) | buf[3];
238 static inline uint32_t le_to_be_32(const uint32_t val) {
239 return be_to_le_32(val);
243 static inline int get_channel_index(ushort_t port) {
244 if (((port & 0xfff8) == 0x1f0) ||
245 ((port & 0xfffe) == 0x3f6) ||
246 ((port & 0xfff8) == 0xc000)) {
248 } else if (((port & 0xfff8) == 0x170) ||
249 ((port & 0xfffe) == 0x376) ||
250 ((port & 0xfff8) == 0xc008)) {
257 static inline struct ide_channel * get_selected_channel(struct ide_internal * ide, ushort_t port) {
258 int channel_idx = get_channel_index(port);
259 return &(ide->channels[channel_idx]);
262 static inline struct ide_drive * get_selected_drive(struct ide_channel * channel) {
263 return &(channel->drives[channel->drive_head.drive_sel]);
267 static inline int is_lba_enabled(struct ide_channel * channel) {
268 return channel->drive_head.lba_mode;
273 static void ide_raise_irq(struct vm_device * dev, struct ide_channel * channel) {
274 if (channel->ctrl_reg.irq_disable == 0) {
275 PrintDebug("Raising IDE Interrupt %d\n", channel->irq);
276 channel->dma_status.int_gen = 1;
277 v3_raise_irq(dev->vm, channel->irq);
282 static void drive_reset(struct ide_drive * drive) {
283 drive->sector_count = 0x01;
284 drive->sector_num = 0x01;
286 if (drive->drive_type == IDE_CDROM) {
287 drive->cylinder = 0xeb14;
289 drive->cylinder = 0x0000;
293 memset(drive->data_buf, 0, sizeof(drive->data_buf));
294 drive->transfer_index = 0;
296 // Send the reset signal to the connected device callbacks
297 // channel->drives[0].reset();
298 // channel->drives[1].reset();
301 static void channel_reset(struct ide_channel * channel) {
303 // set busy and seek complete flags
304 channel->status.val = 0x90;
307 channel->error_reg.val = 0x01;
310 channel->cmd_reg = 0x00;
312 channel->ctrl_reg.irq_disable = 0;
315 static void channel_reset_complete(struct ide_channel * channel) {
316 channel->status.busy = 0;
317 channel->status.ready = 1;
319 channel->drive_head.head_num = 0;
321 drive_reset(&(channel->drives[0]));
322 drive_reset(&(channel->drives[1]));
326 static void ide_abort_command(struct vm_device * dev, struct ide_channel * channel) {
327 channel->status.val = 0x41; // Error + ready
328 channel->error_reg.val = 0x04; // No idea...
330 ide_raise_irq(dev, channel);
335 static void ide_identify_device(struct ide_drive * drive) {
336 struct ide_drive_id * drive_id = (struct ide_drive_id *)(drive->data_buf);
337 const char* serial_number = " VT00001\0\0\0\0\0\0\0\0\0\0\0\0";
338 const char* firmware = "ALPHA1 ";
340 drive->transfer_length = 512;
341 drive->transfer_index = 0;
344 memset(drive_id->buf, 0, sizeof(drive_id->buf));
346 drive_id->fixed_drive = 1;
347 drive_id->removable_media = 0;
350 drive_id->disk_speed1 = 1;
351 drive_id->disk_speed3 = 1;
353 drive_id->cdrom_flag = 0;
355 // Make it the simplest drive possible (1 head, 1 cyl, 1 sect/track)
356 drive_id->num_cylinders = 1;
357 drive_id->num_heads = 1;
358 drive_id->bytes_per_track = IDE_SECTOR_SIZE;
359 drive_id->bytes_per_sector = IDE_SECTOR_SIZE;
360 drive_id->sectors_per_track = 1;
363 // These buffers do not contain a terminating "\0"
364 memcpy(drive_id->serial_num, serial_number, strlen(serial_number));
365 memcpy(drive_id->firmware_rev, firmware, strlen(firmware));
366 memcpy(drive_id->model_num, drive->model, 40);
369 drive_id->dword_io = 1;
372 drive_id->dma_enable = 1;
375 drive_id->lba_enable = 1;
378 drive_id->lba_capacity = drive->hd_ops->get_capacity(drive->private_data);
380 drive_id->rw_multiples = 0x80ff;
382 // words 64-70, 54-58 valid
383 drive_id->field_valid = 0x0007; // DMA + pkg cmd valid
385 // copied from CFA540A
386 drive_id->buf[63] = 0x0103; // variable (DMA stuff)
387 //drive_id->buf[63] = 0x0000; // variable (DMA stuff)
389 // drive_id->buf[64] = 0x0001; // PIO
390 drive_id->buf[65] = 0x00b4;
391 drive_id->buf[66] = 0x00b4;
392 drive_id->buf[67] = 0x012c;
393 drive_id->buf[68] = 0x00b4;
395 drive_id->buf[71] = 30; // faked
396 drive_id->buf[72] = 30; // faked
398 // drive_id->buf[80] = 0x1e; // supports up to ATA/ATAPI-4
399 drive_id->major_rev_num = 0x0040; // supports up to ATA/ATAPI-6
401 drive_id->dma_ultra = 0x2020; // Ultra_DMA_Mode_5_Selected | Ultra_DMA_Mode_5_Supported;
411 /* ATAPI functions */
417 static int dma_read(struct vm_device * dev, struct ide_channel * channel) {
418 struct ide_drive * drive = get_selected_drive(channel);
419 struct ide_dma_prd prd_entry;
420 uint32_t prd_entry_addr = channel->dma_prd_addr + (sizeof(struct ide_dma_prd) * channel->dma_tbl_index);
424 PrintDebug("PRD table address = %x\n", channel->dma_prd_addr);
426 ret = read_guest_pa_memory(dev->vm, prd_entry_addr, sizeof(struct ide_dma_prd), (void *)&prd_entry);
428 if (ret != sizeof(struct ide_dma_prd)) {
429 PrintError("Could not read PRD\n");
433 PrintDebug("PRD Addr: %x, PDR Len: %d, EOT: %d\n", prd_entry.base_addr, prd_entry.size, prd_entry.end_of_table);
435 ret = write_guest_pa_memory(dev->vm, prd_entry.base_addr, prd_entry.size, drive->data_buf);
437 if (ret != prd_entry.size) {
438 PrintError("Failed to copy data into guest memory... (ret=%d)\n", ret);
442 channel->status.busy = 0;
443 channel->status.ready = 1;
444 channel->status.data_req = 0;
445 channel->status.error = 0;
446 channel->status.seek_complete = 1;
449 drive->irq_flags.io_dir = 1;
450 drive->irq_flags.c_d = 1;
451 drive->irq_flags.rel = 0;
456 channel->dma_status.active = 0;
457 channel->dma_status.err = 1;
458 channel->dma_status.int_gen = 1;
460 ide_raise_irq(dev, channel);
466 static int dma_write(struct vm_device * dev, struct ide_channel * channel) {
468 PrintError("DMA writes currently not supported\n");
474 * This is an ugly ugly ugly way to differentiate between the first and second DMA channels
477 static int write_dma_port(ushort_t port_offset, void * src, uint_t length, struct vm_device * dev, struct ide_channel * channel);
478 static int read_dma_port(ushort_t port_offset, void * dst, uint_t length, struct vm_device * dev, struct ide_channel * channel);
481 static int write_pri_dma_port(ushort_t port, void * src, uint_t length, struct vm_device * dev) {
482 struct ide_internal * ide = (struct ide_internal *)(dev->private_data);
483 PrintDebug("IDE: Writing PRI DMA Port %x (%s) (val=%x)\n", port, dma_port_to_str(port & 0x7), *(uint32_t *)src);
484 return write_dma_port(port & 0x7, src, length, dev, &(ide->channels[0]));
487 static int write_sec_dma_port(ushort_t port, void * src, uint_t length, struct vm_device * dev) {
488 struct ide_internal * ide = (struct ide_internal *)(dev->private_data);
489 PrintDebug("IDE: Writing SEC DMA Port %x (%s) (val=%x)\n", port, dma_port_to_str(port & 0x7), *(uint32_t *)src);
490 return write_dma_port(port & 0x7, src, length, dev, &(ide->channels[1]));
494 static int read_pri_dma_port(ushort_t port, void * dst, uint_t length, struct vm_device * dev) {
495 struct ide_internal * ide = (struct ide_internal *)(dev->private_data);
496 PrintDebug("IDE: Reading PRI DMA Port %x (%s)\n", port, dma_port_to_str(port & 0x7));
497 return read_dma_port(port & 0x7, dst, length, dev, &(ide->channels[0]));
500 static int read_sec_dma_port(ushort_t port, void * dst, uint_t length, struct vm_device * dev) {
501 struct ide_internal * ide = (struct ide_internal *)(dev->private_data);
502 PrintDebug("IDE: Reading SEC DMA Port %x (%s)\n", port, dma_port_to_str(port & 0x7));
503 return read_dma_port(port & 0x7, dst, length, dev, &(ide->channels[1]));
507 #define DMA_CMD_PORT 0x00
508 #define DMA_STATUS_PORT 0x02
509 #define DMA_PRD_PORT0 0x04
510 #define DMA_PRD_PORT1 0x05
511 #define DMA_PRD_PORT2 0x06
512 #define DMA_PRD_PORT3 0x07
515 static int write_dma_port(ushort_t port_offset, void * src, uint_t length,
516 struct vm_device * dev, struct ide_channel * channel) {
518 switch (port_offset) {
520 channel->dma_cmd.val = *(uint8_t *)src;
522 if (channel->dma_cmd.start == 0) {
523 channel->dma_tbl_index = 0;
525 channel->dma_status.active = 1;
527 if (channel->dma_cmd.read == 1) {
529 if (dma_read(dev, channel) == -1) {
530 PrintError("Failed DMA Read\n");
535 if (dma_write(dev, channel) == -1) {
536 PrintError("Failed DMA Write\n");
544 case DMA_STATUS_PORT:
546 PrintError("Invalid read length for DMA status port\n");
550 channel->dma_status.val = *(uint8_t *)src;
556 case DMA_PRD_PORT3: {
557 uint_t addr_index = port_offset & 0x3;
558 uint8_t * addr_buf = (uint8_t *)&(channel->dma_prd_addr);
561 if (addr_index + length > 4) {
562 PrintError("DMA Port space overrun port=%x len=%d\n", port_offset, length);
566 for (i = 0; i < length; i++) {
567 addr_buf[addr_index + i] = *((uint8_t *)src + i);
570 PrintDebug("Writing PRD Port %x (val=%x)\n", port_offset, channel->dma_prd_addr);
575 PrintError("IDE: Invalid DMA Port (%s)\n", dma_port_to_str(port_offset));
583 static int read_dma_port(ushort_t port_offset, void * dst, uint_t length,
584 struct vm_device * dev, struct ide_channel * channel) {
586 switch (port_offset) {
588 *(uint8_t *)dst = channel->dma_cmd.val;
591 case DMA_STATUS_PORT:
593 PrintError("Invalid read length for DMA status port\n");
597 *(uint8_t *)dst = channel->dma_status.val;
603 case DMA_PRD_PORT3: {
604 uint_t addr_index = port_offset & 0x3;
605 uint8_t * addr_buf = (uint8_t *)&(channel->dma_prd_addr);
608 if (addr_index + length > 4) {
609 PrintError("DMA Port space overrun port=%x len=%d\n", port_offset, length);
613 for (i = 0; i < length; i++) {
614 *((uint8_t *)dst + i) = addr_buf[addr_index + i];
620 PrintError("IDE: Invalid DMA Port (%s)\n", dma_port_to_str(port_offset));
624 PrintDebug("\tval=%x\n", *(uint32_t *)dst);
631 static int write_cmd_port(ushort_t port, void * src, uint_t length, struct vm_device * dev) {
632 struct ide_internal * ide = (struct ide_internal *)(dev->private_data);
633 struct ide_channel * channel = get_selected_channel(ide, port);
634 struct ide_drive * drive = get_selected_drive(channel);
637 PrintError("Invalid Write Length on IDE command Port %x\n", port);
641 PrintDebug("IDE: Writing Command Port %x (%s) (val=%x)\n", port, io_port_to_str(port), *(uint8_t *)src);
643 channel->cmd_reg = *(uint8_t *)src;
645 switch (channel->cmd_reg) {
647 case 0xa0: // ATAPI Command Packet
648 if (drive->drive_type != IDE_CDROM) {
649 ide_abort_command(dev, channel);
652 drive->sector_count = 1;
654 channel->status.busy = 0;
655 channel->status.write_fault = 0;
656 channel->status.data_req = 1;
657 channel->status.error = 0;
659 // reset the data buffer...
660 drive->transfer_length = ATAPI_PACKET_SIZE;
661 drive->transfer_index = 0;
664 case 0xa1: // ATAPI Identify Device Packet
665 atapi_identify_device(drive);
667 channel->error_reg.val = 0;
668 channel->status.val = 0x58; // ready, data_req, seek_complete
670 ide_raise_irq(dev, channel);
672 case 0xec: // Identify Device
673 if (drive->drive_type != IDE_DISK) {
676 // JRL: Should we abort here?
677 ide_abort_command(dev, channel);
679 ide_identify_device(drive);
681 channel->error_reg.val = 0;
682 channel->status.val = 0x58;
684 ide_raise_irq(dev, channel);
688 case 0xef: // Set Features
689 // Prior to this the features register has been written to.
690 // This command tells the drive to check if the new value is supported (the value is drive specific)
691 // Common is that bit0=DMA enable
692 // If valid the drive raises an interrupt, if not it aborts.
694 // Do some checking here...
696 channel->status.busy = 0;
697 channel->status.write_fault = 0;
698 channel->status.error = 0;
699 channel->status.ready = 1;
700 channel->status.seek_complete = 1;
702 ide_raise_irq(dev, channel);
705 PrintError("Unimplemented IDE command (%x)\n", channel->cmd_reg);
713 static int write_data_port(ushort_t port, void * src, uint_t length, struct vm_device * dev) {
714 struct ide_internal * ide = (struct ide_internal *)(dev->private_data);
715 struct ide_channel * channel = get_selected_channel(ide, port);
716 struct ide_drive * drive = get_selected_drive(channel);
718 // PrintDebug("IDE: Writing Data Port %x (val=%x, len=%d)\n",
719 // port, *(uint32_t *)src, length);
721 memcpy(drive->data_buf + drive->transfer_index, src, length);
722 drive->transfer_index += length;
724 // Transfer is complete, dispatch the command
725 if (drive->transfer_index >= drive->transfer_length) {
726 switch (channel->cmd_reg) {
727 case 0x30: // Write Sectors
728 PrintError("Writing Data not yet implemented\n");
731 case 0xa0: // ATAPI packet command
732 if (atapi_handle_packet(dev, channel) == -1) {
733 PrintError("Error handling ATAPI packet\n");
738 PrintError("Unhandld IDE Command %x\n", channel->cmd_reg);
747 static int read_hd_data(uint8_t * dst, uint_t length, struct vm_device * dev, struct ide_channel * channel) {
748 PrintError("Harddrive data port read not implemented\n");
754 static int read_cd_data(uint8_t * dst, uint_t length, struct vm_device * dev, struct ide_channel * channel) {
755 struct ide_drive * drive = get_selected_drive(channel);
756 int data_offset = drive->transfer_index % DATA_BUFFER_SIZE;
757 int req_offset = drive->transfer_index % drive->req_len;
759 if (drive->cd_state.atapi_cmd != 0x28) {
760 PrintDebug("IDE: Reading CD Data (len=%d) (req_len=%d)\n", length, drive->req_len);
763 if (drive->transfer_index >= drive->transfer_length) {
764 PrintError("Buffer Overrun... (xfer_len=%d) (cur_idx=%d) (post_idx=%d)\n",
765 drive->transfer_length, drive->transfer_index,
766 drive->transfer_index + length);
772 if ((data_offset == 0) && (drive->transfer_index > 0)) {
774 if (drive->drive_type == IDE_CDROM) {
775 if (atapi_update_data_buf(dev, channel) == -1) {
776 PrintError("Could not update CDROM data buffer\n");
780 PrintError("IDE Harddrives not implemented\n");
785 memcpy(dst, drive->data_buf + data_offset, length);
787 drive->transfer_index += length;
789 if ((req_offset == 0) && (drive->transfer_index > 0)) {
790 if (drive->transfer_index < drive->transfer_length) {
791 // An increment is complete, but there is still more data to be transferred...
793 channel->status.data_req = 1;
795 drive->irq_flags.c_d = 0;
797 // Update the request length in the cylinder regs
798 if (atapi_update_req_len(dev, channel, drive->transfer_length - drive->transfer_index) == -1) {
799 PrintError("Could not update request length after completed increment\n");
803 // This was the final read of the request
804 channel->status.data_req = 0;
805 channel->status.ready = 1;
807 drive->irq_flags.c_d = 1;
808 drive->irq_flags.rel = 0;
811 drive->irq_flags.io_dir = 1;
812 channel->status.busy = 0;
814 ide_raise_irq(dev, channel);
821 static int read_drive_id(uint8_t * dst, uint_t length, struct vm_device * dev, struct ide_channel * channel) {
822 struct ide_drive * drive = get_selected_drive(channel);
824 channel->status.busy = 0;
825 channel->status.ready = 1;
826 channel->status.write_fault = 0;
827 channel->status.seek_complete = 1;
828 channel->status.corrected = 0;
829 channel->status.error = 0;
832 memcpy(dst, drive->data_buf + drive->transfer_index, length);
833 drive->transfer_index += length;
835 if (drive->transfer_index >= drive->transfer_length) {
836 channel->status.data_req = 0;
843 static int ide_read_data_port(ushort_t port, void * dst, uint_t length, struct vm_device * dev) {
844 struct ide_internal * ide = (struct ide_internal *)(dev->private_data);
845 struct ide_channel * channel = get_selected_channel(ide, port);
846 struct ide_drive * drive = get_selected_drive(channel);
848 // PrintDebug("IDE: Reading Data Port %x (len=%d)\n", port, length);
850 if ((channel->cmd_reg == 0xec) ||
851 (channel->cmd_reg == 0xa1)) {
852 return read_drive_id((uint8_t *)dst, length, dev, channel);
855 if (drive->drive_type == IDE_CDROM) {
856 if (read_cd_data((uint8_t *)dst, length, dev, channel) == -1) {
857 PrintError("IDE: Could not read CD Data\n");
860 } else if (drive->drive_type == IDE_DISK) {
861 if (read_hd_data((uint8_t *)dst, length, dev, channel) == -1) {
862 PrintError("IDE: Could not read HD Data\n");
866 memset((uint8_t *)dst, 0, length);
872 static int write_port_std(ushort_t port, void * src, uint_t length, struct vm_device * dev) {
873 struct ide_internal * ide = (struct ide_internal *)(dev->private_data);
874 struct ide_channel * channel = get_selected_channel(ide, port);
875 struct ide_drive * drive = get_selected_drive(channel);
878 PrintError("Invalid Write length on IDE port %x\n", port);
882 PrintDebug("IDE: Writing Standard Port %x (%s) (val=%x)\n", port, io_port_to_str(port), *(uint8_t *)src);
885 // reset and interrupt enable
887 case SEC_CTRL_PORT: {
888 struct ide_ctrl_reg * tmp_ctrl = (struct ide_ctrl_reg *)src;
890 // only reset channel on a 0->1 reset bit transition
891 if ((!channel->ctrl_reg.soft_reset) && (tmp_ctrl->soft_reset)) {
892 channel_reset(channel);
893 } else if ((channel->ctrl_reg.soft_reset) && (!tmp_ctrl->soft_reset)) {
894 channel_reset_complete(channel);
897 channel->ctrl_reg.val = tmp_ctrl->val;
900 case PRI_FEATURES_PORT:
901 case SEC_FEATURES_PORT:
902 channel->features.val = *(uint8_t *)src;
905 case PRI_SECT_CNT_PORT:
906 case SEC_SECT_CNT_PORT:
907 drive->sector_count = *(uint8_t *)src;
910 case PRI_SECT_NUM_PORT:
911 case SEC_SECT_NUM_PORT:
912 drive->sector_num = *(uint8_t *)src;
914 case PRI_CYL_LOW_PORT:
915 case SEC_CYL_LOW_PORT:
916 drive->cylinder_low = *(uint8_t *)src;
919 case PRI_CYL_HIGH_PORT:
920 case SEC_CYL_HIGH_PORT:
921 drive->cylinder_high = *(uint8_t *)src;
924 case PRI_DRV_SEL_PORT:
925 case SEC_DRV_SEL_PORT: {
926 channel->drive_head.val = *(uint8_t *)src;
928 // make sure the reserved bits are ok..
929 // JRL TODO: check with new ramdisk to make sure this is right...
930 channel->drive_head.val |= 0xa0;
932 drive = get_selected_drive(channel);
934 // Selecting a non-present device is a no-no
935 if (drive->drive_type == IDE_NONE) {
936 PrintDebug("Attempting to select a non-present drive\n");
937 channel->error_reg.abort = 1;
938 channel->status.error = 1;
944 PrintError("IDE: Write to unknown Port %x\n", port);
951 static int read_port_std(ushort_t port, void * dst, uint_t length, struct vm_device * dev) {
952 struct ide_internal * ide = (struct ide_internal *)(dev->private_data);
953 struct ide_channel * channel = get_selected_channel(ide, port);
954 struct ide_drive * drive = get_selected_drive(channel);
957 PrintError("Invalid Read length on IDE port %x\n", port);
961 PrintDebug("IDE: Reading Standard Port %x (%s)\n", port, io_port_to_str(port));
963 if ((port == PRI_ADDR_REG_PORT) ||
964 (port == SEC_ADDR_REG_PORT)) {
965 // unused, return 0xff
966 *(uint8_t *)dst = 0xff;
971 // if no drive is present just return 0 + reserved bits
972 if (drive->drive_type == IDE_NONE) {
973 if ((port == PRI_DRV_SEL_PORT) ||
974 (port == SEC_DRV_SEL_PORT)) {
975 *(uint8_t *)dst = 0xa0;
985 // This is really the error register.
986 case PRI_FEATURES_PORT:
987 case SEC_FEATURES_PORT:
988 *(uint8_t *)dst = channel->error_reg.val;
991 case PRI_SECT_CNT_PORT:
992 case SEC_SECT_CNT_PORT:
993 *(uint8_t *)dst = drive->sector_count;
996 case PRI_SECT_NUM_PORT:
997 case SEC_SECT_NUM_PORT:
998 *(uint8_t *)dst = drive->sector_num;
1001 case PRI_CYL_LOW_PORT:
1002 case SEC_CYL_LOW_PORT:
1003 *(uint8_t *)dst = drive->cylinder_low;
1007 case PRI_CYL_HIGH_PORT:
1008 case SEC_CYL_HIGH_PORT:
1009 *(uint8_t *)dst = drive->cylinder_high;
1012 case PRI_DRV_SEL_PORT:
1013 case SEC_DRV_SEL_PORT: // hard disk drive and head register 0x1f6
1014 *(uint8_t *)dst = channel->drive_head.val;
1021 // Something about lowering interrupts here....
1022 *(uint8_t *)dst = channel->status.val;
1026 PrintError("Invalid Port: %x\n", port);
1030 PrintDebug("\tVal=%x\n", *(uint8_t *)dst);
1037 static void init_drive(struct ide_drive * drive) {
1039 drive->sector_count = 0x01;
1040 drive->sector_num = 0x01;
1041 drive->cylinder = 0x0000;
1043 drive->drive_type = IDE_NONE;
1045 memset(drive->model, 0, sizeof(drive->model));
1047 drive->transfer_index = 0;
1048 drive->transfer_length = 0;
1049 memset(drive->data_buf, 0, sizeof(drive->data_buf));
1053 drive->private_data = NULL;
1054 drive->cd_ops = NULL;
1057 static void init_channel(struct ide_channel * channel) {
1060 channel->error_reg.val = 0x01;
1061 channel->drive_head.val = 0x00;
1062 channel->status.val = 0x00;
1063 channel->cmd_reg = 0x00;
1064 channel->ctrl_reg.val = 0x08;
1067 channel->dma_cmd.val = 0;
1068 channel->dma_status.val = 0;
1069 channel->dma_prd_addr = 0;
1070 channel->dma_tbl_index = 0;
1072 for (i = 0; i < 2; i++) {
1073 init_drive(&(channel->drives[i]));
1079 static int pci_config_update(struct pci_device * pci_dev, uint_t reg_num, int length) {
1080 PrintDebug("Interupt register (Dev=%s), irq=%d\n", pci_dev->name, pci_dev->config_header.intr_line);
1085 static int init_ide_state(struct vm_device * dev) {
1086 struct ide_internal * ide = (struct ide_internal *)(dev->private_data);
1087 struct v3_pci_bar bars[6];
1088 struct pci_device * pci_dev = NULL;
1091 for (i = 0; i < 2; i++) {
1092 init_channel(&(ide->channels[i]));
1094 // JRL: this is a terrible hack...
1095 ide->channels[i].irq = PRI_DEFAULT_IRQ + i;
1097 for (j = 0; j < 6; j++) {
1098 bars[j].type = PCI_BAR_NONE;
1102 bars[4].type = PCI_BAR_IO;
1103 bars[4].default_base_port = PRI_DEFAULT_DMA_PORT + (i * 0x8);
1104 bars[4].num_ports = 8;
1107 bars[4].io_read = read_pri_dma_port;
1108 bars[4].io_write = write_pri_dma_port;
1110 bars[4].io_read = read_sec_dma_port;
1111 bars[4].io_write = write_sec_dma_port;
1114 pci_dev = v3_pci_register_device(ide->pci, PCI_STD_DEVICE, 0, "V3_IDE", -1, bars,
1115 pci_config_update, NULL, NULL, dev);
1117 if (pci_dev == NULL) {
1118 PrintError("Failed to register IDE BUS %d with PCI\n", i);
1122 ide->channels[i].pci_dev = pci_dev;
1124 pci_dev->config_header.vendor_id = 0x1095;
1125 pci_dev->config_header.device_id = 0x0646;
1126 pci_dev->config_header.revision = 0x8f07;
1127 pci_dev->config_header.subclass = 0x01;
1128 pci_dev->config_header.class = 0x01;
1130 pci_dev->config_header.intr_line = PRI_DEFAULT_IRQ + i;
1131 pci_dev->config_header.intr_pin = 1;
1136 /* Register PIIX3 Busmaster PCI device */
1137 for (j = 0; j < 6; j++) {
1138 bars[j].type = PCI_BAR_NONE;
1141 pci_dev = v3_pci_register_device(ide->pci, PCI_STD_DEVICE, 0, "PIIX3 IDE", -1, bars,
1142 NULL, NULL, NULL, dev);
1145 ide->busmaster_pci = pci_dev;
1147 pci_dev->config_header.vendor_id = 0x8086;
1148 pci_dev->config_header.device_id = 0x7010;
1149 pci_dev->config_header.revision = 0x80;
1150 pci_dev->config_header.subclass = 0x01;
1151 pci_dev->config_header.class = 0x01;
1159 static int init_ide(struct vm_device * dev) {
1160 //struct ide_internal * ide = (struct ide_internal *)(dev->private_data);
1162 PrintDebug("IDE: Initializing IDE\n");
1164 if (init_ide_state(dev) == -1) {
1165 PrintError("Failed to initialize IDE state\n");
1170 v3_dev_hook_io(dev, PRI_DATA_PORT,
1171 &ide_read_data_port, &write_data_port);
1172 v3_dev_hook_io(dev, PRI_FEATURES_PORT,
1173 &read_port_std, &write_port_std);
1174 v3_dev_hook_io(dev, PRI_SECT_CNT_PORT,
1175 &read_port_std, &write_port_std);
1176 v3_dev_hook_io(dev, PRI_SECT_NUM_PORT,
1177 &read_port_std, &write_port_std);
1178 v3_dev_hook_io(dev, PRI_CYL_LOW_PORT,
1179 &read_port_std, &write_port_std);
1180 v3_dev_hook_io(dev, PRI_CYL_HIGH_PORT,
1181 &read_port_std, &write_port_std);
1182 v3_dev_hook_io(dev, PRI_DRV_SEL_PORT,
1183 &read_port_std, &write_port_std);
1184 v3_dev_hook_io(dev, PRI_CMD_PORT,
1185 &read_port_std, &write_cmd_port);
1187 v3_dev_hook_io(dev, SEC_DATA_PORT,
1188 &ide_read_data_port, &write_data_port);
1189 v3_dev_hook_io(dev, SEC_FEATURES_PORT,
1190 &read_port_std, &write_port_std);
1191 v3_dev_hook_io(dev, SEC_SECT_CNT_PORT,
1192 &read_port_std, &write_port_std);
1193 v3_dev_hook_io(dev, SEC_SECT_NUM_PORT,
1194 &read_port_std, &write_port_std);
1195 v3_dev_hook_io(dev, SEC_CYL_LOW_PORT,
1196 &read_port_std, &write_port_std);
1197 v3_dev_hook_io(dev, SEC_CYL_HIGH_PORT,
1198 &read_port_std, &write_port_std);
1199 v3_dev_hook_io(dev, SEC_DRV_SEL_PORT,
1200 &read_port_std, &write_port_std);
1201 v3_dev_hook_io(dev, SEC_CMD_PORT,
1202 &read_port_std, &write_cmd_port);
1205 v3_dev_hook_io(dev, PRI_CTRL_PORT,
1206 &read_port_std, &write_port_std);
1208 v3_dev_hook_io(dev, SEC_CTRL_PORT,
1209 &read_port_std, &write_port_std);
1212 v3_dev_hook_io(dev, SEC_ADDR_REG_PORT,
1213 &read_port_std, &write_port_std);
1215 v3_dev_hook_io(dev, PRI_ADDR_REG_PORT,
1216 &read_port_std, &write_port_std);
1222 static int deinit_ide(struct vm_device * dev) {
1223 // unhook io ports....
1224 // deregister from PCI?
1229 static struct vm_device_ops dev_ops = {
1231 .deinit = deinit_ide,
1238 struct vm_device * v3_create_ide(struct vm_device * pci) {
1239 struct ide_internal * ide = (struct ide_internal *)V3_Malloc(sizeof(struct ide_internal));
1240 struct vm_device * device = v3_create_device("IDE", &dev_ops, ide);
1244 PrintDebug("IDE: Creating IDE bus x 2\n");
1253 int v3_ide_register_cdrom(struct vm_device * ide_dev,
1257 struct v3_ide_cd_ops * ops,
1258 void * private_data) {
1260 struct ide_internal * ide = (struct ide_internal *)(ide_dev->private_data);
1261 struct ide_channel * channel = NULL;
1262 struct ide_drive * drive = NULL;
1264 V3_ASSERT((bus_num >= 0) && (bus_num < 2));
1265 V3_ASSERT((drive_num >= 0) && (drive_num < 2));
1267 channel = &(ide->channels[bus_num]);
1268 drive = &(channel->drives[drive_num]);
1270 if (drive->drive_type != IDE_NONE) {
1271 PrintError("Device slot (bus=%d, drive=%d) already occupied\n", bus_num, drive_num);
1275 strncpy(drive->model, dev_name, sizeof(drive->model) - 1);
1277 while (strlen((char *)(drive->model)) < 40) {
1278 strcat((char*)(drive->model), " ");
1282 drive->drive_type = IDE_CDROM;
1284 drive->cd_ops = ops;
1286 drive->private_data = private_data;
1292 int v3_ide_register_harddisk(struct vm_device * ide_dev,
1296 struct v3_ide_hd_ops * ops,
1297 void * private_data) {
1299 struct ide_internal * ide = (struct ide_internal *)(ide_dev->private_data);
1300 struct ide_channel * channel = NULL;
1301 struct ide_drive * drive = NULL;
1303 V3_ASSERT((bus_num >= 0) && (bus_num < 2));
1304 V3_ASSERT((drive_num >= 0) && (drive_num < 2));
1306 channel = &(ide->channels[bus_num]);
1307 drive = &(channel->drives[drive_num]);
1309 if (drive->drive_type != IDE_NONE) {
1310 PrintError("Device slot (bus=%d, drive=%d) already occupied\n", bus_num, drive_num);
1314 strncpy(drive->model, dev_name, sizeof(drive->model) - 1);
1316 drive->drive_type = IDE_DISK;
1318 drive->hd_ops = ops;
1320 drive->private_data = private_data;