2 * This file is part of the Palacios Virtual Machine Monitor developed
3 * by the V3VEE Project with funding from the United States National
4 * Science Foundation and the Department of Energy.
6 * The V3VEE Project is a joint project between Northwestern University
7 * and the University of New Mexico. You can find out more at
10 * Copyright (c) 2008, Jack Lange <jarusl@cs.northwestern.edu>
11 * Copyright (c) 2008, The V3VEE Project <http://www.v3vee.org>
12 * All rights reserved.
14 * Author: Jack Lange <jarusl@cs.northwestern.edu>
16 * This is free software. You are permitted to use,
17 * redistribute, and modify it as specified in the file "V3VEE_LICENSE".
20 #include <palacios/vmm.h>
21 #include <palacios/vm_guest_mem.h>
22 #include <devices/ide.h>
23 #include <devices/pci.h>
24 #include <devices/southbridge.h>
25 #include "ide-types.h"
26 #include "atapi-types.h"
30 #define PrintDebug(fmt, args...)
33 #define PRI_DEFAULT_IRQ 14
34 #define SEC_DEFAULT_IRQ 15
37 #define PRI_DATA_PORT 0x1f0
38 #define PRI_FEATURES_PORT 0x1f1
39 #define PRI_SECT_CNT_PORT 0x1f2
40 #define PRI_SECT_NUM_PORT 0x1f3
41 #define PRI_CYL_LOW_PORT 0x1f4
42 #define PRI_CYL_HIGH_PORT 0x1f5
43 #define PRI_DRV_SEL_PORT 0x1f6
44 #define PRI_CMD_PORT 0x1f7
45 #define PRI_CTRL_PORT 0x3f6
46 #define PRI_ADDR_REG_PORT 0x3f7
48 #define SEC_DATA_PORT 0x170
49 #define SEC_FEATURES_PORT 0x171
50 #define SEC_SECT_CNT_PORT 0x172
51 #define SEC_SECT_NUM_PORT 0x173
52 #define SEC_CYL_LOW_PORT 0x174
53 #define SEC_CYL_HIGH_PORT 0x175
54 #define SEC_DRV_SEL_PORT 0x176
55 #define SEC_CMD_PORT 0x177
56 #define SEC_CTRL_PORT 0x376
57 #define SEC_ADDR_REG_PORT 0x377
60 #define PRI_DEFAULT_DMA_PORT 0xc000
61 #define SEC_DEFAULT_DMA_PORT 0xc008
63 #define DATA_BUFFER_SIZE 2048
65 static const char * ide_pri_port_strs[] = {"PRI_DATA", "PRI_FEATURES", "PRI_SECT_CNT", "PRI_SECT_NUM",
66 "PRI_CYL_LOW", "PRI_CYL_HIGH", "PRI_DRV_SEL", "PRI_CMD",
67 "PRI_CTRL", "PRI_ADDR_REG"};
70 static const char * ide_sec_port_strs[] = {"SEC_DATA", "SEC_FEATURES", "SEC_SECT_CNT", "SEC_SECT_NUM",
71 "SEC_CYL_LOW", "SEC_CYL_HIGH", "SEC_DRV_SEL", "SEC_CMD",
72 "SEC_CTRL", "SEC_ADDR_REG"};
74 static const char * ide_dma_port_strs[] = {"DMA_CMD", NULL, "DMA_STATUS", NULL,
75 "DMA_PRD0", "DMA_PRD1", "DMA_PRD2", "DMA_PRD3"};
79 static inline const char * io_port_to_str(uint16_t port) {
80 if ((port >= PRI_DATA_PORT) && (port <= PRI_CMD_PORT)) {
81 return ide_pri_port_strs[port - PRI_DATA_PORT];
82 } else if ((port >= SEC_DATA_PORT) && (port <= SEC_CMD_PORT)) {
83 return ide_sec_port_strs[port - SEC_DATA_PORT];
84 } else if ((port == PRI_CTRL_PORT) || (port == PRI_ADDR_REG_PORT)) {
85 return ide_pri_port_strs[port - PRI_CTRL_PORT + 8];
86 } else if ((port == SEC_CTRL_PORT) || (port == SEC_ADDR_REG_PORT)) {
87 return ide_sec_port_strs[port - SEC_CTRL_PORT + 8];
93 static inline const char * dma_port_to_str(uint16_t port) {
94 return ide_dma_port_strs[port & 0x7];
98 static const char * ide_dev_type_strs[] = {"NONE", "HARDDISK", "CDROM" };
101 static inline const char * device_type_to_str(v3_ide_dev_type_t type) {
106 return ide_dev_type_strs[type];
111 struct ide_cd_state {
112 struct atapi_sense_data sense;
115 struct atapi_error_recovery err_recovery;
118 struct ide_hd_state {
121 /* this is the multiple sector transfer size as configured for read/write multiple sectors*/
122 uint_t mult_sector_num;
124 /* This is the current op sector size:
125 * for multiple sector ops this equals mult_sector_num
126 * for standard ops this equals 1
128 uint_t cur_sector_num;
134 v3_ide_dev_type_t drive_type;
137 struct v3_ide_cd_ops * cd_ops;
138 struct v3_ide_hd_ops * hd_ops;
143 struct ide_cd_state cd_state;
144 struct ide_hd_state hd_state;
149 // Where we are in the data transfer
150 uint_t transfer_index;
152 // the length of a transfer
153 // calculated for easy access
154 uint_t transfer_length;
156 uint64_t current_lba;
158 // We have a local data buffer that we use for IO port accesses
159 uint8_t data_buf[DATA_BUFFER_SIZE];
163 uint32_t num_cylinders;
165 uint32_t num_sectors;
170 uint8_t sector_count; // 0x1f2,0x172
171 struct atapi_irq_flags irq_flags;
172 } __attribute__((packed));
175 uint8_t sector_num; // 0x1f3,0x173
177 } __attribute__((packed));
184 uint8_t cylinder_low; // 0x1f4,0x174
185 uint8_t cylinder_high; // 0x1f5,0x175
186 } __attribute__((packed));
191 } __attribute__((packed));
194 // The transfer length requested by the CPU
196 } __attribute__((packed));
203 struct ide_drive drives[2];
206 struct ide_error_reg error_reg; // [read] 0x1f1,0x171
208 struct ide_features_reg features;
210 struct ide_drive_head_reg drive_head; // 0x1f6,0x176
212 struct ide_status_reg status; // [read] 0x1f7,0x177
213 uint8_t cmd_reg; // [write] 0x1f7,0x177
215 int irq; // this is temporary until we add PCI support
218 struct ide_ctrl_reg ctrl_reg; // [write] 0x3f6,0x376
220 struct ide_dma_cmd_reg dma_cmd;
221 struct ide_dma_status_reg dma_status;
222 uint32_t dma_prd_addr;
223 uint_t dma_tbl_index;
228 struct ide_internal {
229 struct ide_channel channels[2];
231 struct v3_southbridge * southbridge;
232 struct vm_device * pci_bus;
234 struct pci_device * ide_pci;
241 /* Utility functions */
243 static inline uint16_t be_to_le_16(const uint16_t val) {
244 uint8_t * buf = (uint8_t *)&val;
245 return (buf[0] << 8) | (buf[1]) ;
248 static inline uint16_t le_to_be_16(const uint16_t val) {
249 return be_to_le_16(val);
253 static inline uint32_t be_to_le_32(const uint32_t val) {
254 uint8_t * buf = (uint8_t *)&val;
255 return (buf[0] << 24) | (buf[1] << 16) | (buf[2] << 8) | buf[3];
258 static inline uint32_t le_to_be_32(const uint32_t val) {
259 return be_to_le_32(val);
263 static inline int get_channel_index(ushort_t port) {
264 if (((port & 0xfff8) == 0x1f0) ||
265 ((port & 0xfffe) == 0x3f6) ||
266 ((port & 0xfff8) == 0xc000)) {
268 } else if (((port & 0xfff8) == 0x170) ||
269 ((port & 0xfffe) == 0x376) ||
270 ((port & 0xfff8) == 0xc008)) {
277 static inline struct ide_channel * get_selected_channel(struct ide_internal * ide, ushort_t port) {
278 int channel_idx = get_channel_index(port);
279 return &(ide->channels[channel_idx]);
282 static inline struct ide_drive * get_selected_drive(struct ide_channel * channel) {
283 return &(channel->drives[channel->drive_head.drive_sel]);
287 static inline int is_lba_enabled(struct ide_channel * channel) {
288 return channel->drive_head.lba_mode;
293 static void ide_raise_irq(struct vm_device * dev, struct ide_channel * channel) {
294 if (channel->ctrl_reg.irq_disable == 0) {
295 PrintDebug("Raising IDE Interrupt %d\n", channel->irq);
296 channel->dma_status.int_gen = 1;
297 v3_raise_irq(dev->vm, channel->irq);
302 static void drive_reset(struct ide_drive * drive) {
303 drive->sector_count = 0x01;
304 drive->sector_num = 0x01;
306 PrintDebug("Resetting drive %s\n", drive->model);
308 if (drive->drive_type == IDE_CDROM) {
309 drive->cylinder = 0xeb14;
311 drive->cylinder = 0x0000;
312 //drive->hd_state.accessed = 0;
316 memset(drive->data_buf, 0, sizeof(drive->data_buf));
317 drive->transfer_index = 0;
319 // Send the reset signal to the connected device callbacks
320 // channel->drives[0].reset();
321 // channel->drives[1].reset();
324 static void channel_reset(struct ide_channel * channel) {
326 // set busy and seek complete flags
327 channel->status.val = 0x90;
330 channel->error_reg.val = 0x01;
333 channel->cmd_reg = 0x00;
335 channel->ctrl_reg.irq_disable = 0;
338 static void channel_reset_complete(struct ide_channel * channel) {
339 channel->status.busy = 0;
340 channel->status.ready = 1;
342 channel->drive_head.head_num = 0;
344 drive_reset(&(channel->drives[0]));
345 drive_reset(&(channel->drives[1]));
349 static void ide_abort_command(struct vm_device * dev, struct ide_channel * channel) {
350 channel->status.val = 0x41; // Error + ready
351 channel->error_reg.val = 0x04; // No idea...
353 ide_raise_irq(dev, channel);
361 /* ATAPI functions */
370 static int dma_read(struct vm_device * dev, struct ide_channel * channel) {
371 struct ide_drive * drive = get_selected_drive(channel);
372 // This is at top level scope to do the EOT test at the end
373 struct ide_dma_prd prd_entry;
375 // Read in the data buffer....
376 // Read a sector/block at a time until the prd entry is full.
378 if (drive->drive_type == IDE_DISK) {
379 uint_t bytes_left = drive->transfer_length;
381 // Loop through the disk data
382 while (bytes_left > 0) {
384 uint32_t prd_entry_addr = channel->dma_prd_addr + (sizeof(struct ide_dma_prd) * channel->dma_tbl_index);
385 uint_t prd_bytes_left = 0;
386 uint_t prd_offset = 0;
389 PrintDebug("PRD table address = %x\n", channel->dma_prd_addr);
391 ret = read_guest_pa_memory(dev->vm, prd_entry_addr, sizeof(struct ide_dma_prd), (void *)&prd_entry);
393 if (ret != sizeof(struct ide_dma_prd)) {
394 PrintError("Could not read PRD\n");
398 PrintDebug("PRD Addr: %x, PDR Len: %d, EOT: %d\n", prd_entry.base_addr, prd_entry.size, prd_entry.end_of_table);
400 // loop through the PRD data....
402 prd_bytes_left = prd_entry.size;
405 while (prd_bytes_left > 0) {
406 uint_t bytes_to_write = (prd_bytes_left > IDE_SECTOR_SIZE) ? IDE_SECTOR_SIZE : prd_bytes_left;
409 if (ata_read(dev, channel, drive->data_buf, 1) == -1) {
410 PrintError("Failed to read next disk sector\n");
414 drive->current_lba++;
416 ret = write_guest_pa_memory(dev->vm, prd_entry.base_addr + prd_offset, bytes_to_write, drive->data_buf);
418 if (ret != bytes_to_write) {
419 PrintError("Failed to copy data into guest memory... (ret=%d)\n", ret);
423 drive->transfer_index += ret;
424 prd_bytes_left -= ret;
429 channel->dma_tbl_index++;
431 if (drive->transfer_index % IDE_SECTOR_SIZE) {
432 PrintError("We currently don't handle sectors that span PRD descriptors\n");
436 if ((prd_entry.end_of_table == 1) && (bytes_left > 0)) {
437 PrintError("DMA table not large enough for data transfer...\n");
443 } else if (drive->drive_type == IDE_CDROM) {
444 PrintError("CDROM DMA not supported\n");
449 drive->irq_flags.io_dir = 1;
450 drive->irq_flags.c_d = 1;
451 drive->irq_flags.rel = 0;
455 // Update to the next PRD entry
459 if (prd_entry.end_of_table) {
460 channel->status.busy = 0;
461 channel->status.ready = 1;
462 channel->status.data_req = 0;
463 channel->status.error = 0;
464 channel->status.seek_complete = 1;
466 channel->dma_status.active = 0;
467 channel->dma_status.err = 0;
470 ide_raise_irq(dev, channel);
476 static int dma_write(struct vm_device * dev, struct ide_channel * channel) {
478 PrintError("DMA writes currently not supported\n");
484 #define DMA_CMD_PORT 0x00
485 #define DMA_STATUS_PORT 0x02
486 #define DMA_PRD_PORT0 0x04
487 #define DMA_PRD_PORT1 0x05
488 #define DMA_PRD_PORT2 0x06
489 #define DMA_PRD_PORT3 0x07
491 #define DMA_CHANNEL_FLAG 0x08
493 static int write_dma_port(ushort_t port, void * src, uint_t length, struct vm_device * dev) {
494 struct ide_internal * ide = (struct ide_internal *)(dev->private_data);
495 uint16_t port_offset = port & (DMA_CHANNEL_FLAG - 1);
496 uint_t channel_flag = (port & DMA_CHANNEL_FLAG) >> 3;
497 struct ide_channel * channel = &(ide->channels[channel_flag]);
499 PrintDebug("IDE: Writing DMA Port %x (%s) (val=%x) (len=%d) (channel=%d)\n",
500 port, dma_port_to_str(port_offset), *(uint32_t *)src, length, channel_flag);
502 switch (port_offset) {
504 channel->dma_cmd.val = *(uint8_t *)src;
506 if (channel->dma_cmd.start == 0) {
507 channel->dma_tbl_index = 0;
509 channel->dma_status.active = 1;
511 if (channel->dma_cmd.read == 1) {
513 if (dma_read(dev, channel) == -1) {
514 PrintError("Failed DMA Read\n");
519 if (dma_write(dev, channel) == -1) {
520 PrintError("Failed DMA Write\n");
525 channel->dma_cmd.val &= 0x09;
530 case DMA_STATUS_PORT: {
531 uint8_t val = *(uint8_t *)src;
534 PrintError("Invalid read length for DMA status port\n");
539 channel->dma_status.val = ((val & 0x60) |
540 (channel->dma_status.val & 0x01) |
541 (channel->dma_status.val & ~val & 0x06));
548 case DMA_PRD_PORT3: {
549 uint_t addr_index = port_offset & 0x3;
550 uint8_t * addr_buf = (uint8_t *)&(channel->dma_prd_addr);
553 if (addr_index + length > 4) {
554 PrintError("DMA Port space overrun port=%x len=%d\n", port_offset, length);
558 for (i = 0; i < length; i++) {
559 addr_buf[addr_index + i] = *((uint8_t *)src + i);
562 PrintDebug("Writing PRD Port %x (val=%x)\n", port_offset, channel->dma_prd_addr);
567 PrintError("IDE: Invalid DMA Port (%s)\n", dma_port_to_str(port_offset));
575 static int read_dma_port(ushort_t port, void * dst, uint_t length, struct vm_device * dev) {
576 struct ide_internal * ide = (struct ide_internal *)(dev->private_data);
577 uint16_t port_offset = port & (DMA_CHANNEL_FLAG - 1);
578 uint_t channel_flag = (port & DMA_CHANNEL_FLAG) >> 3;
579 struct ide_channel * channel = &(ide->channels[channel_flag]);
581 PrintDebug("Reading DMA port %d (%x) (channel=%d)\n", port, port, channel_flag);
583 switch (port_offset) {
585 *(uint8_t *)dst = channel->dma_cmd.val;
588 case DMA_STATUS_PORT:
590 PrintError("Invalid read length for DMA status port\n");
594 *(uint8_t *)dst = channel->dma_status.val;
600 case DMA_PRD_PORT3: {
601 uint_t addr_index = port_offset & 0x3;
602 uint8_t * addr_buf = (uint8_t *)&(channel->dma_prd_addr);
605 if (addr_index + length > 4) {
606 PrintError("DMA Port space overrun port=%x len=%d\n", port_offset, length);
610 for (i = 0; i < length; i++) {
611 *((uint8_t *)dst + i) = addr_buf[addr_index + i];
617 PrintError("IDE: Invalid DMA Port (%s)\n", dma_port_to_str(port_offset));
621 PrintDebug("\tval=%x (len=%d)\n", *(uint32_t *)dst, length);
628 static int write_cmd_port(ushort_t port, void * src, uint_t length, struct vm_device * dev) {
629 struct ide_internal * ide = (struct ide_internal *)(dev->private_data);
630 struct ide_channel * channel = get_selected_channel(ide, port);
631 struct ide_drive * drive = get_selected_drive(channel);
634 PrintError("Invalid Write Length on IDE command Port %x\n", port);
638 PrintDebug("IDE: Writing Command Port %x (%s) (val=%x)\n", port, io_port_to_str(port), *(uint8_t *)src);
640 channel->cmd_reg = *(uint8_t *)src;
642 switch (channel->cmd_reg) {
644 case 0xa1: // ATAPI Identify Device Packet
645 if (drive->drive_type != IDE_CDROM) {
648 // JRL: Should we abort here?
649 ide_abort_command(dev, channel);
652 atapi_identify_device(drive);
654 channel->error_reg.val = 0;
655 channel->status.val = 0x58; // ready, data_req, seek_complete
657 ide_raise_irq(dev, channel);
660 case 0xec: // Identify Device
661 if (drive->drive_type != IDE_DISK) {
664 // JRL: Should we abort here?
665 ide_abort_command(dev, channel);
667 ata_identify_device(drive);
669 channel->error_reg.val = 0;
670 channel->status.val = 0x58;
672 ide_raise_irq(dev, channel);
676 case 0xa0: // ATAPI Command Packet
677 if (drive->drive_type != IDE_CDROM) {
678 ide_abort_command(dev, channel);
681 drive->sector_count = 1;
683 channel->status.busy = 0;
684 channel->status.write_fault = 0;
685 channel->status.data_req = 1;
686 channel->status.error = 0;
688 // reset the data buffer...
689 drive->transfer_length = ATAPI_PACKET_SIZE;
690 drive->transfer_index = 0;
694 case 0x20: // Read Sectors with Retry
695 case 0x21: // Read Sectors without Retry
696 drive->hd_state.cur_sector_num = 1;
698 if (ata_read_sectors(dev, channel) == -1) {
699 PrintError("Error reading sectors\n");
704 case 0x24: // Read Sectors Extended
705 drive->hd_state.cur_sector_num = 1;
707 if (ata_read_sectors_ext(dev, channel) == -1) {
708 PrintError("Error reading extended sectors\n");
713 case 0xc8: // Read DMA with retry
714 case 0xc9: { // Read DMA
715 uint32_t sect_cnt = (drive->sector_count == 0) ? 256 : drive->sector_count;
717 if (ata_get_lba(dev, channel, &(drive->current_lba)) == -1) {
718 ide_abort_command(dev, channel);
722 drive->hd_state.cur_sector_num = 1;
724 drive->transfer_length = sect_cnt * IDE_SECTOR_SIZE;
725 drive->transfer_index = 0;
727 if (channel->dma_status.active == 1) {
729 if (dma_read(dev, channel) == -1) {
730 PrintError("Failed DMA Read\n");
736 case 0xef: // Set Features
737 // Prior to this the features register has been written to.
738 // This command tells the drive to check if the new value is supported (the value is drive specific)
739 // Common is that bit0=DMA enable
740 // If valid the drive raises an interrupt, if not it aborts.
742 // Do some checking here...
744 channel->status.busy = 0;
745 channel->status.write_fault = 0;
746 channel->status.error = 0;
747 channel->status.ready = 1;
748 channel->status.seek_complete = 1;
750 ide_raise_irq(dev, channel);
753 case 0x91: // Initialize Drive Parameters
754 case 0x10: // recalibrate?
755 channel->status.error = 0;
756 channel->status.ready = 1;
757 channel->status.seek_complete = 1;
758 ide_raise_irq(dev, channel);
760 case 0xc6: { // Set multiple mode (IDE Block mode)
761 // This makes the drive transfer multiple sectors before generating an interrupt
762 uint32_t tmp_sect_num = drive->sector_num; // GCC SUCKS
764 if (tmp_sect_num > MAX_MULT_SECTORS) {
765 ide_abort_command(dev, channel);
769 if (drive->sector_count == 0) {
770 drive->hd_state.mult_sector_num= 1;
772 drive->hd_state.mult_sector_num = drive->sector_count;
775 channel->status.ready = 1;
776 channel->status.error = 0;
778 ide_raise_irq(dev, channel);
782 case 0xc4: // read multiple sectors
783 drive->hd_state.cur_sector_num = drive->hd_state.mult_sector_num;
785 PrintError("Unimplemented IDE command (%x)\n", channel->cmd_reg);
793 static int write_data_port(ushort_t port, void * src, uint_t length, struct vm_device * dev) {
794 struct ide_internal * ide = (struct ide_internal *)(dev->private_data);
795 struct ide_channel * channel = get_selected_channel(ide, port);
796 struct ide_drive * drive = get_selected_drive(channel);
798 // PrintDebug("IDE: Writing Data Port %x (val=%x, len=%d)\n",
799 // port, *(uint32_t *)src, length);
801 memcpy(drive->data_buf + drive->transfer_index, src, length);
802 drive->transfer_index += length;
804 // Transfer is complete, dispatch the command
805 if (drive->transfer_index >= drive->transfer_length) {
806 switch (channel->cmd_reg) {
807 case 0x30: // Write Sectors
808 PrintError("Writing Data not yet implemented\n");
811 case 0xa0: // ATAPI packet command
812 if (atapi_handle_packet(dev, channel) == -1) {
813 PrintError("Error handling ATAPI packet\n");
818 PrintError("Unhandld IDE Command %x\n", channel->cmd_reg);
827 static int read_hd_data(uint8_t * dst, uint_t length, struct vm_device * dev, struct ide_channel * channel) {
828 struct ide_drive * drive = get_selected_drive(channel);
829 int data_offset = drive->transfer_index % IDE_SECTOR_SIZE;
833 if (drive->transfer_index >= drive->transfer_length) {
834 PrintError("Buffer overrun... (xfer_len=%d) (cur_idx=%x) (post_idx=%d)\n",
835 drive->transfer_length, drive->transfer_index,
836 drive->transfer_index + length);
841 if ((data_offset == 0) && (drive->transfer_index > 0)) {
842 drive->current_lba++;
844 if (ata_read(dev, channel, drive->data_buf, 1) == -1) {
845 PrintError("Could not read next disk sector\n");
851 PrintDebug("Reading HD Data (Val=%x), (len=%d) (offset=%d)\n",
852 *(uint32_t *)(drive->data_buf + data_offset),
853 length, data_offset);
855 memcpy(dst, drive->data_buf + data_offset, length);
857 drive->transfer_index += length;
860 /* This is the trigger for interrupt injection.
861 * For read single sector commands we interrupt after every sector
862 * For multi sector reads we interrupt only at end of the cluster size (mult_sector_num)
863 * cur_sector_num is configured depending on the operation we are currently running
864 * We also trigger an interrupt if this is the last byte to transfer, regardless of sector count
866 if (((drive->transfer_index % (IDE_SECTOR_SIZE * drive->hd_state.cur_sector_num)) == 0) ||
867 (drive->transfer_index == drive->transfer_length)) {
868 if (drive->transfer_index < drive->transfer_length) {
869 // An increment is complete, but there is still more data to be transferred...
870 PrintDebug("Integral Complete, still transferring more sectors\n");
871 channel->status.data_req = 1;
873 drive->irq_flags.c_d = 0;
875 PrintDebug("Final Sector Transferred\n");
876 // This was the final read of the request
877 channel->status.data_req = 0;
880 drive->irq_flags.c_d = 1;
881 drive->irq_flags.rel = 0;
884 channel->status.ready = 1;
885 drive->irq_flags.io_dir = 1;
886 channel->status.busy = 0;
888 ide_raise_irq(dev, channel);
897 static int read_cd_data(uint8_t * dst, uint_t length, struct vm_device * dev, struct ide_channel * channel) {
898 struct ide_drive * drive = get_selected_drive(channel);
899 int data_offset = drive->transfer_index % ATAPI_BLOCK_SIZE;
900 int req_offset = drive->transfer_index % drive->req_len;
902 if (drive->cd_state.atapi_cmd != 0x28) {
903 PrintDebug("IDE: Reading CD Data (len=%d) (req_len=%d)\n", length, drive->req_len);
906 if (drive->transfer_index >= drive->transfer_length) {
907 PrintError("Buffer Overrun... (xfer_len=%d) (cur_idx=%d) (post_idx=%d)\n",
908 drive->transfer_length, drive->transfer_index,
909 drive->transfer_index + length);
915 if ((data_offset == 0) && (drive->transfer_index > 0)) {
916 if (atapi_update_data_buf(dev, channel) == -1) {
917 PrintError("Could not update CDROM data buffer\n");
922 memcpy(dst, drive->data_buf + data_offset, length);
924 drive->transfer_index += length;
927 // Should the req_offset be recalculated here?????
928 if ((req_offset == 0) && (drive->transfer_index > 0)) {
929 if (drive->transfer_index < drive->transfer_length) {
930 // An increment is complete, but there is still more data to be transferred...
932 channel->status.data_req = 1;
934 drive->irq_flags.c_d = 0;
936 // Update the request length in the cylinder regs
937 if (atapi_update_req_len(dev, channel, drive->transfer_length - drive->transfer_index) == -1) {
938 PrintError("Could not update request length after completed increment\n");
942 // This was the final read of the request
943 channel->status.data_req = 0;
944 channel->status.ready = 1;
946 drive->irq_flags.c_d = 1;
947 drive->irq_flags.rel = 0;
950 drive->irq_flags.io_dir = 1;
951 channel->status.busy = 0;
953 ide_raise_irq(dev, channel);
960 static int read_drive_id(uint8_t * dst, uint_t length, struct vm_device * dev, struct ide_channel * channel) {
961 struct ide_drive * drive = get_selected_drive(channel);
963 channel->status.busy = 0;
964 channel->status.ready = 1;
965 channel->status.write_fault = 0;
966 channel->status.seek_complete = 1;
967 channel->status.corrected = 0;
968 channel->status.error = 0;
971 memcpy(dst, drive->data_buf + drive->transfer_index, length);
972 drive->transfer_index += length;
974 if (drive->transfer_index >= drive->transfer_length) {
975 channel->status.data_req = 0;
982 static int ide_read_data_port(ushort_t port, void * dst, uint_t length, struct vm_device * dev) {
983 struct ide_internal * ide = (struct ide_internal *)(dev->private_data);
984 struct ide_channel * channel = get_selected_channel(ide, port);
985 struct ide_drive * drive = get_selected_drive(channel);
987 // PrintDebug("IDE: Reading Data Port %x (len=%d)\n", port, length);
989 if ((channel->cmd_reg == 0xec) ||
990 (channel->cmd_reg == 0xa1)) {
991 return read_drive_id((uint8_t *)dst, length, dev, channel);
994 if (drive->drive_type == IDE_CDROM) {
995 if (read_cd_data((uint8_t *)dst, length, dev, channel) == -1) {
996 PrintError("IDE: Could not read CD Data\n");
999 } else if (drive->drive_type == IDE_DISK) {
1000 if (read_hd_data((uint8_t *)dst, length, dev, channel) == -1) {
1001 PrintError("IDE: Could not read HD Data\n");
1005 memset((uint8_t *)dst, 0, length);
1011 static int write_port_std(ushort_t port, void * src, uint_t length, struct vm_device * dev) {
1012 struct ide_internal * ide = (struct ide_internal *)(dev->private_data);
1013 struct ide_channel * channel = get_selected_channel(ide, port);
1014 struct ide_drive * drive = get_selected_drive(channel);
1017 PrintError("Invalid Write length on IDE port %x\n", port);
1021 PrintDebug("IDE: Writing Standard Port %x (%s) (val=%x)\n", port, io_port_to_str(port), *(uint8_t *)src);
1024 // reset and interrupt enable
1026 case SEC_CTRL_PORT: {
1027 struct ide_ctrl_reg * tmp_ctrl = (struct ide_ctrl_reg *)src;
1029 // only reset channel on a 0->1 reset bit transition
1030 if ((!channel->ctrl_reg.soft_reset) && (tmp_ctrl->soft_reset)) {
1031 channel_reset(channel);
1032 } else if ((channel->ctrl_reg.soft_reset) && (!tmp_ctrl->soft_reset)) {
1033 channel_reset_complete(channel);
1036 channel->ctrl_reg.val = tmp_ctrl->val;
1039 case PRI_FEATURES_PORT:
1040 case SEC_FEATURES_PORT:
1041 channel->features.val = *(uint8_t *)src;
1044 case PRI_SECT_CNT_PORT:
1045 case SEC_SECT_CNT_PORT:
1046 channel->drives[0].sector_count = *(uint8_t *)src;
1047 channel->drives[1].sector_count = *(uint8_t *)src;
1050 case PRI_SECT_NUM_PORT:
1051 case SEC_SECT_NUM_PORT:
1052 channel->drives[0].sector_num = *(uint8_t *)src;
1053 channel->drives[1].sector_num = *(uint8_t *)src;
1055 case PRI_CYL_LOW_PORT:
1056 case SEC_CYL_LOW_PORT:
1057 channel->drives[0].cylinder_low = *(uint8_t *)src;
1058 channel->drives[1].cylinder_low = *(uint8_t *)src;
1061 case PRI_CYL_HIGH_PORT:
1062 case SEC_CYL_HIGH_PORT:
1063 channel->drives[0].cylinder_high = *(uint8_t *)src;
1064 channel->drives[1].cylinder_high = *(uint8_t *)src;
1067 case PRI_DRV_SEL_PORT:
1068 case SEC_DRV_SEL_PORT: {
1069 channel->drive_head.val = *(uint8_t *)src;
1071 // make sure the reserved bits are ok..
1072 // JRL TODO: check with new ramdisk to make sure this is right...
1073 channel->drive_head.val |= 0xa0;
1075 drive = get_selected_drive(channel);
1077 // Selecting a non-present device is a no-no
1078 if (drive->drive_type == IDE_NONE) {
1079 PrintDebug("Attempting to select a non-present drive\n");
1080 channel->error_reg.abort = 1;
1081 channel->status.error = 1;
1087 PrintError("IDE: Write to unknown Port %x\n", port);
1094 static int read_port_std(ushort_t port, void * dst, uint_t length, struct vm_device * dev) {
1095 struct ide_internal * ide = (struct ide_internal *)(dev->private_data);
1096 struct ide_channel * channel = get_selected_channel(ide, port);
1097 struct ide_drive * drive = get_selected_drive(channel);
1100 PrintError("Invalid Read length on IDE port %x\n", port);
1104 PrintDebug("IDE: Reading Standard Port %x (%s)\n", port, io_port_to_str(port));
1106 if ((port == PRI_ADDR_REG_PORT) ||
1107 (port == SEC_ADDR_REG_PORT)) {
1108 // unused, return 0xff
1109 *(uint8_t *)dst = 0xff;
1114 // if no drive is present just return 0 + reserved bits
1115 if (drive->drive_type == IDE_NONE) {
1116 if ((port == PRI_DRV_SEL_PORT) ||
1117 (port == SEC_DRV_SEL_PORT)) {
1118 *(uint8_t *)dst = 0xa0;
1120 *(uint8_t *)dst = 0;
1128 // This is really the error register.
1129 case PRI_FEATURES_PORT:
1130 case SEC_FEATURES_PORT:
1131 *(uint8_t *)dst = channel->error_reg.val;
1134 case PRI_SECT_CNT_PORT:
1135 case SEC_SECT_CNT_PORT:
1136 *(uint8_t *)dst = drive->sector_count;
1139 case PRI_SECT_NUM_PORT:
1140 case SEC_SECT_NUM_PORT:
1141 *(uint8_t *)dst = drive->sector_num;
1144 case PRI_CYL_LOW_PORT:
1145 case SEC_CYL_LOW_PORT:
1146 *(uint8_t *)dst = drive->cylinder_low;
1150 case PRI_CYL_HIGH_PORT:
1151 case SEC_CYL_HIGH_PORT:
1152 *(uint8_t *)dst = drive->cylinder_high;
1155 case PRI_DRV_SEL_PORT:
1156 case SEC_DRV_SEL_PORT: // hard disk drive and head register 0x1f6
1157 *(uint8_t *)dst = channel->drive_head.val;
1164 // Something about lowering interrupts here....
1165 *(uint8_t *)dst = channel->status.val;
1169 PrintError("Invalid Port: %x\n", port);
1173 PrintDebug("\tVal=%x\n", *(uint8_t *)dst);
1180 static void init_drive(struct ide_drive * drive) {
1182 drive->sector_count = 0x01;
1183 drive->sector_num = 0x01;
1184 drive->cylinder = 0x0000;
1186 drive->drive_type = IDE_NONE;
1188 memset(drive->model, 0, sizeof(drive->model));
1190 drive->transfer_index = 0;
1191 drive->transfer_length = 0;
1192 memset(drive->data_buf, 0, sizeof(drive->data_buf));
1194 drive->num_cylinders = 0;
1195 drive->num_heads = 0;
1196 drive->num_sectors = 0;
1199 drive->private_data = NULL;
1200 drive->cd_ops = NULL;
1203 static void init_channel(struct ide_channel * channel) {
1206 channel->error_reg.val = 0x01;
1207 channel->drive_head.val = 0x00;
1208 channel->status.val = 0x00;
1209 channel->cmd_reg = 0x00;
1210 channel->ctrl_reg.val = 0x08;
1213 channel->dma_cmd.val = 0;
1214 channel->dma_status.val = 0;
1215 channel->dma_prd_addr = 0;
1216 channel->dma_tbl_index = 0;
1218 for (i = 0; i < 2; i++) {
1219 init_drive(&(channel->drives[i]));
1225 static int pci_config_update(struct pci_device * pci_dev, uint_t reg_num, int length) {
1226 PrintDebug("PCI Config Update\n");
1227 PrintDebug("\t\tInterupt register (Dev=%s), irq=%d\n", pci_dev->name, pci_dev->config_header.intr_line);
1232 static int init_ide_state(struct vm_device * dev) {
1233 struct ide_internal * ide = (struct ide_internal *)(dev->private_data);
1237 * Check if the PIIX 3 actually represents both IDE channels in a single PCI entry
1240 for (i = 0; i < 1; i++) {
1241 init_channel(&(ide->channels[i]));
1243 // JRL: this is a terrible hack...
1244 ide->channels[i].irq = PRI_DEFAULT_IRQ + i;
1253 static int init_ide(struct vm_device * dev) {
1254 struct ide_internal * ide = (struct ide_internal *)(dev->private_data);
1256 PrintDebug("IDE: Initializing IDE\n");
1258 if (init_ide_state(dev) == -1) {
1259 PrintError("Failed to initialize IDE state\n");
1264 v3_dev_hook_io(dev, PRI_DATA_PORT,
1265 &ide_read_data_port, &write_data_port);
1266 v3_dev_hook_io(dev, PRI_FEATURES_PORT,
1267 &read_port_std, &write_port_std);
1268 v3_dev_hook_io(dev, PRI_SECT_CNT_PORT,
1269 &read_port_std, &write_port_std);
1270 v3_dev_hook_io(dev, PRI_SECT_NUM_PORT,
1271 &read_port_std, &write_port_std);
1272 v3_dev_hook_io(dev, PRI_CYL_LOW_PORT,
1273 &read_port_std, &write_port_std);
1274 v3_dev_hook_io(dev, PRI_CYL_HIGH_PORT,
1275 &read_port_std, &write_port_std);
1276 v3_dev_hook_io(dev, PRI_DRV_SEL_PORT,
1277 &read_port_std, &write_port_std);
1278 v3_dev_hook_io(dev, PRI_CMD_PORT,
1279 &read_port_std, &write_cmd_port);
1281 v3_dev_hook_io(dev, SEC_DATA_PORT,
1282 &ide_read_data_port, &write_data_port);
1283 v3_dev_hook_io(dev, SEC_FEATURES_PORT,
1284 &read_port_std, &write_port_std);
1285 v3_dev_hook_io(dev, SEC_SECT_CNT_PORT,
1286 &read_port_std, &write_port_std);
1287 v3_dev_hook_io(dev, SEC_SECT_NUM_PORT,
1288 &read_port_std, &write_port_std);
1289 v3_dev_hook_io(dev, SEC_CYL_LOW_PORT,
1290 &read_port_std, &write_port_std);
1291 v3_dev_hook_io(dev, SEC_CYL_HIGH_PORT,
1292 &read_port_std, &write_port_std);
1293 v3_dev_hook_io(dev, SEC_DRV_SEL_PORT,
1294 &read_port_std, &write_port_std);
1295 v3_dev_hook_io(dev, SEC_CMD_PORT,
1296 &read_port_std, &write_cmd_port);
1299 v3_dev_hook_io(dev, PRI_CTRL_PORT,
1300 &read_port_std, &write_port_std);
1302 v3_dev_hook_io(dev, SEC_CTRL_PORT,
1303 &read_port_std, &write_port_std);
1306 v3_dev_hook_io(dev, SEC_ADDR_REG_PORT,
1307 &read_port_std, &write_port_std);
1309 v3_dev_hook_io(dev, PRI_ADDR_REG_PORT,
1310 &read_port_std, &write_port_std);
1316 struct v3_pci_bar bars[6];
1317 struct v3_southbridge * southbridge = (struct v3_southbridge *)(ide->southbridge);
1318 struct pci_device * sb_pci = (struct pci_device *)(southbridge->southbridge_pci);
1319 struct pci_device * pci_dev = NULL;
1322 for (i = 0; i < 6; i++) {
1323 bars[i].type = PCI_BAR_NONE;
1326 bars[4].type = PCI_BAR_IO;
1327 bars[4].default_base_port = PRI_DEFAULT_DMA_PORT;
1328 bars[4].num_ports = 16;
1330 bars[4].io_read = read_dma_port;
1331 bars[4].io_write = write_dma_port;
1333 pci_dev = v3_pci_register_device(ide->pci_bus, PCI_STD_DEVICE, 0, sb_pci->dev_num, 1,
1335 pci_config_update, NULL, NULL, dev);
1337 if (pci_dev == NULL) {
1338 PrintError("Failed to register IDE BUS %d with PCI\n", i);
1342 /* This is for CMD646 devices
1343 pci_dev->config_header.vendor_id = 0x1095;
1344 pci_dev->config_header.device_id = 0x0646;
1345 pci_dev->config_header.revision = 0x8f07;
1348 pci_dev->config_header.vendor_id = 0x8086;
1349 pci_dev->config_header.device_id = 0x7010;
1350 pci_dev->config_header.revision = 0x00;
1352 pci_dev->config_header.prog_if = 0x80;
1353 pci_dev->config_header.subclass = 0x01;
1354 pci_dev->config_header.class = 0x01;
1356 pci_dev->config_header.command = 0;
1357 pci_dev->config_header.status = 0x0280;
1359 ide->ide_pci = pci_dev;
1368 static int deinit_ide(struct vm_device * dev) {
1369 // unhook io ports....
1370 // deregister from PCI?
1375 static struct vm_device_ops dev_ops = {
1377 .deinit = deinit_ide,
1384 struct vm_device * v3_create_ide(struct vm_device * pci_bus, struct vm_device * southbridge_dev) {
1385 struct ide_internal * ide = (struct ide_internal *)V3_Malloc(sizeof(struct ide_internal));
1386 struct vm_device * device = v3_create_device("IDE", &dev_ops, ide);
1388 ide->pci_bus = pci_bus;
1389 ide->southbridge = (struct v3_southbridge *)(southbridge_dev->private_data);
1391 PrintDebug("IDE: Creating IDE bus x 2\n");
1398 int v3_ide_get_geometry(struct vm_device * ide_dev, int channel_num, int drive_num,
1399 uint32_t * cylinders, uint32_t * heads, uint32_t * sectors) {
1401 struct ide_internal * ide = (struct ide_internal *)(ide_dev->private_data);
1402 struct ide_channel * channel = &(ide->channels[channel_num]);
1403 struct ide_drive * drive = &(channel->drives[drive_num]);
1405 if (drive->drive_type == IDE_NONE) {
1409 *cylinders = drive->num_cylinders;
1410 *heads = drive->num_heads;
1411 *sectors = drive->num_sectors;
1419 int v3_ide_register_cdrom(struct vm_device * ide_dev,
1423 struct v3_ide_cd_ops * ops,
1424 void * private_data) {
1426 struct ide_internal * ide = (struct ide_internal *)(ide_dev->private_data);
1427 struct ide_channel * channel = NULL;
1428 struct ide_drive * drive = NULL;
1430 V3_ASSERT((bus_num >= 0) && (bus_num < 2));
1431 V3_ASSERT((drive_num >= 0) && (drive_num < 2));
1433 channel = &(ide->channels[bus_num]);
1434 drive = &(channel->drives[drive_num]);
1436 if (drive->drive_type != IDE_NONE) {
1437 PrintError("Device slot (bus=%d, drive=%d) already occupied\n", bus_num, drive_num);
1441 strncpy(drive->model, dev_name, sizeof(drive->model) - 1);
1443 while (strlen((char *)(drive->model)) < 40) {
1444 strcat((char*)(drive->model), " ");
1448 drive->drive_type = IDE_CDROM;
1450 drive->cd_ops = ops;
1453 // Hardcode this for now, but its not a good idea....
1454 ide->ide_pci->config_space[0x41 + (bus_num * 2)] = 0x80;
1457 drive->private_data = private_data;
1463 int v3_ide_register_harddisk(struct vm_device * ide_dev,
1467 struct v3_ide_hd_ops * ops,
1468 void * private_data) {
1470 struct ide_internal * ide = (struct ide_internal *)(ide_dev->private_data);
1471 struct ide_channel * channel = NULL;
1472 struct ide_drive * drive = NULL;
1474 V3_ASSERT((bus_num >= 0) && (bus_num < 2));
1475 V3_ASSERT((drive_num >= 0) && (drive_num < 2));
1477 channel = &(ide->channels[bus_num]);
1478 drive = &(channel->drives[drive_num]);
1480 if (drive->drive_type != IDE_NONE) {
1481 PrintError("Device slot (bus=%d, drive=%d) already occupied\n", bus_num, drive_num);
1485 strncpy(drive->model, dev_name, sizeof(drive->model) - 1);
1487 drive->drive_type = IDE_DISK;
1489 drive->hd_state.accessed = 0;
1490 drive->hd_state.mult_sector_num = 1;
1492 drive->hd_ops = ops;
1494 /* this is something of a hack... */
1495 drive->num_sectors = 63;
1496 drive->num_heads = 16;
1497 drive->num_cylinders = (ops->get_capacity(private_data) / 512) / (drive->num_sectors * drive->num_heads);
1500 // Hardcode this for now, but its not a good idea....
1501 ide->ide_pci->config_space[0x41 + (bus_num * 2)] = 0x80;
1506 drive->private_data = private_data;