2 * This file is part of the Palacios Virtual Machine Monitor developed
3 * by the V3VEE Project with funding from the United States National
4 * Science Foundation and the Department of Energy.
6 * The V3VEE Project is a joint project between Northwestern University
7 * and the University of New Mexico. You can find out more at
10 * Copyright (c) 2008, Jack Lange <jarusl@cs.northwestern.edu>
11 * Copyright (c) 2008, The V3VEE Project <http://www.v3vee.org>
12 * All rights reserved.
14 * Author: Jack Lange <jarusl@cs.northwestern.edu>
16 * This is free software. You are permitted to use,
17 * redistribute, and modify it as specified in the file "V3VEE_LICENSE".
20 #include <palacios/vmm.h>
21 #include <palacios/vm_guest_mem.h>
22 #include <devices/ide.h>
23 #include <devices/pci.h>
24 #include "ide-types.h"
25 #include "atapi-types.h"
29 #define PrintDebug(fmt, args...)
32 #define PRI_DEFAULT_IRQ 14
33 #define SEC_DEFAULT_IRQ 15
36 #define PRI_DATA_PORT 0x1f0
37 #define PRI_FEATURES_PORT 0x1f1
38 #define PRI_SECT_CNT_PORT 0x1f2
39 #define PRI_SECT_NUM_PORT 0x1f3
40 #define PRI_CYL_LOW_PORT 0x1f4
41 #define PRI_CYL_HIGH_PORT 0x1f5
42 #define PRI_DRV_SEL_PORT 0x1f6
43 #define PRI_CMD_PORT 0x1f7
44 #define PRI_CTRL_PORT 0x3f6
45 #define PRI_ADDR_REG_PORT 0x3f7
47 #define SEC_DATA_PORT 0x170
48 #define SEC_FEATURES_PORT 0x171
49 #define SEC_SECT_CNT_PORT 0x172
50 #define SEC_SECT_NUM_PORT 0x173
51 #define SEC_CYL_LOW_PORT 0x174
52 #define SEC_CYL_HIGH_PORT 0x175
53 #define SEC_DRV_SEL_PORT 0x176
54 #define SEC_CMD_PORT 0x177
55 #define SEC_CTRL_PORT 0x376
56 #define SEC_ADDR_REG_PORT 0x377
59 #define PRI_DEFAULT_DMA_PORT 0xc000
60 #define SEC_DEFAULT_DMA_PORT 0xc008
62 #define DATA_BUFFER_SIZE 2048
64 static const char * ide_pri_port_strs[] = {"PRI_DATA", "PRI_FEATURES", "PRI_SECT_CNT", "PRI_SECT_NUM",
65 "PRI_CYL_LOW", "PRI_CYL_HIGH", "PRI_DRV_SEL", "PRI_CMD",
66 "PRI_CTRL", "PRI_ADDR_REG"};
69 static const char * ide_sec_port_strs[] = {"SEC_DATA", "SEC_FEATURES", "SEC_SECT_CNT", "SEC_SECT_NUM",
70 "SEC_CYL_LOW", "SEC_CYL_HIGH", "SEC_DRV_SEL", "SEC_CMD",
71 "SEC_CTRL", "SEC_ADDR_REG"};
73 static const char * ide_dma_port_strs[] = {"DMA_CMD", NULL, "DMA_STATUS", NULL,
74 "DMA_PRD0", "DMA_PRD1", "DMA_PRD2", "DMA_PRD3"};
78 static inline const char * io_port_to_str(uint16_t port) {
79 if ((port >= PRI_DATA_PORT) && (port <= PRI_CMD_PORT)) {
80 return ide_pri_port_strs[port - PRI_DATA_PORT];
81 } else if ((port >= SEC_DATA_PORT) && (port <= SEC_CMD_PORT)) {
82 return ide_sec_port_strs[port - SEC_DATA_PORT];
83 } else if ((port == PRI_CTRL_PORT) || (port == PRI_ADDR_REG_PORT)) {
84 return ide_pri_port_strs[port - PRI_CTRL_PORT + 8];
85 } else if ((port == SEC_CTRL_PORT) || (port == SEC_ADDR_REG_PORT)) {
86 return ide_sec_port_strs[port - SEC_CTRL_PORT + 8];
92 static inline const char * dma_port_to_str(uint16_t port) {
93 return ide_dma_port_strs[port & 0x7];
97 static const char * ide_dev_type_strs[] = {"NONE", "HARDDISK", "CDROM" };
100 static inline const char * device_type_to_str(v3_ide_dev_type_t type) {
105 return ide_dev_type_strs[type];
110 struct ide_cd_state {
111 struct atapi_sense_data sense;
114 struct atapi_error_recovery err_recovery;
117 struct ide_hd_state {
120 /* this is the multiple sector transfer size as configured for read/write multiple sectors*/
121 uint_t mult_sector_num;
123 /* This is the current op sector size:
124 * for multiple sector ops this equals mult_sector_num
125 * for standard ops this equals 1
127 uint_t cur_sector_num;
133 v3_ide_dev_type_t drive_type;
136 struct v3_ide_cd_ops * cd_ops;
137 struct v3_ide_hd_ops * hd_ops;
142 struct ide_cd_state cd_state;
143 struct ide_hd_state hd_state;
148 // Where we are in the data transfer
149 uint_t transfer_index;
151 // the length of a transfer
152 // calculated for easy access
153 uint_t transfer_length;
155 uint64_t current_lba;
157 // We have a local data buffer that we use for IO port accesses
158 uint8_t data_buf[DATA_BUFFER_SIZE];
164 uint8_t sector_count; // 0x1f2,0x172
165 struct atapi_irq_flags irq_flags;
166 } __attribute__((packed));
169 uint8_t sector_num; // 0x1f3,0x173
171 } __attribute__((packed));
178 uint8_t cylinder_low; // 0x1f4,0x174
179 uint8_t cylinder_high; // 0x1f5,0x175
180 } __attribute__((packed));
185 } __attribute__((packed));
188 // The transfer length requested by the CPU
190 } __attribute__((packed));
197 struct ide_drive drives[2];
200 struct ide_error_reg error_reg; // [read] 0x1f1,0x171
202 struct ide_features_reg features;
204 struct ide_drive_head_reg drive_head; // 0x1f6,0x176
206 struct ide_status_reg status; // [read] 0x1f7,0x177
207 uint8_t cmd_reg; // [write] 0x1f7,0x177
209 int irq; // this is temporary until we add PCI support
211 struct pci_device * pci_dev;
214 struct ide_ctrl_reg ctrl_reg; // [write] 0x3f6,0x376
216 struct ide_dma_cmd_reg dma_cmd;
217 struct ide_dma_status_reg dma_status;
218 uint32_t dma_prd_addr;
219 uint_t dma_tbl_index;
224 struct ide_internal {
225 struct ide_channel channels[2];
226 struct vm_device * pci;
227 struct pci_device * busmaster_pci;
234 /* Utility functions */
236 static inline uint16_t be_to_le_16(const uint16_t val) {
237 uint8_t * buf = (uint8_t *)&val;
238 return (buf[0] << 8) | (buf[1]) ;
241 static inline uint16_t le_to_be_16(const uint16_t val) {
242 return be_to_le_16(val);
246 static inline uint32_t be_to_le_32(const uint32_t val) {
247 uint8_t * buf = (uint8_t *)&val;
248 return (buf[0] << 24) | (buf[1] << 16) | (buf[2] << 8) | buf[3];
251 static inline uint32_t le_to_be_32(const uint32_t val) {
252 return be_to_le_32(val);
256 static inline int get_channel_index(ushort_t port) {
257 if (((port & 0xfff8) == 0x1f0) ||
258 ((port & 0xfffe) == 0x3f6) ||
259 ((port & 0xfff8) == 0xc000)) {
261 } else if (((port & 0xfff8) == 0x170) ||
262 ((port & 0xfffe) == 0x376) ||
263 ((port & 0xfff8) == 0xc008)) {
270 static inline struct ide_channel * get_selected_channel(struct ide_internal * ide, ushort_t port) {
271 int channel_idx = get_channel_index(port);
272 return &(ide->channels[channel_idx]);
275 static inline struct ide_drive * get_selected_drive(struct ide_channel * channel) {
276 return &(channel->drives[channel->drive_head.drive_sel]);
280 static inline int is_lba_enabled(struct ide_channel * channel) {
281 return channel->drive_head.lba_mode;
286 static void ide_raise_irq(struct vm_device * dev, struct ide_channel * channel) {
287 if (channel->ctrl_reg.irq_disable == 0) {
288 PrintDebug("Raising IDE Interrupt %d\n", channel->irq);
289 channel->dma_status.int_gen = 1;
290 v3_raise_irq(dev->vm, channel->irq);
295 static void drive_reset(struct ide_drive * drive) {
296 drive->sector_count = 0x01;
297 drive->sector_num = 0x01;
299 PrintDebug("Resetting drive %s\n", drive->model);
301 if (drive->drive_type == IDE_CDROM) {
302 drive->cylinder = 0xeb14;
304 drive->cylinder = 0x0000;
305 //drive->hd_state.accessed = 0;
309 memset(drive->data_buf, 0, sizeof(drive->data_buf));
310 drive->transfer_index = 0;
312 // Send the reset signal to the connected device callbacks
313 // channel->drives[0].reset();
314 // channel->drives[1].reset();
317 static void channel_reset(struct ide_channel * channel) {
319 // set busy and seek complete flags
320 channel->status.val = 0x90;
323 channel->error_reg.val = 0x01;
326 channel->cmd_reg = 0x00;
328 channel->ctrl_reg.irq_disable = 0;
331 static void channel_reset_complete(struct ide_channel * channel) {
332 channel->status.busy = 0;
333 channel->status.ready = 1;
335 channel->drive_head.head_num = 0;
337 drive_reset(&(channel->drives[0]));
338 drive_reset(&(channel->drives[1]));
342 static void ide_abort_command(struct vm_device * dev, struct ide_channel * channel) {
343 channel->status.val = 0x41; // Error + ready
344 channel->error_reg.val = 0x04; // No idea...
346 ide_raise_irq(dev, channel);
354 /* ATAPI functions */
363 static int dma_read(struct vm_device * dev, struct ide_channel * channel) {
364 struct ide_drive * drive = get_selected_drive(channel);
365 struct ide_dma_prd prd_entry;
366 uint32_t prd_entry_addr = channel->dma_prd_addr + (sizeof(struct ide_dma_prd) * channel->dma_tbl_index);
369 PrintDebug("PRD table address = %x\n", channel->dma_prd_addr);
371 ret = read_guest_pa_memory(dev->vm, prd_entry_addr, sizeof(struct ide_dma_prd), (void *)&prd_entry);
373 if (ret != sizeof(struct ide_dma_prd)) {
374 PrintError("Could not read PRD\n");
378 PrintDebug("PRD Addr: %x, PDR Len: %d, EOT: %d\n", prd_entry.base_addr, prd_entry.size, prd_entry.end_of_table);
380 ret = write_guest_pa_memory(dev->vm, prd_entry.base_addr, prd_entry.size, drive->data_buf);
382 if (ret != prd_entry.size) {
383 PrintError("Failed to copy data into guest memory... (ret=%d)\n", ret);
390 drive->irq_flags.io_dir = 1;
391 drive->irq_flags.c_d = 1;
392 drive->irq_flags.rel = 0;
398 if (prd_entry.end_of_table) {
399 channel->dma_status.active = 0;
400 channel->dma_status.err = 0;
401 channel->dma_status.int_gen = 1;
403 channel->status.busy = 0;
404 channel->status.ready = 1;
405 channel->status.data_req = 0;
406 channel->status.error = 0;
407 channel->status.seek_complete = 1;
410 ide_raise_irq(dev, channel);
416 static int dma_write(struct vm_device * dev, struct ide_channel * channel) {
418 PrintError("DMA writes currently not supported\n");
424 * This is an ugly ugly ugly way to differentiate between the first and second DMA channels
427 static int write_dma_port(ushort_t port_offset, void * src, uint_t length, struct vm_device * dev, struct ide_channel * channel);
428 static int read_dma_port(ushort_t port_offset, void * dst, uint_t length, struct vm_device * dev, struct ide_channel * channel);
431 static int write_pri_dma_port(ushort_t port, void * src, uint_t length, struct vm_device * dev) {
432 struct ide_internal * ide = (struct ide_internal *)(dev->private_data);
433 PrintDebug("IDE: Writing PRI DMA Port %x (%s) (val=%x)\n", port, dma_port_to_str(port & 0x7), *(uint32_t *)src);
434 return write_dma_port(port & 0x7, src, length, dev, &(ide->channels[0]));
437 static int write_sec_dma_port(ushort_t port, void * src, uint_t length, struct vm_device * dev) {
438 struct ide_internal * ide = (struct ide_internal *)(dev->private_data);
439 PrintDebug("IDE: Writing SEC DMA Port %x (%s) (val=%x)\n", port, dma_port_to_str(port & 0x7), *(uint32_t *)src);
440 return write_dma_port(port & 0x7, src, length, dev, &(ide->channels[1]));
444 static int read_pri_dma_port(ushort_t port, void * dst, uint_t length, struct vm_device * dev) {
445 struct ide_internal * ide = (struct ide_internal *)(dev->private_data);
446 PrintDebug("IDE: Reading PRI DMA Port %x (%s)\n", port, dma_port_to_str(port & 0x7));
447 return read_dma_port(port & 0x7, dst, length, dev, &(ide->channels[0]));
450 static int read_sec_dma_port(ushort_t port, void * dst, uint_t length, struct vm_device * dev) {
451 struct ide_internal * ide = (struct ide_internal *)(dev->private_data);
452 PrintDebug("IDE: Reading SEC DMA Port %x (%s)\n", port, dma_port_to_str(port & 0x7));
453 return read_dma_port(port & 0x7, dst, length, dev, &(ide->channels[1]));
457 #define DMA_CMD_PORT 0x00
458 #define DMA_STATUS_PORT 0x02
459 #define DMA_PRD_PORT0 0x04
460 #define DMA_PRD_PORT1 0x05
461 #define DMA_PRD_PORT2 0x06
462 #define DMA_PRD_PORT3 0x07
465 static int write_dma_port(ushort_t port_offset, void * src, uint_t length,
466 struct vm_device * dev, struct ide_channel * channel) {
468 switch (port_offset) {
470 channel->dma_cmd.val = *(uint8_t *)src;
472 if (channel->dma_cmd.start == 0) {
473 channel->dma_tbl_index = 0;
475 channel->dma_status.active = 1;
477 if (channel->dma_cmd.read == 1) {
479 if (dma_read(dev, channel) == -1) {
480 PrintError("Failed DMA Read\n");
485 if (dma_write(dev, channel) == -1) {
486 PrintError("Failed DMA Write\n");
491 channel->dma_cmd.val &= 0x09;
496 case DMA_STATUS_PORT:
498 PrintError("Invalid read length for DMA status port\n");
502 channel->dma_status.val = *(uint8_t *)src;
508 case DMA_PRD_PORT3: {
509 uint_t addr_index = port_offset & 0x3;
510 uint8_t * addr_buf = (uint8_t *)&(channel->dma_prd_addr);
513 if (addr_index + length > 4) {
514 PrintError("DMA Port space overrun port=%x len=%d\n", port_offset, length);
518 for (i = 0; i < length; i++) {
519 addr_buf[addr_index + i] = *((uint8_t *)src + i);
522 PrintDebug("Writing PRD Port %x (val=%x)\n", port_offset, channel->dma_prd_addr);
527 PrintError("IDE: Invalid DMA Port (%s)\n", dma_port_to_str(port_offset));
535 static int read_dma_port(ushort_t port_offset, void * dst, uint_t length,
536 struct vm_device * dev, struct ide_channel * channel) {
538 switch (port_offset) {
540 *(uint8_t *)dst = channel->dma_cmd.val;
543 case DMA_STATUS_PORT:
545 PrintError("Invalid read length for DMA status port\n");
549 *(uint8_t *)dst = channel->dma_status.val;
555 case DMA_PRD_PORT3: {
556 uint_t addr_index = port_offset & 0x3;
557 uint8_t * addr_buf = (uint8_t *)&(channel->dma_prd_addr);
560 if (addr_index + length > 4) {
561 PrintError("DMA Port space overrun port=%x len=%d\n", port_offset, length);
565 for (i = 0; i < length; i++) {
566 *((uint8_t *)dst + i) = addr_buf[addr_index + i];
572 PrintError("IDE: Invalid DMA Port (%s)\n", dma_port_to_str(port_offset));
576 PrintDebug("\tval=%x\n", *(uint32_t *)dst);
583 static int write_cmd_port(ushort_t port, void * src, uint_t length, struct vm_device * dev) {
584 struct ide_internal * ide = (struct ide_internal *)(dev->private_data);
585 struct ide_channel * channel = get_selected_channel(ide, port);
586 struct ide_drive * drive = get_selected_drive(channel);
589 PrintError("Invalid Write Length on IDE command Port %x\n", port);
593 PrintDebug("IDE: Writing Command Port %x (%s) (val=%x)\n", port, io_port_to_str(port), *(uint8_t *)src);
595 channel->cmd_reg = *(uint8_t *)src;
597 switch (channel->cmd_reg) {
599 case 0xa1: // ATAPI Identify Device Packet
600 if (drive->drive_type != IDE_CDROM) {
603 // JRL: Should we abort here?
604 ide_abort_command(dev, channel);
607 atapi_identify_device(drive);
609 channel->error_reg.val = 0;
610 channel->status.val = 0x58; // ready, data_req, seek_complete
612 ide_raise_irq(dev, channel);
615 case 0xec: // Identify Device
616 if (drive->drive_type != IDE_DISK) {
619 // JRL: Should we abort here?
620 ide_abort_command(dev, channel);
622 ata_identify_device(drive);
624 channel->error_reg.val = 0;
625 channel->status.val = 0x58;
627 ide_raise_irq(dev, channel);
631 case 0xa0: // ATAPI Command Packet
632 if (drive->drive_type != IDE_CDROM) {
633 ide_abort_command(dev, channel);
636 drive->sector_count = 1;
638 channel->status.busy = 0;
639 channel->status.write_fault = 0;
640 channel->status.data_req = 1;
641 channel->status.error = 0;
643 // reset the data buffer...
644 drive->transfer_length = ATAPI_PACKET_SIZE;
645 drive->transfer_index = 0;
649 case 0x20: // Read Sectors with Retry
650 case 0x21: // Read Sectors without Retry
651 drive->hd_state.cur_sector_num = 1;
653 if (ata_read_sectors(dev, channel) == -1) {
654 PrintError("Error reading sectors\n");
659 case 0x24: // Read Sectors Extended
660 drive->hd_state.cur_sector_num = 1;
662 if (ata_read_sectors_ext(dev, channel) == -1) {
663 PrintError("Error reading extended sectors\n");
668 case 0xc8: // Read DMA with retry
669 case 0xc9: // Read DMA
670 drive->hd_state.cur_sector_num = 1;
673 case 0xef: // Set Features
674 // Prior to this the features register has been written to.
675 // This command tells the drive to check if the new value is supported (the value is drive specific)
676 // Common is that bit0=DMA enable
677 // If valid the drive raises an interrupt, if not it aborts.
679 // Do some checking here...
681 channel->status.busy = 0;
682 channel->status.write_fault = 0;
683 channel->status.error = 0;
684 channel->status.ready = 1;
685 channel->status.seek_complete = 1;
687 ide_raise_irq(dev, channel);
690 case 0x91: // Initialize Drive Parameters
691 case 0x10: // recalibrate?
692 channel->status.error = 0;
693 channel->status.ready = 1;
694 channel->status.seek_complete = 1;
695 ide_raise_irq(dev, channel);
697 case 0xc6: { // Set multiple mode (IDE Block mode)
698 // This makes the drive transfer multiple sectors before generating an interrupt
699 uint32_t tmp_sect_num = drive->sector_num; // GCC SUCKS
701 if (tmp_sect_num > MAX_MULT_SECTORS) {
702 ide_abort_command(dev, channel);
706 if (drive->sector_count == 0) {
707 drive->hd_state.mult_sector_num= 1;
709 drive->hd_state.mult_sector_num = drive->sector_count;
712 channel->status.ready = 1;
713 channel->status.error = 0;
715 ide_raise_irq(dev, channel);
719 case 0xc4: // read multiple sectors
720 drive->hd_state.cur_sector_num = drive->hd_state.mult_sector_num;
722 PrintError("Unimplemented IDE command (%x)\n", channel->cmd_reg);
730 static int write_data_port(ushort_t port, void * src, uint_t length, struct vm_device * dev) {
731 struct ide_internal * ide = (struct ide_internal *)(dev->private_data);
732 struct ide_channel * channel = get_selected_channel(ide, port);
733 struct ide_drive * drive = get_selected_drive(channel);
735 // PrintDebug("IDE: Writing Data Port %x (val=%x, len=%d)\n",
736 // port, *(uint32_t *)src, length);
738 memcpy(drive->data_buf + drive->transfer_index, src, length);
739 drive->transfer_index += length;
741 // Transfer is complete, dispatch the command
742 if (drive->transfer_index >= drive->transfer_length) {
743 switch (channel->cmd_reg) {
744 case 0x30: // Write Sectors
745 PrintError("Writing Data not yet implemented\n");
748 case 0xa0: // ATAPI packet command
749 if (atapi_handle_packet(dev, channel) == -1) {
750 PrintError("Error handling ATAPI packet\n");
755 PrintError("Unhandld IDE Command %x\n", channel->cmd_reg);
764 static int read_hd_data(uint8_t * dst, uint_t length, struct vm_device * dev, struct ide_channel * channel) {
765 struct ide_drive * drive = get_selected_drive(channel);
766 int data_offset = drive->transfer_index % IDE_SECTOR_SIZE;
770 if (drive->transfer_index >= drive->transfer_length) {
771 PrintError("Buffer overrun... (xfer_len=%d) (cur_idx=%x) (post_idx=%d)\n",
772 drive->transfer_length, drive->transfer_index,
773 drive->transfer_index + length);
778 if ((data_offset == 0) && (drive->transfer_index > 0)) {
779 drive->current_lba++;
781 if (ata_read(dev, channel, drive->data_buf, 1) == -1) {
782 PrintError("Could not read next disk sector\n");
788 PrintDebug("Reading HD Data (Val=%x), (len=%d) (offset=%d)\n",
789 *(uint32_t *)(drive->data_buf + data_offset),
790 length, data_offset);
792 memcpy(dst, drive->data_buf + data_offset, length);
794 drive->transfer_index += length;
797 /* This is the trigger for interrupt injection.
798 * For read single sector commands we interrupt after every sector
799 * For multi sector reads we interrupt only at end of the cluster size (mult_sector_num)
800 * cur_sector_num is configured depending on the operation we are currently running
801 * We also trigger an interrupt if this is the last byte to transfer, regardless of sector count
803 if (((drive->transfer_index % (IDE_SECTOR_SIZE * drive->hd_state.cur_sector_num)) == 0) ||
804 (drive->transfer_index == drive->transfer_length)) {
805 if (drive->transfer_index < drive->transfer_length) {
806 // An increment is complete, but there is still more data to be transferred...
807 PrintDebug("Integral Complete, still transferring more sectors\n");
808 channel->status.data_req = 1;
810 drive->irq_flags.c_d = 0;
812 PrintDebug("Final Sector Transferred\n");
813 // This was the final read of the request
814 channel->status.data_req = 0;
817 drive->irq_flags.c_d = 1;
818 drive->irq_flags.rel = 0;
821 channel->status.ready = 1;
822 drive->irq_flags.io_dir = 1;
823 channel->status.busy = 0;
825 ide_raise_irq(dev, channel);
834 static int read_cd_data(uint8_t * dst, uint_t length, struct vm_device * dev, struct ide_channel * channel) {
835 struct ide_drive * drive = get_selected_drive(channel);
836 int data_offset = drive->transfer_index % ATAPI_BLOCK_SIZE;
837 int req_offset = drive->transfer_index % drive->req_len;
839 if (drive->cd_state.atapi_cmd != 0x28) {
840 PrintDebug("IDE: Reading CD Data (len=%d) (req_len=%d)\n", length, drive->req_len);
843 if (drive->transfer_index >= drive->transfer_length) {
844 PrintError("Buffer Overrun... (xfer_len=%d) (cur_idx=%d) (post_idx=%d)\n",
845 drive->transfer_length, drive->transfer_index,
846 drive->transfer_index + length);
852 if ((data_offset == 0) && (drive->transfer_index > 0)) {
853 if (atapi_update_data_buf(dev, channel) == -1) {
854 PrintError("Could not update CDROM data buffer\n");
859 memcpy(dst, drive->data_buf + data_offset, length);
861 drive->transfer_index += length;
864 // Should the req_offset be recalculated here?????
865 if ((req_offset == 0) && (drive->transfer_index > 0)) {
866 if (drive->transfer_index < drive->transfer_length) {
867 // An increment is complete, but there is still more data to be transferred...
869 channel->status.data_req = 1;
871 drive->irq_flags.c_d = 0;
873 // Update the request length in the cylinder regs
874 if (atapi_update_req_len(dev, channel, drive->transfer_length - drive->transfer_index) == -1) {
875 PrintError("Could not update request length after completed increment\n");
879 // This was the final read of the request
880 channel->status.data_req = 0;
881 channel->status.ready = 1;
883 drive->irq_flags.c_d = 1;
884 drive->irq_flags.rel = 0;
887 drive->irq_flags.io_dir = 1;
888 channel->status.busy = 0;
890 ide_raise_irq(dev, channel);
897 static int read_drive_id(uint8_t * dst, uint_t length, struct vm_device * dev, struct ide_channel * channel) {
898 struct ide_drive * drive = get_selected_drive(channel);
900 channel->status.busy = 0;
901 channel->status.ready = 1;
902 channel->status.write_fault = 0;
903 channel->status.seek_complete = 1;
904 channel->status.corrected = 0;
905 channel->status.error = 0;
908 memcpy(dst, drive->data_buf + drive->transfer_index, length);
909 drive->transfer_index += length;
911 if (drive->transfer_index >= drive->transfer_length) {
912 channel->status.data_req = 0;
919 static int ide_read_data_port(ushort_t port, void * dst, uint_t length, struct vm_device * dev) {
920 struct ide_internal * ide = (struct ide_internal *)(dev->private_data);
921 struct ide_channel * channel = get_selected_channel(ide, port);
922 struct ide_drive * drive = get_selected_drive(channel);
924 // PrintDebug("IDE: Reading Data Port %x (len=%d)\n", port, length);
926 if ((channel->cmd_reg == 0xec) ||
927 (channel->cmd_reg == 0xa1)) {
928 return read_drive_id((uint8_t *)dst, length, dev, channel);
931 if (drive->drive_type == IDE_CDROM) {
932 if (read_cd_data((uint8_t *)dst, length, dev, channel) == -1) {
933 PrintError("IDE: Could not read CD Data\n");
936 } else if (drive->drive_type == IDE_DISK) {
937 if (read_hd_data((uint8_t *)dst, length, dev, channel) == -1) {
938 PrintError("IDE: Could not read HD Data\n");
942 memset((uint8_t *)dst, 0, length);
948 static int write_port_std(ushort_t port, void * src, uint_t length, struct vm_device * dev) {
949 struct ide_internal * ide = (struct ide_internal *)(dev->private_data);
950 struct ide_channel * channel = get_selected_channel(ide, port);
951 struct ide_drive * drive = get_selected_drive(channel);
954 PrintError("Invalid Write length on IDE port %x\n", port);
958 PrintDebug("IDE: Writing Standard Port %x (%s) (val=%x)\n", port, io_port_to_str(port), *(uint8_t *)src);
961 // reset and interrupt enable
963 case SEC_CTRL_PORT: {
964 struct ide_ctrl_reg * tmp_ctrl = (struct ide_ctrl_reg *)src;
966 // only reset channel on a 0->1 reset bit transition
967 if ((!channel->ctrl_reg.soft_reset) && (tmp_ctrl->soft_reset)) {
968 channel_reset(channel);
969 } else if ((channel->ctrl_reg.soft_reset) && (!tmp_ctrl->soft_reset)) {
970 channel_reset_complete(channel);
973 channel->ctrl_reg.val = tmp_ctrl->val;
976 case PRI_FEATURES_PORT:
977 case SEC_FEATURES_PORT:
978 channel->features.val = *(uint8_t *)src;
981 case PRI_SECT_CNT_PORT:
982 case SEC_SECT_CNT_PORT:
983 channel->drives[0].sector_count = *(uint8_t *)src;
984 channel->drives[1].sector_count = *(uint8_t *)src;
987 case PRI_SECT_NUM_PORT:
988 case SEC_SECT_NUM_PORT:
989 channel->drives[0].sector_num = *(uint8_t *)src;
990 channel->drives[1].sector_num = *(uint8_t *)src;
992 case PRI_CYL_LOW_PORT:
993 case SEC_CYL_LOW_PORT:
994 channel->drives[0].cylinder_low = *(uint8_t *)src;
995 channel->drives[1].cylinder_low = *(uint8_t *)src;
998 case PRI_CYL_HIGH_PORT:
999 case SEC_CYL_HIGH_PORT:
1000 channel->drives[0].cylinder_high = *(uint8_t *)src;
1001 channel->drives[1].cylinder_high = *(uint8_t *)src;
1004 case PRI_DRV_SEL_PORT:
1005 case SEC_DRV_SEL_PORT: {
1006 channel->drive_head.val = *(uint8_t *)src;
1008 // make sure the reserved bits are ok..
1009 // JRL TODO: check with new ramdisk to make sure this is right...
1010 channel->drive_head.val |= 0xa0;
1012 drive = get_selected_drive(channel);
1014 // Selecting a non-present device is a no-no
1015 if (drive->drive_type == IDE_NONE) {
1016 PrintDebug("Attempting to select a non-present drive\n");
1017 channel->error_reg.abort = 1;
1018 channel->status.error = 1;
1024 PrintError("IDE: Write to unknown Port %x\n", port);
1031 static int read_port_std(ushort_t port, void * dst, uint_t length, struct vm_device * dev) {
1032 struct ide_internal * ide = (struct ide_internal *)(dev->private_data);
1033 struct ide_channel * channel = get_selected_channel(ide, port);
1034 struct ide_drive * drive = get_selected_drive(channel);
1037 PrintError("Invalid Read length on IDE port %x\n", port);
1041 PrintDebug("IDE: Reading Standard Port %x (%s)\n", port, io_port_to_str(port));
1043 if ((port == PRI_ADDR_REG_PORT) ||
1044 (port == SEC_ADDR_REG_PORT)) {
1045 // unused, return 0xff
1046 *(uint8_t *)dst = 0xff;
1051 // if no drive is present just return 0 + reserved bits
1052 if (drive->drive_type == IDE_NONE) {
1053 if ((port == PRI_DRV_SEL_PORT) ||
1054 (port == SEC_DRV_SEL_PORT)) {
1055 *(uint8_t *)dst = 0xa0;
1057 *(uint8_t *)dst = 0;
1065 // This is really the error register.
1066 case PRI_FEATURES_PORT:
1067 case SEC_FEATURES_PORT:
1068 *(uint8_t *)dst = channel->error_reg.val;
1071 case PRI_SECT_CNT_PORT:
1072 case SEC_SECT_CNT_PORT:
1073 *(uint8_t *)dst = drive->sector_count;
1076 case PRI_SECT_NUM_PORT:
1077 case SEC_SECT_NUM_PORT:
1078 *(uint8_t *)dst = drive->sector_num;
1081 case PRI_CYL_LOW_PORT:
1082 case SEC_CYL_LOW_PORT:
1083 *(uint8_t *)dst = drive->cylinder_low;
1087 case PRI_CYL_HIGH_PORT:
1088 case SEC_CYL_HIGH_PORT:
1089 *(uint8_t *)dst = drive->cylinder_high;
1092 case PRI_DRV_SEL_PORT:
1093 case SEC_DRV_SEL_PORT: // hard disk drive and head register 0x1f6
1094 *(uint8_t *)dst = channel->drive_head.val;
1101 // Something about lowering interrupts here....
1102 *(uint8_t *)dst = channel->status.val;
1106 PrintError("Invalid Port: %x\n", port);
1110 PrintDebug("\tVal=%x\n", *(uint8_t *)dst);
1117 static void init_drive(struct ide_drive * drive) {
1119 drive->sector_count = 0x01;
1120 drive->sector_num = 0x01;
1121 drive->cylinder = 0x0000;
1123 drive->drive_type = IDE_NONE;
1125 memset(drive->model, 0, sizeof(drive->model));
1127 drive->transfer_index = 0;
1128 drive->transfer_length = 0;
1129 memset(drive->data_buf, 0, sizeof(drive->data_buf));
1132 drive->private_data = NULL;
1133 drive->cd_ops = NULL;
1136 static void init_channel(struct ide_channel * channel) {
1139 channel->error_reg.val = 0x01;
1140 channel->drive_head.val = 0x00;
1141 channel->status.val = 0x00;
1142 channel->cmd_reg = 0x00;
1143 channel->ctrl_reg.val = 0x08;
1146 channel->dma_cmd.val = 0;
1147 channel->dma_status.val = 0;
1148 channel->dma_prd_addr = 0;
1149 channel->dma_tbl_index = 0;
1151 for (i = 0; i < 2; i++) {
1152 init_drive(&(channel->drives[i]));
1158 static int pci_config_update(struct pci_device * pci_dev, uint_t reg_num, int length) {
1159 PrintDebug("PCI Config Update\n");
1160 PrintDebug("\t\tInterupt register (Dev=%s), irq=%d\n", pci_dev->name, pci_dev->config_header.intr_line);
1165 static int init_ide_state(struct vm_device * dev) {
1166 struct ide_internal * ide = (struct ide_internal *)(dev->private_data);
1167 struct v3_pci_bar bars[6];
1168 struct pci_device * pci_dev = NULL;
1171 for (i = 0; i < 2; i++) {
1172 init_channel(&(ide->channels[i]));
1174 // JRL: this is a terrible hack...
1175 ide->channels[i].irq = PRI_DEFAULT_IRQ + i;
1177 for (j = 0; j < 6; j++) {
1178 bars[j].type = PCI_BAR_NONE;
1182 bars[4].type = PCI_BAR_IO;
1183 bars[4].default_base_port = PRI_DEFAULT_DMA_PORT + (i * 0x8);
1184 bars[4].num_ports = 8;
1187 bars[4].io_read = read_pri_dma_port;
1188 bars[4].io_write = write_pri_dma_port;
1190 bars[4].io_read = read_sec_dma_port;
1191 bars[4].io_write = write_sec_dma_port;
1194 pci_dev = v3_pci_register_device(ide->pci, PCI_STD_DEVICE, 0, "V3_IDE", -1, bars,
1195 pci_config_update, NULL, NULL, dev);
1197 if (pci_dev == NULL) {
1198 PrintError("Failed to register IDE BUS %d with PCI\n", i);
1202 ide->channels[i].pci_dev = pci_dev;
1204 pci_dev->config_header.vendor_id = 0x1095;
1205 pci_dev->config_header.device_id = 0x0646;
1206 pci_dev->config_header.revision = 0x8f07;
1207 pci_dev->config_header.subclass = 0x01;
1208 pci_dev->config_header.class = 0x01;
1210 pci_dev->config_header.intr_line = PRI_DEFAULT_IRQ + i;
1211 pci_dev->config_header.intr_pin = 1;
1216 /* Register PIIX3 Busmaster PCI device */
1217 for (j = 0; j < 6; j++) {
1218 bars[j].type = PCI_BAR_NONE;
1221 pci_dev = v3_pci_register_device(ide->pci, PCI_STD_DEVICE, 0, "PIIX3 IDE", -1, bars,
1222 NULL, NULL, NULL, dev);
1225 ide->busmaster_pci = pci_dev;
1227 pci_dev->config_header.vendor_id = 0x8086;
1228 pci_dev->config_header.device_id = 0x7010;
1229 pci_dev->config_header.revision = 0x80;
1230 pci_dev->config_header.subclass = 0x01;
1231 pci_dev->config_header.class = 0x01;
1239 static int init_ide(struct vm_device * dev) {
1240 //struct ide_internal * ide = (struct ide_internal *)(dev->private_data);
1242 PrintDebug("IDE: Initializing IDE\n");
1244 if (init_ide_state(dev) == -1) {
1245 PrintError("Failed to initialize IDE state\n");
1250 v3_dev_hook_io(dev, PRI_DATA_PORT,
1251 &ide_read_data_port, &write_data_port);
1252 v3_dev_hook_io(dev, PRI_FEATURES_PORT,
1253 &read_port_std, &write_port_std);
1254 v3_dev_hook_io(dev, PRI_SECT_CNT_PORT,
1255 &read_port_std, &write_port_std);
1256 v3_dev_hook_io(dev, PRI_SECT_NUM_PORT,
1257 &read_port_std, &write_port_std);
1258 v3_dev_hook_io(dev, PRI_CYL_LOW_PORT,
1259 &read_port_std, &write_port_std);
1260 v3_dev_hook_io(dev, PRI_CYL_HIGH_PORT,
1261 &read_port_std, &write_port_std);
1262 v3_dev_hook_io(dev, PRI_DRV_SEL_PORT,
1263 &read_port_std, &write_port_std);
1264 v3_dev_hook_io(dev, PRI_CMD_PORT,
1265 &read_port_std, &write_cmd_port);
1267 v3_dev_hook_io(dev, SEC_DATA_PORT,
1268 &ide_read_data_port, &write_data_port);
1269 v3_dev_hook_io(dev, SEC_FEATURES_PORT,
1270 &read_port_std, &write_port_std);
1271 v3_dev_hook_io(dev, SEC_SECT_CNT_PORT,
1272 &read_port_std, &write_port_std);
1273 v3_dev_hook_io(dev, SEC_SECT_NUM_PORT,
1274 &read_port_std, &write_port_std);
1275 v3_dev_hook_io(dev, SEC_CYL_LOW_PORT,
1276 &read_port_std, &write_port_std);
1277 v3_dev_hook_io(dev, SEC_CYL_HIGH_PORT,
1278 &read_port_std, &write_port_std);
1279 v3_dev_hook_io(dev, SEC_DRV_SEL_PORT,
1280 &read_port_std, &write_port_std);
1281 v3_dev_hook_io(dev, SEC_CMD_PORT,
1282 &read_port_std, &write_cmd_port);
1285 v3_dev_hook_io(dev, PRI_CTRL_PORT,
1286 &read_port_std, &write_port_std);
1288 v3_dev_hook_io(dev, SEC_CTRL_PORT,
1289 &read_port_std, &write_port_std);
1292 v3_dev_hook_io(dev, SEC_ADDR_REG_PORT,
1293 &read_port_std, &write_port_std);
1295 v3_dev_hook_io(dev, PRI_ADDR_REG_PORT,
1296 &read_port_std, &write_port_std);
1302 static int deinit_ide(struct vm_device * dev) {
1303 // unhook io ports....
1304 // deregister from PCI?
1309 static struct vm_device_ops dev_ops = {
1311 .deinit = deinit_ide,
1318 struct vm_device * v3_create_ide(struct vm_device * pci) {
1319 struct ide_internal * ide = (struct ide_internal *)V3_Malloc(sizeof(struct ide_internal));
1320 struct vm_device * device = v3_create_device("IDE", &dev_ops, ide);
1324 PrintDebug("IDE: Creating IDE bus x 2\n");
1333 int v3_ide_register_cdrom(struct vm_device * ide_dev,
1337 struct v3_ide_cd_ops * ops,
1338 void * private_data) {
1340 struct ide_internal * ide = (struct ide_internal *)(ide_dev->private_data);
1341 struct ide_channel * channel = NULL;
1342 struct ide_drive * drive = NULL;
1344 V3_ASSERT((bus_num >= 0) && (bus_num < 2));
1345 V3_ASSERT((drive_num >= 0) && (drive_num < 2));
1347 channel = &(ide->channels[bus_num]);
1348 drive = &(channel->drives[drive_num]);
1350 if (drive->drive_type != IDE_NONE) {
1351 PrintError("Device slot (bus=%d, drive=%d) already occupied\n", bus_num, drive_num);
1355 strncpy(drive->model, dev_name, sizeof(drive->model) - 1);
1357 while (strlen((char *)(drive->model)) < 40) {
1358 strcat((char*)(drive->model), " ");
1362 drive->drive_type = IDE_CDROM;
1364 drive->cd_ops = ops;
1366 drive->private_data = private_data;
1372 int v3_ide_register_harddisk(struct vm_device * ide_dev,
1376 struct v3_ide_hd_ops * ops,
1377 void * private_data) {
1379 struct ide_internal * ide = (struct ide_internal *)(ide_dev->private_data);
1380 struct ide_channel * channel = NULL;
1381 struct ide_drive * drive = NULL;
1383 V3_ASSERT((bus_num >= 0) && (bus_num < 2));
1384 V3_ASSERT((drive_num >= 0) && (drive_num < 2));
1386 channel = &(ide->channels[bus_num]);
1387 drive = &(channel->drives[drive_num]);
1389 if (drive->drive_type != IDE_NONE) {
1390 PrintError("Device slot (bus=%d, drive=%d) already occupied\n", bus_num, drive_num);
1394 strncpy(drive->model, dev_name, sizeof(drive->model) - 1);
1396 drive->drive_type = IDE_DISK;
1398 drive->hd_state.accessed = 0;
1399 drive->hd_state.mult_sector_num = 1;
1401 drive->hd_ops = ops;
1403 drive->private_data = private_data;