2 * This file is part of the Palacios Virtual Machine Monitor developed
3 * by the V3VEE Project with funding from the United States National
4 * Science Foundation and the Department of Energy.
6 * The V3VEE Project is a joint project between Northwestern University
7 * and the University of New Mexico. You can find out more at
10 * Copyright (c) 2008, Jack Lange <jarusl@cs.northwestern.edu>
11 * Copyright (c) 2008, The V3VEE Project <http://www.v3vee.org>
12 * All rights reserved.
14 * Author: Jack Lange <jarusl@cs.northwestern.edu>
16 * This is free software. You are permitted to use,
17 * redistribute, and modify it as specified in the file "V3VEE_LICENSE".
20 #include <palacios/vmm.h>
21 #include <palacios/vm_guest_mem.h>
22 #include <devices/ide.h>
23 #include <devices/pci.h>
24 #include "ide-types.h"
25 #include "atapi-types.h"
27 #define PRI_DEFAULT_IRQ 14
28 #define SEC_DEFAULT_IRQ 15
31 #define PRI_DATA_PORT 0x1f0
32 #define PRI_FEATURES_PORT 0x1f1
33 #define PRI_SECT_CNT_PORT 0x1f2
34 #define PRI_SECT_NUM_PORT 0x1f3
35 #define PRI_CYL_LOW_PORT 0x1f4
36 #define PRI_CYL_HIGH_PORT 0x1f5
37 #define PRI_DRV_SEL_PORT 0x1f6
38 #define PRI_CMD_PORT 0x1f7
39 #define PRI_CTRL_PORT 0x3f6
40 #define PRI_ADDR_REG_PORT 0x3f7
42 #define SEC_DATA_PORT 0x170
43 #define SEC_FEATURES_PORT 0x171
44 #define SEC_SECT_CNT_PORT 0x172
45 #define SEC_SECT_NUM_PORT 0x173
46 #define SEC_CYL_LOW_PORT 0x174
47 #define SEC_CYL_HIGH_PORT 0x175
48 #define SEC_DRV_SEL_PORT 0x176
49 #define SEC_CMD_PORT 0x177
50 #define SEC_CTRL_PORT 0x376
51 #define SEC_ADDR_REG_PORT 0x377
54 #define PRI_DEFAULT_DMA_PORT 0xc000
55 #define SEC_DEFAULT_DMA_PORT 0xc008
58 #define DATA_BUFFER_SIZE 2048
60 static const char * ide_pri_port_strs[] = {"PRI_DATA", "PRI_FEATURES", "PRI_SECT_CNT", "PRI_SECT_NUM",
61 "PRI_CYL_LOW", "PRI_CYL_HIGH", "PRI_DRV_SEL", "PRI_CMD",
62 "PRI_CTRL", "PRI_ADDR_REG"};
65 static const char * ide_sec_port_strs[] = {"SEC_DATA", "SEC_FEATURES", "SEC_SECT_CNT", "SEC_SECT_NUM",
66 "SEC_CYL_LOW", "SEC_CYL_HIGH", "SEC_DRV_SEL", "SEC_CMD",
67 "SEC_CTRL", "SEC_ADDR_REG"};
69 static const char * ide_dma_port_strs[] = {"DMA_CMD", NULL, "DMA_STATUS", NULL,
70 "DMA_PRD0", "DMA_PRD1", "DMA_PRD2", "DMA_PRD3"};
74 static inline const char * io_port_to_str(uint16_t port) {
75 if ((port >= PRI_DATA_PORT) && (port <= PRI_CMD_PORT)) {
76 return ide_pri_port_strs[port - PRI_DATA_PORT];
77 } else if ((port >= SEC_DATA_PORT) && (port <= SEC_CMD_PORT)) {
78 return ide_sec_port_strs[port - SEC_DATA_PORT];
79 } else if ((port == PRI_CTRL_PORT) || (port == PRI_ADDR_REG_PORT)) {
80 return ide_pri_port_strs[port - PRI_CTRL_PORT + 8];
81 } else if ((port == SEC_CTRL_PORT) || (port == SEC_ADDR_REG_PORT)) {
82 return ide_sec_port_strs[port - SEC_CTRL_PORT + 8];
88 static inline const char * dma_port_to_str(uint16_t port) {
89 return ide_dma_port_strs[port & 0x7];
93 static const char * ide_dev_type_strs[] = {"HARDDISK", "CDROM", "NONE"};
96 static inline const char * device_type_to_str(v3_ide_dev_type_t type) {
101 return ide_dev_type_strs[type];
106 struct ide_cd_state {
107 struct atapi_sense_data sense;
110 struct atapi_error_recovery err_recovery;
113 struct ide_hd_state {
120 v3_ide_dev_type_t drive_type;
123 struct v3_ide_cd_ops * cd_ops;
124 struct v3_ide_hd_ops * hd_ops;
129 struct ide_cd_state cd_state;
130 struct ide_hd_state hd_state;
135 // Where we are in the data transfer
136 uint_t transfer_index;
138 // the length of a transfer
139 // calculated for easy access
140 uint_t transfer_length;
143 // We have a local data buffer that we use for IO port accesses
144 uint8_t data_buf[DATA_BUFFER_SIZE];
150 uint8_t sector_count; // 0x1f2,0x172
151 struct atapi_irq_flags irq_flags;
152 } __attribute__((packed));
155 uint8_t sector_num; // 0x1f3,0x173
165 uint8_t cylinder_low; // 0x1f4,0x174
166 uint8_t cylinder_high; // 0x1f5,0x175
167 } __attribute__((packed));
172 } __attribute__((packed));
175 // The transfer length requested by the CPU
177 } __attribute__((packed));
184 struct ide_drive drives[2];
187 struct ide_error_reg error_reg; // [read] 0x1f1,0x171
189 struct ide_features_reg features;
191 struct ide_drive_head_reg drive_head; // 0x1f6,0x176
193 struct ide_status_reg status; // [read] 0x1f7,0x177
194 uint8_t cmd_reg; // [write] 0x1f7,0x177
196 int irq; // this is temporary until we add PCI support
198 struct pci_device * pci_dev;
201 struct ide_ctrl_reg ctrl_reg; // [write] 0x3f6,0x376
203 struct ide_dma_cmd_reg dma_cmd;
204 struct ide_dma_status_reg dma_status;
205 uint32_t dma_prd_addr;
206 uint_t dma_tbl_index;
211 struct ide_internal {
212 struct ide_channel channels[2];
213 struct vm_device * pci;
214 struct pci_device * busmaster_pci;
219 static inline uint16_t be_to_le_16(const uint16_t val) {
220 uint8_t * buf = (uint8_t *)&val;
221 return (buf[0] << 8) | (buf[1]) ;
224 static inline uint16_t le_to_be_16(const uint16_t val) {
225 return be_to_le_16(val);
229 static inline uint32_t be_to_le_32(const uint32_t val) {
230 uint8_t * buf = (uint8_t *)&val;
231 return (buf[0] << 24) | (buf[1] << 16) | (buf[2] << 8) | buf[3];
234 static inline uint32_t le_to_be_32(const uint32_t val) {
235 return be_to_le_32(val);
239 static inline int get_channel_index(ushort_t port) {
240 if (((port & 0xfff8) == 0x1f0) ||
241 ((port & 0xfffe) == 0x3f6) ||
242 ((port & 0xfff8) == 0xc000)) {
244 } else if (((port & 0xfff8) == 0x170) ||
245 ((port & 0xfffe) == 0x376) ||
246 ((port & 0xfff8) == 0xc008)) {
253 static inline struct ide_channel * get_selected_channel(struct ide_internal * ide, ushort_t port) {
254 int channel_idx = get_channel_index(port);
255 return &(ide->channels[channel_idx]);
258 static inline struct ide_drive * get_selected_drive(struct ide_channel * channel) {
259 return &(channel->drives[channel->drive_head.drive_sel]);
263 static inline int is_lba_enabled(struct ide_channel * channel) {
264 return channel->drive_head.lba_mode;
268 static void ide_raise_irq(struct vm_device * dev, struct ide_channel * channel) {
269 if (channel->ctrl_reg.irq_disable == 0) {
270 PrintDebug("Raising IDE Interrupt %d\n", channel->irq);
271 channel->dma_status.int_gen = 1;
272 v3_raise_irq(dev->vm, channel->irq);
277 static void drive_reset(struct ide_drive * drive) {
278 drive->sector_count = 0x01;
279 drive->sector_num = 0x01;
281 if (drive->drive_type == IDE_CDROM) {
282 drive->cylinder = 0xeb14;
284 drive->cylinder = 0x0000;
288 memset(drive->data_buf, 0, sizeof(drive->data_buf));
289 drive->transfer_index = 0;
291 // Send the reset signal to the connected device callbacks
292 // channel->drives[0].reset();
293 // channel->drives[1].reset();
296 static void channel_reset(struct ide_channel * channel) {
298 // set busy and seek complete flags
299 channel->status.val = 0x90;
302 channel->error_reg.val = 0x01;
305 channel->cmd_reg = 0x00;
307 channel->ctrl_reg.irq_disable = 0;
310 static void channel_reset_complete(struct ide_channel * channel) {
311 channel->status.busy = 0;
312 channel->status.ready = 1;
314 channel->drive_head.head_num = 0;
316 drive_reset(&(channel->drives[0]));
317 drive_reset(&(channel->drives[1]));
321 static void ide_abort_command(struct vm_device * dev, struct ide_channel * channel) {
322 channel->status.val = 0x41; // Error + ready
323 channel->error_reg.val = 0x04; // No idea...
325 ide_raise_irq(dev, channel);
329 // Include the ATAPI interface handlers
334 static int dma_read(struct vm_device * dev, struct ide_channel * channel) {
335 struct ide_drive * drive = get_selected_drive(channel);
336 struct ide_dma_prd prd_entry;
337 uint32_t prd_entry_addr = channel->dma_prd_addr + (sizeof(struct ide_dma_prd) * channel->dma_tbl_index);
341 PrintDebug("PRD table address = %x\n", channel->dma_prd_addr);
343 ret = read_guest_pa_memory(dev->vm, prd_entry_addr, sizeof(struct ide_dma_prd), (void *)&prd_entry);
345 if (ret != sizeof(struct ide_dma_prd)) {
346 PrintError("Could not read PRD\n");
350 PrintDebug("PRD Addr: %x, PDR Len: %d, EOT: %d\n", prd_entry.base_addr, prd_entry.size, prd_entry.end_of_table);
352 ret = write_guest_pa_memory(dev->vm, prd_entry.base_addr, prd_entry.size, drive->data_buf);
354 if (ret != prd_entry.size) {
355 PrintError("Failed to copy data into guest memory... (ret=%d)\n", ret);
359 channel->status.busy = 0;
360 channel->status.ready = 1;
361 channel->status.data_req = 0;
362 channel->status.error = 0;
363 channel->status.seek_complete = 1;
366 drive->irq_flags.io_dir = 1;
367 drive->irq_flags.c_d = 1;
368 drive->irq_flags.rel = 0;
373 channel->dma_status.active = 0;
374 channel->dma_status.err = 1;
375 channel->dma_status.int_gen = 1;
377 ide_raise_irq(dev, channel);
383 static int dma_write(struct vm_device * dev, struct ide_channel * channel) {
385 PrintError("DMA writes currently not supported\n");
391 * This is an ugly ugly ugly way to differentiate between the first and second DMA channels
394 static int write_dma_port(ushort_t port_offset, void * src, uint_t length, struct vm_device * dev, struct ide_channel * channel);
395 static int read_dma_port(ushort_t port_offset, void * dst, uint_t length, struct vm_device * dev, struct ide_channel * channel);
398 static int write_pri_dma_port(ushort_t port, void * src, uint_t length, struct vm_device * dev) {
399 struct ide_internal * ide = (struct ide_internal *)(dev->private_data);
400 PrintDebug("IDE: Writing PRI DMA Port %x (%s) (val=%x)\n", port, dma_port_to_str(port & 0x7), *(uint32_t *)src);
401 return write_dma_port(port & 0x7, src, length, dev, &(ide->channels[0]));
404 static int write_sec_dma_port(ushort_t port, void * src, uint_t length, struct vm_device * dev) {
405 struct ide_internal * ide = (struct ide_internal *)(dev->private_data);
406 PrintDebug("IDE: Writing SEC DMA Port %x (%s) (val=%x)\n", port, dma_port_to_str(port & 0x7), *(uint32_t *)src);
407 return write_dma_port(port & 0x7, src, length, dev, &(ide->channels[1]));
411 static int read_pri_dma_port(ushort_t port, void * dst, uint_t length, struct vm_device * dev) {
412 struct ide_internal * ide = (struct ide_internal *)(dev->private_data);
413 PrintDebug("IDE: Reading PRI DMA Port %x (%s)\n", port, dma_port_to_str(port & 0x7));
414 return read_dma_port(port & 0x7, dst, length, dev, &(ide->channels[0]));
417 static int read_sec_dma_port(ushort_t port, void * dst, uint_t length, struct vm_device * dev) {
418 struct ide_internal * ide = (struct ide_internal *)(dev->private_data);
419 PrintDebug("IDE: Reading SEC DMA Port %x (%s)\n", port, dma_port_to_str(port & 0x7));
420 return read_dma_port(port & 0x7, dst, length, dev, &(ide->channels[1]));
424 #define DMA_CMD_PORT 0x00
425 #define DMA_STATUS_PORT 0x02
426 #define DMA_PRD_PORT0 0x04
427 #define DMA_PRD_PORT1 0x05
428 #define DMA_PRD_PORT2 0x06
429 #define DMA_PRD_PORT3 0x07
432 static int write_dma_port(ushort_t port_offset, void * src, uint_t length,
433 struct vm_device * dev, struct ide_channel * channel) {
435 switch (port_offset) {
437 channel->dma_cmd.val = *(uint8_t *)src;
439 if (channel->dma_cmd.start == 0) {
440 channel->dma_tbl_index = 0;
442 channel->dma_status.active = 1;
444 if (channel->dma_cmd.read == 1) {
446 if (dma_read(dev, channel) == -1) {
447 PrintError("Failed DMA Read\n");
452 if (dma_write(dev, channel) == -1) {
453 PrintError("Failed DMA Write\n");
461 case DMA_STATUS_PORT:
463 PrintError("Invalid read length for DMA status port\n");
467 channel->dma_status.val = *(uint8_t *)src;
473 case DMA_PRD_PORT3: {
474 uint_t addr_index = port_offset & 0x3;
475 uint8_t * addr_buf = (uint8_t *)&(channel->dma_prd_addr);
478 if (addr_index + length > 4) {
479 PrintError("DMA Port space overrun port=%x len=%d\n", port_offset, length);
483 for (i = 0; i < length; i++) {
484 addr_buf[addr_index + i] = *((uint8_t *)src + i);
487 PrintDebug("Writing PRD Port %x (val=%x)\n", port_offset, channel->dma_prd_addr);
492 PrintError("IDE: Invalid DMA Port (%s)\n", dma_port_to_str(port_offset));
500 static int read_dma_port(ushort_t port_offset, void * dst, uint_t length,
501 struct vm_device * dev, struct ide_channel * channel) {
503 switch (port_offset) {
505 *(uint8_t *)dst = channel->dma_cmd.val;
508 case DMA_STATUS_PORT:
510 PrintError("Invalid read length for DMA status port\n");
514 *(uint8_t *)dst = channel->dma_status.val;
520 case DMA_PRD_PORT3: {
521 uint_t addr_index = port_offset & 0x3;
522 uint8_t * addr_buf = (uint8_t *)&(channel->dma_prd_addr);
525 if (addr_index + length > 4) {
526 PrintError("DMA Port space overrun port=%x len=%d\n", port_offset, length);
530 for (i = 0; i < length; i++) {
531 *((uint8_t *)dst + i) = addr_buf[addr_index + i];
537 PrintError("IDE: Invalid DMA Port (%s)\n", dma_port_to_str(port_offset));
541 PrintDebug("\tval=%x\n", *(uint32_t *)dst);
548 static int write_cmd_port(ushort_t port, void * src, uint_t length, struct vm_device * dev) {
549 struct ide_internal * ide = (struct ide_internal *)(dev->private_data);
550 struct ide_channel * channel = get_selected_channel(ide, port);
551 struct ide_drive * drive = get_selected_drive(channel);
554 PrintError("Invalid Write Length on IDE command Port %x\n", port);
558 PrintDebug("IDE: Writing Command Port %x (%s) (val=%x)\n", port, io_port_to_str(port), *(uint8_t *)src);
560 channel->cmd_reg = *(uint8_t *)src;
562 switch (channel->cmd_reg) {
564 case 0xa0: // ATAPI Command Packet
565 if (drive->drive_type != IDE_CDROM) {
566 ide_abort_command(dev, channel);
569 drive->sector_count = 1;
571 channel->status.busy = 0;
572 channel->status.write_fault = 0;
573 channel->status.data_req = 1;
574 channel->status.error = 0;
576 // reset the data buffer...
577 drive->transfer_length = ATAPI_PACKET_SIZE;
578 drive->transfer_index = 0;
581 case 0xa1: // ATAPI Identify Device Packet
582 atapi_identify_device(drive);
584 channel->error_reg.val = 0;
585 channel->status.val = 0x58; // ready, data_req, seek_complete
587 ide_raise_irq(dev, channel);
589 case 0xec: // Identify Device
590 if (drive->drive_type != IDE_DISK) {
593 // JRL: Should we abort here?
594 ide_abort_command(dev, channel);
596 PrintError("IDE Disks currently not implemented\n");
601 case 0xef: // Set Features
602 // Prior to this the features register has been written to.
603 // This command tells the drive to check if the new value is supported (the value is drive specific)
604 // Common is that bit0=DMA enable
605 // If valid the drive raises an interrupt, if not it aborts.
607 // Do some checking here...
609 channel->status.busy = 0;
610 channel->status.write_fault = 0;
611 channel->status.error = 0;
612 channel->status.ready = 1;
613 channel->status.seek_complete = 1;
615 ide_raise_irq(dev, channel);
618 PrintError("Unimplemented IDE command (%x)\n", channel->cmd_reg);
626 static int write_data_port(ushort_t port, void * src, uint_t length, struct vm_device * dev) {
627 struct ide_internal * ide = (struct ide_internal *)(dev->private_data);
628 struct ide_channel * channel = get_selected_channel(ide, port);
629 struct ide_drive * drive = get_selected_drive(channel);
631 // PrintDebug("IDE: Writing Data Port %x (val=%x, len=%d)\n",
632 // port, *(uint32_t *)src, length);
634 memcpy(drive->data_buf + drive->transfer_index, src, length);
635 drive->transfer_index += length;
637 // Transfer is complete, dispatch the command
638 if (drive->transfer_index >= drive->transfer_length) {
639 switch (channel->cmd_reg) {
640 case 0x30: // Write Sectors
641 PrintError("Writing Data not yet implemented\n");
644 case 0xa0: // ATAPI packet command
645 if (atapi_handle_packet(dev, channel) == -1) {
646 PrintError("Error handling ATAPI packet\n");
651 PrintError("Unhandld IDE Command %x\n", channel->cmd_reg);
660 static int read_hd_data(uint8_t * dst, uint_t length, struct vm_device * dev, struct ide_channel * channel) {
661 PrintError("Harddrive data port read not implemented\n");
667 static int read_cd_data(uint8_t * dst, uint_t length, struct vm_device * dev, struct ide_channel * channel) {
668 struct ide_drive * drive = get_selected_drive(channel);
669 int data_offset = drive->transfer_index % DATA_BUFFER_SIZE;
670 int req_offset = drive->transfer_index % drive->req_len;
672 if (drive->cd_state.atapi_cmd != 0x28) {
673 PrintDebug("IDE: Reading CD Data (len=%d) (req_len=%d)\n", length, drive->req_len);
676 if (drive->transfer_index >= drive->transfer_length) {
677 PrintError("Buffer Overrun... (xfer_len=%d) (cur_idx=%d) (post_idx=%d)\n",
678 drive->transfer_length, drive->transfer_index,
679 drive->transfer_index + length);
685 if ((data_offset == 0) && (drive->transfer_index > 0)) {
687 if (drive->drive_type == IDE_CDROM) {
688 if (atapi_update_data_buf(dev, channel) == -1) {
689 PrintError("Could not update CDROM data buffer\n");
693 PrintError("IDE Harddrives not implemented\n");
698 memcpy(dst, drive->data_buf + data_offset, length);
700 drive->transfer_index += length;
702 if ((req_offset == 0) && (drive->transfer_index > 0)) {
703 if (drive->transfer_index < drive->transfer_length) {
704 // An increment is complete, but there is still more data to be transferred...
706 channel->status.data_req = 1;
708 drive->irq_flags.c_d = 0;
710 // Update the request length in the cylinder regs
711 if (atapi_update_req_len(dev, channel, drive->transfer_length - drive->transfer_index) == -1) {
712 PrintError("Could not update request length after completed increment\n");
716 // This was the final read of the request
717 channel->status.data_req = 0;
718 channel->status.ready = 1;
720 drive->irq_flags.c_d = 1;
721 drive->irq_flags.rel = 0;
724 drive->irq_flags.io_dir = 1;
725 channel->status.busy = 0;
727 ide_raise_irq(dev, channel);
734 static int read_drive_id(uint8_t * dst, uint_t length, struct vm_device * dev, struct ide_channel * channel) {
735 struct ide_drive * drive = get_selected_drive(channel);
737 channel->status.busy = 0;
738 channel->status.ready = 1;
739 channel->status.write_fault = 0;
740 channel->status.seek_complete = 1;
741 channel->status.corrected = 0;
742 channel->status.error = 0;
745 memcpy(dst, drive->data_buf + drive->transfer_index, length);
746 drive->transfer_index += length;
748 if (drive->transfer_index >= drive->transfer_length) {
749 channel->status.data_req = 0;
756 static int ide_read_data_port(ushort_t port, void * dst, uint_t length, struct vm_device * dev) {
757 struct ide_internal * ide = (struct ide_internal *)(dev->private_data);
758 struct ide_channel * channel = get_selected_channel(ide, port);
759 struct ide_drive * drive = get_selected_drive(channel);
761 // PrintDebug("IDE: Reading Data Port %x (len=%d)\n", port, length);
763 if ((channel->cmd_reg == 0xec) ||
764 (channel->cmd_reg == 0xa1)) {
765 return read_drive_id((uint8_t *)dst, length, dev, channel);
768 if (drive->drive_type == IDE_CDROM) {
769 if (read_cd_data((uint8_t *)dst, length, dev, channel) == -1) {
770 PrintError("IDE: Could not read CD Data\n");
773 } else if (drive->drive_type == IDE_DISK) {
774 if (read_hd_data((uint8_t *)dst, length, dev, channel) == -1) {
775 PrintError("IDE: Could not read HD Data\n");
779 memset((uint8_t *)dst, 0, length);
785 static int write_port_std(ushort_t port, void * src, uint_t length, struct vm_device * dev) {
786 struct ide_internal * ide = (struct ide_internal *)(dev->private_data);
787 struct ide_channel * channel = get_selected_channel(ide, port);
788 struct ide_drive * drive = get_selected_drive(channel);
791 PrintError("Invalid Write length on IDE port %x\n", port);
795 PrintDebug("IDE: Writing Standard Port %x (%s) (val=%x)\n", port, io_port_to_str(port), *(uint8_t *)src);
798 // reset and interrupt enable
800 case SEC_CTRL_PORT: {
801 struct ide_ctrl_reg * tmp_ctrl = (struct ide_ctrl_reg *)src;
803 // only reset channel on a 0->1 reset bit transition
804 if ((!channel->ctrl_reg.soft_reset) && (tmp_ctrl->soft_reset)) {
805 channel_reset(channel);
806 } else if ((channel->ctrl_reg.soft_reset) && (!tmp_ctrl->soft_reset)) {
807 channel_reset_complete(channel);
810 channel->ctrl_reg.val = tmp_ctrl->val;
813 case PRI_FEATURES_PORT:
814 case SEC_FEATURES_PORT:
815 channel->features.val = *(uint8_t *)src;
818 case PRI_SECT_CNT_PORT:
819 case SEC_SECT_CNT_PORT:
820 drive->sector_count = *(uint8_t *)src;
823 case PRI_SECT_NUM_PORT:
824 case SEC_SECT_NUM_PORT:
825 drive->sector_num = *(uint8_t *)src;
827 case PRI_CYL_LOW_PORT:
828 case SEC_CYL_LOW_PORT:
829 drive->cylinder_low = *(uint8_t *)src;
832 case PRI_CYL_HIGH_PORT:
833 case SEC_CYL_HIGH_PORT:
834 drive->cylinder_high = *(uint8_t *)src;
837 case PRI_DRV_SEL_PORT:
838 case SEC_DRV_SEL_PORT: {
839 channel->drive_head.val = *(uint8_t *)src;
841 // make sure the reserved bits are ok..
842 // JRL TODO: check with new ramdisk to make sure this is right...
843 channel->drive_head.val |= 0xa0;
845 drive = get_selected_drive(channel);
847 // Selecting a non-present device is a no-no
848 if (drive->drive_type == IDE_NONE) {
849 PrintDebug("Attempting to select a non-present drive\n");
850 channel->error_reg.abort = 1;
851 channel->status.error = 1;
857 PrintError("IDE: Write to unknown Port %x\n", port);
864 static int read_port_std(ushort_t port, void * dst, uint_t length, struct vm_device * dev) {
865 struct ide_internal * ide = (struct ide_internal *)(dev->private_data);
866 struct ide_channel * channel = get_selected_channel(ide, port);
867 struct ide_drive * drive = get_selected_drive(channel);
870 PrintError("Invalid Read length on IDE port %x\n", port);
874 PrintDebug("IDE: Reading Standard Port %x (%s)\n", port, io_port_to_str(port));
876 if ((port == PRI_ADDR_REG_PORT) ||
877 (port == SEC_ADDR_REG_PORT)) {
878 // unused, return 0xff
879 *(uint8_t *)dst = 0xff;
884 // if no drive is present just return 0 + reserved bits
885 if (drive->drive_type == IDE_NONE) {
886 if ((port == PRI_DRV_SEL_PORT) ||
887 (port == SEC_DRV_SEL_PORT)) {
888 *(uint8_t *)dst = 0xa0;
898 // This is really the error register.
899 case PRI_FEATURES_PORT:
900 case SEC_FEATURES_PORT:
901 *(uint8_t *)dst = channel->error_reg.val;
904 case PRI_SECT_CNT_PORT:
905 case SEC_SECT_CNT_PORT:
906 *(uint8_t *)dst = drive->sector_count;
909 case PRI_SECT_NUM_PORT:
910 case SEC_SECT_NUM_PORT:
911 *(uint8_t *)dst = drive->sector_num;
914 case PRI_CYL_LOW_PORT:
915 case SEC_CYL_LOW_PORT:
916 *(uint8_t *)dst = drive->cylinder_low;
920 case PRI_CYL_HIGH_PORT:
921 case SEC_CYL_HIGH_PORT:
922 *(uint8_t *)dst = drive->cylinder_high;
925 case PRI_DRV_SEL_PORT:
926 case SEC_DRV_SEL_PORT: // hard disk drive and head register 0x1f6
927 *(uint8_t *)dst = channel->drive_head.val;
934 // Something about lowering interrupts here....
935 *(uint8_t *)dst = channel->status.val;
939 PrintError("Invalid Port: %x\n", port);
943 PrintDebug("\tVal=%x\n", *(uint8_t *)dst);
950 static void init_drive(struct ide_drive * drive) {
952 drive->sector_count = 0x01;
953 drive->sector_num = 0x01;
954 drive->cylinder = 0x0000;
956 drive->drive_type = IDE_NONE;
958 memset(drive->model, 0, sizeof(drive->model));
960 drive->transfer_index = 0;
961 drive->transfer_length = 0;
962 memset(drive->data_buf, 0, sizeof(drive->data_buf));
966 drive->private_data = NULL;
967 drive->cd_ops = NULL;
970 static void init_channel(struct ide_channel * channel) {
973 channel->error_reg.val = 0x01;
974 channel->drive_head.val = 0x00;
975 channel->status.val = 0x00;
976 channel->cmd_reg = 0x00;
977 channel->ctrl_reg.val = 0x08;
980 channel->dma_cmd.val = 0;
981 channel->dma_status.val = 0;
982 channel->dma_prd_addr = 0;
983 channel->dma_tbl_index = 0;
985 for (i = 0; i < 2; i++) {
986 init_drive(&(channel->drives[i]));
992 static int pci_config_update(struct pci_device * pci_dev, uint_t reg_num, int length) {
993 PrintDebug("Interupt register (Dev=%s), irq=%d\n", pci_dev->name, pci_dev->config_header.intr_line);
998 static int init_ide_state(struct vm_device * dev) {
999 struct ide_internal * ide = (struct ide_internal *)(dev->private_data);
1000 struct v3_pci_bar bars[6];
1001 struct pci_device * pci_dev = NULL;
1004 for (i = 0; i < 2; i++) {
1005 init_channel(&(ide->channels[i]));
1007 // JRL: this is a terrible hack...
1008 ide->channels[i].irq = PRI_DEFAULT_IRQ + i;
1010 for (j = 0; j < 6; j++) {
1011 bars[j].type = PCI_BAR_NONE;
1015 bars[4].type = PCI_BAR_IO;
1016 bars[4].default_base_port = PRI_DEFAULT_DMA_PORT + (i * 0x8);
1017 bars[4].num_ports = 8;
1020 bars[4].io_read = read_pri_dma_port;
1021 bars[4].io_write = write_pri_dma_port;
1023 bars[4].io_read = read_sec_dma_port;
1024 bars[4].io_write = write_sec_dma_port;
1027 pci_dev = v3_pci_register_device(ide->pci, PCI_STD_DEVICE, 0, "V3_IDE", -1, bars,
1028 pci_config_update, NULL, NULL, dev);
1030 if (pci_dev == NULL) {
1031 PrintError("Failed to register IDE BUS %d with PCI\n", i);
1035 ide->channels[i].pci_dev = pci_dev;
1037 pci_dev->config_header.vendor_id = 0x1095;
1038 pci_dev->config_header.device_id = 0x0646;
1039 pci_dev->config_header.revision = 0x8f07;
1040 pci_dev->config_header.subclass = 0x01;
1041 pci_dev->config_header.class = 0x01;
1043 pci_dev->config_header.intr_line = PRI_DEFAULT_IRQ + i;
1044 pci_dev->config_header.intr_pin = 1;
1049 /* Register PIIX3 Busmaster PCI device */
1050 for (j = 0; j < 6; j++) {
1051 bars[j].type = PCI_BAR_NONE;
1054 pci_dev = v3_pci_register_device(ide->pci, PCI_STD_DEVICE, 0, "PIIX3 IDE", -1, bars,
1055 NULL, NULL, NULL, dev);
1058 ide->busmaster_pci = pci_dev;
1060 pci_dev->config_header.vendor_id = 0x8086;
1061 pci_dev->config_header.device_id = 0x7010;
1062 pci_dev->config_header.revision = 0x80;
1063 pci_dev->config_header.subclass = 0x01;
1064 pci_dev->config_header.class = 0x01;
1072 static int init_ide(struct vm_device * dev) {
1073 //struct ide_internal * ide = (struct ide_internal *)(dev->private_data);
1075 PrintDebug("IDE: Initializing IDE\n");
1077 if (init_ide_state(dev) == -1) {
1078 PrintError("Failed to initialize IDE state\n");
1083 v3_dev_hook_io(dev, PRI_DATA_PORT,
1084 &ide_read_data_port, &write_data_port);
1085 v3_dev_hook_io(dev, PRI_FEATURES_PORT,
1086 &read_port_std, &write_port_std);
1087 v3_dev_hook_io(dev, PRI_SECT_CNT_PORT,
1088 &read_port_std, &write_port_std);
1089 v3_dev_hook_io(dev, PRI_SECT_NUM_PORT,
1090 &read_port_std, &write_port_std);
1091 v3_dev_hook_io(dev, PRI_CYL_LOW_PORT,
1092 &read_port_std, &write_port_std);
1093 v3_dev_hook_io(dev, PRI_CYL_HIGH_PORT,
1094 &read_port_std, &write_port_std);
1095 v3_dev_hook_io(dev, PRI_DRV_SEL_PORT,
1096 &read_port_std, &write_port_std);
1097 v3_dev_hook_io(dev, PRI_CMD_PORT,
1098 &read_port_std, &write_cmd_port);
1100 v3_dev_hook_io(dev, SEC_DATA_PORT,
1101 &ide_read_data_port, &write_data_port);
1102 v3_dev_hook_io(dev, SEC_FEATURES_PORT,
1103 &read_port_std, &write_port_std);
1104 v3_dev_hook_io(dev, SEC_SECT_CNT_PORT,
1105 &read_port_std, &write_port_std);
1106 v3_dev_hook_io(dev, SEC_SECT_NUM_PORT,
1107 &read_port_std, &write_port_std);
1108 v3_dev_hook_io(dev, SEC_CYL_LOW_PORT,
1109 &read_port_std, &write_port_std);
1110 v3_dev_hook_io(dev, SEC_CYL_HIGH_PORT,
1111 &read_port_std, &write_port_std);
1112 v3_dev_hook_io(dev, SEC_DRV_SEL_PORT,
1113 &read_port_std, &write_port_std);
1114 v3_dev_hook_io(dev, SEC_CMD_PORT,
1115 &read_port_std, &write_cmd_port);
1118 v3_dev_hook_io(dev, PRI_CTRL_PORT,
1119 &read_port_std, &write_port_std);
1121 v3_dev_hook_io(dev, SEC_CTRL_PORT,
1122 &read_port_std, &write_port_std);
1125 v3_dev_hook_io(dev, SEC_ADDR_REG_PORT,
1126 &read_port_std, &write_port_std);
1128 v3_dev_hook_io(dev, PRI_ADDR_REG_PORT,
1129 &read_port_std, &write_port_std);
1135 static int deinit_ide(struct vm_device * dev) {
1136 // unhook io ports....
1137 // deregister from PCI?
1142 static struct vm_device_ops dev_ops = {
1144 .deinit = deinit_ide,
1151 struct vm_device * v3_create_ide(struct vm_device * pci) {
1152 struct ide_internal * ide = (struct ide_internal *)V3_Malloc(sizeof(struct ide_internal));
1153 struct vm_device * device = v3_create_device("IDE", &dev_ops, ide);
1157 PrintDebug("IDE: Creating IDE bus x 2\n");
1166 int v3_ide_register_cdrom(struct vm_device * ide_dev,
1170 struct v3_ide_cd_ops * ops,
1171 void * private_data) {
1173 struct ide_internal * ide = (struct ide_internal *)(ide_dev->private_data);
1174 struct ide_channel * channel = NULL;
1175 struct ide_drive * drive = NULL;
1177 V3_ASSERT((bus_num >= 0) && (bus_num < 2));
1178 V3_ASSERT((drive_num >= 0) && (drive_num < 2));
1180 channel = &(ide->channels[bus_num]);
1181 drive = &(channel->drives[drive_num]);
1183 if (drive->drive_type != IDE_NONE) {
1184 PrintError("Device slot (bus=%d, drive=%d) already occupied\n", bus_num, drive_num);
1188 strncpy(drive->model, dev_name, sizeof(drive->model) - 1);
1190 while (strlen((char *)(drive->model)) < 40) {
1191 strcat((char*)(drive->model), " ");
1195 drive->drive_type = IDE_CDROM;
1197 drive->cd_ops = ops;
1199 drive->private_data = private_data;
1205 int v3_ide_register_harddisk(struct vm_device * ide_dev,
1209 struct v3_ide_hd_ops * ops,
1210 void * private_data) {
1212 struct ide_internal * ide = (struct ide_internal *)(ide_dev->private_data);
1213 struct ide_channel * channel = NULL;
1214 struct ide_drive * drive = NULL;
1216 V3_ASSERT((bus_num >= 0) && (bus_num < 2));
1217 V3_ASSERT((drive_num >= 0) && (drive_num < 2));
1219 channel = &(ide->channels[bus_num]);
1220 drive = &(channel->drives[drive_num]);
1222 if (drive->drive_type != IDE_NONE) {
1223 PrintError("Device slot (bus=%d, drive=%d) already occupied\n", bus_num, drive_num);
1227 strncpy(drive->model, dev_name, sizeof(drive->model) - 1);
1229 drive->drive_type = IDE_DISK;
1231 drive->hd_ops = ops;
1233 drive->private_data = private_data;