2 * This file is part of the Palacios Virtual Machine Monitor developed
3 * by the V3VEE Project with funding from the United States National
4 * Science Foundation and the Department of Energy.
6 * The V3VEE Project is a joint project between Northwestern University
7 * and the University of New Mexico. You can find out more at
10 * Copyright (c) 2008, Jack Lange <jarusl@cs.northwestern.edu>
11 * Copyright (c) 2008, The V3VEE Project <http://www.v3vee.org>
12 * All rights reserved.
14 * Author: Jack Lange <jarusl@cs.northwestern.edu>
16 * This is free software. You are permitted to use,
17 * redistribute, and modify it as specified in the file "V3VEE_LICENSE".
21 #include <devices/apic.h>
22 #include <devices/apic_regs.h>
23 #include <palacios/vmm.h>
24 #include <palacios/vmm_msr.h>
25 #include <palacios/vmm_sprintf.h>
26 #include <palacios/vm_guest.h>
27 #include <palacios/vmm_types.h>
30 #ifndef CONFIG_DEBUG_APIC
32 #define PrintDebug(fmt, args...)
35 #ifdef CONFIG_DEBUG_APIC
36 static char *shorthand_str[] = {
43 static char *deliverymode_str[] = {
55 typedef enum { APIC_TMR_INT, APIC_THERM_INT, APIC_PERF_INT,
56 APIC_LINT0_INT, APIC_LINT1_INT, APIC_ERR_INT } apic_irq_type_t;
58 #define APIC_FIXED_DELIVERY 0x0
59 #define APIC_SMI_DELIVERY 0x2
60 #define APIC_NMI_DELIVERY 0x4
61 #define APIC_INIT_DELIVERY 0x5
62 #define APIC_EXTINT_DELIVERY 0x7
65 #define BASE_ADDR_MSR 0x0000001B
66 #define DEFAULT_BASE_ADDR 0xfee00000
68 #define APIC_ID_OFFSET 0x020
69 #define APIC_VERSION_OFFSET 0x030
70 #define TPR_OFFSET 0x080
71 #define APR_OFFSET 0x090
72 #define PPR_OFFSET 0x0a0
73 #define EOI_OFFSET 0x0b0
74 #define REMOTE_READ_OFFSET 0x0c0
75 #define LDR_OFFSET 0x0d0
76 #define DFR_OFFSET 0x0e0
77 #define SPURIOUS_INT_VEC_OFFSET 0x0f0
79 #define ISR_OFFSET0 0x100 // 0x100 - 0x170
80 #define ISR_OFFSET1 0x110 // 0x100 - 0x170
81 #define ISR_OFFSET2 0x120 // 0x100 - 0x170
82 #define ISR_OFFSET3 0x130 // 0x100 - 0x170
83 #define ISR_OFFSET4 0x140 // 0x100 - 0x170
84 #define ISR_OFFSET5 0x150 // 0x100 - 0x170
85 #define ISR_OFFSET6 0x160 // 0x100 - 0x170
86 #define ISR_OFFSET7 0x170 // 0x100 - 0x170
88 #define TRIG_OFFSET0 0x180 // 0x180 - 0x1f0
89 #define TRIG_OFFSET1 0x190 // 0x180 - 0x1f0
90 #define TRIG_OFFSET2 0x1a0 // 0x180 - 0x1f0
91 #define TRIG_OFFSET3 0x1b0 // 0x180 - 0x1f0
92 #define TRIG_OFFSET4 0x1c0 // 0x180 - 0x1f0
93 #define TRIG_OFFSET5 0x1d0 // 0x180 - 0x1f0
94 #define TRIG_OFFSET6 0x1e0 // 0x180 - 0x1f0
95 #define TRIG_OFFSET7 0x1f0 // 0x180 - 0x1f0
98 #define IRR_OFFSET0 0x200 // 0x200 - 0x270
99 #define IRR_OFFSET1 0x210 // 0x200 - 0x270
100 #define IRR_OFFSET2 0x220 // 0x200 - 0x270
101 #define IRR_OFFSET3 0x230 // 0x200 - 0x270
102 #define IRR_OFFSET4 0x240 // 0x200 - 0x270
103 #define IRR_OFFSET5 0x250 // 0x200 - 0x270
104 #define IRR_OFFSET6 0x260 // 0x200 - 0x270
105 #define IRR_OFFSET7 0x270 // 0x200 - 0x270
108 #define ESR_OFFSET 0x280
109 #define INT_CMD_LO_OFFSET 0x300
110 #define INT_CMD_HI_OFFSET 0x310
111 #define TMR_LOC_VEC_TBL_OFFSET 0x320
112 #define THERM_LOC_VEC_TBL_OFFSET 0x330
113 #define PERF_CTR_LOC_VEC_TBL_OFFSET 0x340
114 #define LINT0_VEC_TBL_OFFSET 0x350
115 #define LINT1_VEC_TBL_OFFSET 0x360
116 #define ERR_VEC_TBL_OFFSET 0x370
117 #define TMR_INIT_CNT_OFFSET 0x380
118 #define TMR_CUR_CNT_OFFSET 0x390
119 #define TMR_DIV_CFG_OFFSET 0x3e0
120 #define EXT_APIC_FEATURE_OFFSET 0x400
121 #define EXT_APIC_CMD_OFFSET 0x410
122 #define SEOI_OFFSET 0x420
124 #define IER_OFFSET0 0x480 // 0x480 - 0x4f0
125 #define IER_OFFSET1 0x490 // 0x480 - 0x4f0
126 #define IER_OFFSET2 0x4a0 // 0x480 - 0x4f0
127 #define IER_OFFSET3 0x4b0 // 0x480 - 0x4f0
128 #define IER_OFFSET4 0x4c0 // 0x480 - 0x4f0
129 #define IER_OFFSET5 0x4d0 // 0x480 - 0x4f0
130 #define IER_OFFSET6 0x4e0 // 0x480 - 0x4f0
131 #define IER_OFFSET7 0x4f0 // 0x480 - 0x4f0
133 #define EXT_INT_LOC_VEC_TBL_OFFSET0 0x500 // 0x500 - 0x530
134 #define EXT_INT_LOC_VEC_TBL_OFFSET1 0x510 // 0x500 - 0x530
135 #define EXT_INT_LOC_VEC_TBL_OFFSET2 0x520 // 0x500 - 0x530
136 #define EXT_INT_LOC_VEC_TBL_OFFSET3 0x530 // 0x500 - 0x530
147 uint8_t bootstrap_cpu : 1;
149 uint8_t apic_enable : 1;
150 uint64_t base_addr : 40;
152 } __attribute__((packed));
153 } __attribute__((packed));
154 } __attribute__((packed));
158 typedef enum {INIT, SIPI, STARTED} ipi_state_t;
160 struct apic_dev_state;
166 struct apic_msr base_addr_msr;
169 /* memory map registers */
171 struct lapic_id_reg lapic_id;
172 struct apic_ver_reg apic_ver;
173 struct ext_apic_ctrl_reg ext_apic_ctrl;
174 struct local_vec_tbl_reg local_vec_tbl;
175 struct tmr_vec_tbl_reg tmr_vec_tbl;
176 struct tmr_div_cfg_reg tmr_div_cfg;
177 struct lint_vec_tbl_reg lint0_vec_tbl;
178 struct lint_vec_tbl_reg lint1_vec_tbl;
179 struct perf_ctr_loc_vec_tbl_reg perf_ctr_loc_vec_tbl;
180 struct therm_loc_vec_tbl_reg therm_loc_vec_tbl;
181 struct err_vec_tbl_reg err_vec_tbl;
182 struct err_status_reg err_status;
183 struct spurious_int_reg spurious_int;
184 struct int_cmd_reg int_cmd;
185 struct log_dst_reg log_dst;
186 struct dst_fmt_reg dst_fmt;
187 struct arb_prio_reg arb_prio;
188 struct task_prio_reg task_prio;
189 struct proc_prio_reg proc_prio;
190 struct ext_apic_feature_reg ext_apic_feature;
191 struct spec_eoi_reg spec_eoi;
194 uint32_t tmr_cur_cnt;
195 uint32_t tmr_init_cnt;
198 struct local_vec_tbl_reg ext_intr_vec_tbl[4];
200 uint32_t rem_rd_data;
203 ipi_state_t ipi_state;
205 uint8_t int_req_reg[32];
206 uint8_t int_svc_reg[32];
207 uint8_t int_en_reg[32];
208 uint8_t trig_mode_reg[32];
210 struct guest_info * core;
220 struct apic_dev_state {
223 struct apic_state apics[0];
224 } __attribute__((packed));
228 static int apic_read(struct guest_info * core, addr_t guest_addr, void * dst, uint_t length, void * priv_data);
229 static int apic_write(struct guest_info * core, addr_t guest_addr, void * src, uint_t length, void * priv_data);
231 static void init_apic_state(struct apic_state * apic, uint32_t id) {
232 apic->base_addr = DEFAULT_BASE_ADDR;
235 // boot processor, enabled
236 apic->base_addr_msr.value = 0x0000000000000900LL;
238 // ap processor, enabled
239 apic->base_addr_msr.value = 0x0000000000000800LL;
242 // same base address regardless of ap or main
243 apic->base_addr_msr.value |= ((uint64_t)DEFAULT_BASE_ADDR);
245 PrintDebug("apic %u: (init_apic_state): msr=0x%llx\n",id, apic->base_addr_msr.value);
247 PrintDebug("apic %u: (init_apic_state): Sizeof Interrupt Request Register %d, should be 32\n",
248 id, (uint_t)sizeof(apic->int_req_reg));
250 memset(apic->int_req_reg, 0, sizeof(apic->int_req_reg));
251 memset(apic->int_svc_reg, 0, sizeof(apic->int_svc_reg));
252 memset(apic->int_en_reg, 0xff, sizeof(apic->int_en_reg));
253 memset(apic->trig_mode_reg, 0, sizeof(apic->trig_mode_reg));
255 apic->eoi = 0x00000000;
256 apic->rem_rd_data = 0x00000000;
257 apic->tmr_init_cnt = 0x00000000;
258 apic->tmr_cur_cnt = 0x00000000;
260 apic->lapic_id.val = id;
262 apic->ipi_state = INIT;
264 // The P6 has 6 LVT entries, so we set the value to (6-1)...
265 apic->apic_ver.val = 0x80050010;
267 apic->task_prio.val = 0x00000000;
268 apic->arb_prio.val = 0x00000000;
269 apic->proc_prio.val = 0x00000000;
270 apic->log_dst.val = 0x00000000;
271 apic->dst_fmt.val = 0xffffffff;
272 apic->spurious_int.val = 0x000000ff;
273 apic->err_status.val = 0x00000000;
274 apic->int_cmd.val = 0x0000000000000000LL;
275 apic->tmr_vec_tbl.val = 0x00010000;
276 apic->therm_loc_vec_tbl.val = 0x00010000;
277 apic->perf_ctr_loc_vec_tbl.val = 0x00010000;
278 apic->lint0_vec_tbl.val = 0x00010000;
279 apic->lint1_vec_tbl.val = 0x00010000;
280 apic->err_vec_tbl.val = 0x00010000;
281 apic->tmr_div_cfg.val = 0x00000000;
282 //apic->ext_apic_feature.val = 0x00000007;
283 apic->ext_apic_feature.val = 0x00040007;
284 apic->ext_apic_ctrl.val = 0x00000000;
285 apic->spec_eoi.val = 0x00000000;
287 v3_lock_init(&(apic->lock));
293 static int read_apic_msr(struct guest_info * core, uint_t msr, v3_msr_t * dst, void * priv_data) {
294 struct apic_dev_state * apic_dev = (struct apic_dev_state *)priv_data;
295 struct apic_state * apic = &(apic_dev->apics[core->cpu_id]);
297 PrintDebug("apic %u: core %u: MSR read\n", apic->lapic_id.val, core->cpu_id);
299 dst->value = apic->base_addr;
300 v3_unlock(apic->lock);
305 static int write_apic_msr(struct guest_info * core, uint_t msr, v3_msr_t src, void * priv_data) {
306 struct apic_dev_state * apic_dev = (struct apic_dev_state *)priv_data;
307 struct apic_state * apic = &(apic_dev->apics[core->cpu_id]);
308 struct v3_mem_region * old_reg = v3_get_mem_region(core->vm_info, core->cpu_id, apic->base_addr);
311 PrintDebug("apic %u: core %u: MSR write\n", apic->lapic_id.val, core->cpu_id);
313 if (old_reg == NULL) {
315 PrintError("apic %u: core %u: APIC Base address region does not exit...\n",
316 apic->lapic_id.val, core->cpu_id);
322 v3_delete_mem_region(core->vm_info, old_reg);
324 apic->base_addr = src.value;
326 if (v3_hook_full_mem(core->vm_info, core->cpu_id, apic->base_addr, apic->base_addr + PAGE_SIZE_4KB, apic_read, apic_write, apic_dev) == -1) {
327 PrintError("apic %u: core %u: Could not hook new APIC Base address\n",
328 apic->lapic_id.val, core->cpu_id);
329 v3_unlock(apic->lock);
333 v3_unlock(apic->lock);
338 // irq_num is the bit offset into a 256 bit buffer...
339 static int activate_apic_irq(struct apic_state * apic, uint32_t irq_num) {
340 int major_offset = (irq_num & ~0x00000007) >> 3;
341 int minor_offset = irq_num & 0x00000007;
342 uint8_t * req_location = apic->int_req_reg + major_offset;
343 uint8_t * en_location = apic->int_en_reg + major_offset;
344 uint8_t flag = 0x1 << minor_offset;
349 PrintError("apic %u: core ?: Attempting to raise an invalid interrupt: %d\n", apic->lapic_id.val,irq_num);
354 PrintDebug("apic %u: core ?: Raising APIC IRQ %d\n", apic->lapic_id.val, irq_num);
356 if (*req_location & flag) {
357 //V3_Print("Interrupts coallescing\n");
360 if (*en_location & flag) {
361 *req_location |= flag;
363 PrintDebug("apic %u: core ?: Interrupt not enabled... %.2x\n",
364 apic->lapic_id.val, *en_location);
373 static int get_highest_isr(struct apic_state * apic) {
376 // We iterate backwards to find the highest priority
377 for (i = 31; i >= 0; i--) {
378 uint8_t * svc_major = apic->int_svc_reg + i;
380 if ((*svc_major) & 0xff) {
381 for (j = 7; j >= 0; j--) {
382 uint8_t flag = 0x1 << j;
383 if ((*svc_major) & flag) {
384 return ((i * 8) + j);
395 static int get_highest_irr(struct apic_state * apic) {
398 // We iterate backwards to find the highest priority
399 for (i = 31; i >= 0; i--) {
400 uint8_t * req_major = apic->int_req_reg + i;
402 if ((*req_major) & 0xff) {
403 for (j = 7; j >= 0; j--) {
404 uint8_t flag = 0x1 << j;
405 if ((*req_major) & flag) {
406 return ((i * 8) + j);
418 static int apic_do_eoi(struct apic_state * apic) {
419 int isr_irq = get_highest_isr(apic);
422 int major_offset = (isr_irq & ~0x00000007) >> 3;
423 int minor_offset = isr_irq & 0x00000007;
424 uint8_t flag = 0x1 << minor_offset;
425 uint8_t * svc_location = apic->int_svc_reg + major_offset;
427 PrintDebug("apic %u: core ?: Received APIC EOI for IRQ %d\n", apic->lapic_id.val,isr_irq);
429 *svc_location &= ~flag;
431 #ifdef CONFIG_CRAY_XT
433 if ((isr_irq == 238) ||
435 PrintDebug("apic %u: core ?: Acking IRQ %d\n", apic->lapic_id.val,isr_irq);
438 if (isr_irq == 238) {
443 //PrintError("apic %u: core ?: Spurious EOI...\n",apic->lapic_id.val);
450 static int activate_internal_irq(struct apic_state * apic, apic_irq_type_t int_type) {
451 uint32_t vec_num = 0;
452 uint32_t del_mode = 0;
458 vec_num = apic->tmr_vec_tbl.vec;
459 del_mode = APIC_FIXED_DELIVERY;
460 masked = apic->tmr_vec_tbl.mask;
463 vec_num = apic->therm_loc_vec_tbl.vec;
464 del_mode = apic->therm_loc_vec_tbl.msg_type;
465 masked = apic->therm_loc_vec_tbl.mask;
468 vec_num = apic->perf_ctr_loc_vec_tbl.vec;
469 del_mode = apic->perf_ctr_loc_vec_tbl.msg_type;
470 masked = apic->perf_ctr_loc_vec_tbl.mask;
473 vec_num = apic->lint0_vec_tbl.vec;
474 del_mode = apic->lint0_vec_tbl.msg_type;
475 masked = apic->lint0_vec_tbl.mask;
478 vec_num = apic->lint1_vec_tbl.vec;
479 del_mode = apic->lint1_vec_tbl.msg_type;
480 masked = apic->lint1_vec_tbl.mask;
483 vec_num = apic->err_vec_tbl.vec;
484 del_mode = APIC_FIXED_DELIVERY;
485 masked = apic->err_vec_tbl.mask;
488 PrintError("apic %u: core ?: Invalid APIC interrupt type\n", apic->lapic_id.val);
492 // interrupt is masked, don't send
494 PrintDebug("apic %u: core ?: Inerrupt is masked\n", apic->lapic_id.val);
498 if (del_mode == APIC_FIXED_DELIVERY) {
499 //PrintDebug("Activating internal APIC IRQ %d\n", vec_num);
500 return activate_apic_irq(apic, vec_num);
502 PrintError("apic %u: core ?: Unhandled Delivery Mode\n", apic->lapic_id.val);
509 static inline int should_deliver_cluster_ipi(struct guest_info * dst_core,
510 struct apic_state * dst_apic, uint8_t mda) {
512 if ( ((mda & 0xf0) == (dst_apic->log_dst.dst_log_id & 0xf0)) && // (I am in the cluster and
513 ((mda & 0x0f) & (dst_apic->log_dst.dst_log_id & 0x0f)) ) { // I am in the set)
515 PrintDebug("apic %u core %u: accepting clustered IRQ (mda 0x%x == log_dst 0x%x)\n",
516 dst_apic->lapic_id.val, dst_core->cpu_id, mda,
517 dst_apic->log_dst.dst_log_id);
521 PrintDebug("apic %u core %u: rejecting clustered IRQ (mda 0x%x != log_dst 0x%x)\n",
522 dst_apic->lapic_id.val, dst_core->cpu_id, mda,
523 dst_apic->log_dst.dst_log_id);
528 static inline int should_deliver_flat_ipi(struct guest_info * dst_core,
529 struct apic_state * dst_apic, uint8_t mda) {
531 if (dst_apic->log_dst.dst_log_id & mda) { // I am in the set
533 PrintDebug("apic %u core %u: accepting flat IRQ (mda 0x%x == log_dst 0x%x)\n",
534 dst_apic->lapic_id.val, dst_core->cpu_id, mda,
535 dst_apic->log_dst.dst_log_id);
538 PrintDebug("apic %u core %u: rejecting flat IRQ (mda 0x%x != log_dst 0x%x)\n",
539 dst_apic->lapic_id.val, dst_core->cpu_id, mda,
540 dst_apic->log_dst.dst_log_id);
547 static int should_deliver_ipi(struct guest_info * dst_core,
548 struct apic_state * dst_apic, uint8_t mda) {
551 // always deliver broadcast
555 if (dst_apic->dst_fmt.model == 0xf) {
556 return should_deliver_cluster_ipi(dst_core, dst_apic, mda);
557 } else if (dst_apic->dst_fmt.model == 0x0) {
558 return should_deliver_flat_ipi(dst_core, dst_apic, mda);
560 PrintError("apic %u core %u: invalid destination format register value 0x%x for logical mode delivery.\n",
561 dst_apic->lapic_id.val, dst_core->cpu_id, dst_apic->dst_fmt.model);
567 static int deliver_ipi(struct guest_info * core,
568 struct apic_state * src_apic,
569 struct apic_state * dst_apic,
570 uint32_t vector, uint8_t del_mode) {
572 struct guest_info * dst_core = dst_apic->core;
577 case 1: // lowest priority
578 PrintDebug(" delivering IRQ to core %u\n", dst_core->cpu_id);
580 activate_apic_irq(dst_apic, vector);
582 if (dst_apic != src_apic) {
583 // Assume core # is same as logical processor for now
584 // TODO FIX THIS FIX THIS
585 // THERE SHOULD BE: guestapicid->virtualapicid map,
586 // cpu_id->logical processor map
587 // host maitains logical proc->phsysical proc
588 PrintDebug(" non-local core, forcing it to exit\n");
590 v3_interrupt_cpu(core->vm_info, dst_core->cpu_id, 0);
596 PrintDebug(" INIT delivery to core %u\n", dst_core->cpu_id);
598 // TODO: any APIC reset on dest core (shouldn't be needed, but not sure...)
601 if (dst_apic->ipi_state != INIT) {
602 PrintError(" Warning: core %u is not in INIT state (mode = %d), ignored\n",
603 dst_core->cpu_id, dst_core->cpu_mode);
604 // Only a warning, since INIT INIT SIPI is common
608 // We transition the target core to SIPI state
609 dst_apic->ipi_state = SIPI; // note: locking should not be needed here
611 // That should be it since the target core should be
612 // waiting in host on this transition
613 // either it's on another core or on a different preemptive thread
614 // in both cases, it will quickly notice this transition
615 // in particular, we should not need to force an exit here
617 PrintDebug(" INIT delivery done\n");
624 if (dst_apic->ipi_state != SIPI) {
625 PrintError(" core %u is not in SIPI state (mode = %d), ignored!\n",
626 dst_core->cpu_id, dst_core->cpu_mode);
630 // Write the RIP, CS, and descriptor
631 // assume the rest is already good to go
633 // vector VV -> rip at 0
635 // This means we start executing at linear address VV000
637 // So the selector needs to be VV00
638 // and the base needs to be VV000
641 dst_core->segments.cs.selector = vector << 8;
642 dst_core->segments.cs.limit = 0xffff;
643 dst_core->segments.cs.base = vector << 12;
645 PrintDebug(" SIPI delivery (0x%x -> 0x%x:0x0) to core %u\n",
646 vector, dst_core->segments.cs.selector, dst_core->cpu_id);
647 // Maybe need to adjust the APIC?
649 // We transition the target core to SIPI state
650 dst_core->core_run_state = CORE_RUNNING; // note: locking should not be needed here
651 dst_apic->ipi_state = STARTED;
653 // As with INIT, we should not need to do anything else
655 PrintDebug(" SIPI delivery done\n");
664 PrintError("IPI %d delivery is unsupported\n", del_mode);
673 static int route_ipi(struct guest_info * core, struct apic_dev_state * apic_dev,
674 struct apic_state * src_apic, uint32_t icr_val) {
675 struct int_cmd_reg * icr = (struct int_cmd_reg *)&icr_val;
676 struct apic_state * dest_apic = NULL;
678 PrintDebug("route_ipi: src_apic=%p, icr_data=%x",
682 // initial sanity checks
683 if (src_apic == NULL) {
684 PrintError("route_ipi: Apparently sending from unregistered apic id=%d\n",
685 src_apic->core->cpu_id);
690 if ((icr->dst_mode == 0) && (icr->dst >= apic_dev->num_apics)) {
691 PrintError("route_ipi: Attempted send to unregistered apic id=%u\n",
696 dest_apic = &(apic_dev->apics[icr->dst]);
699 PrintDebug("route_ipi: IPI %s %u from apic %p to %s %s %u (icr=0x%llx)\n",
700 deliverymode_str[icr->del_mode],
703 (icr->dst_mode == 0) ? "(physical)" : "(logical)",
704 shorthand_str[icr->dst_shorthand],
709 switch (icr->dst_shorthand) {
711 case 0: // no shorthand
712 if (icr->dst_mode == 0) {
715 if (deliver_ipi(core, src_apic, dest_apic,
716 icr->vec, icr->del_mode) == -1) {
717 PrintError("Error: Could not deliver IPI\n");
724 uint8_t mda = icr->dst;
726 for (i = 0; i < apic_dev->num_apics; i++) {
727 dest_apic = &(apic_dev->apics[i]);
728 int del_flag = should_deliver_ipi(dest_apic->core, dest_apic, mda);
730 if (del_flag == -1) {
731 PrintError("Error checking delivery mode\n");
733 } else if (del_flag == 1) {
734 if (deliver_ipi(core, src_apic, dest_apic,
735 icr->vec, icr->del_mode) == -1) {
736 PrintError("Error: Could not deliver IPI\n");
747 if (icr->dst_mode == 0) {
748 if (deliver_ipi(core, src_apic, src_apic, icr->vec, icr->del_mode) == -1) {
749 PrintError("Could not deliver IPI\n");
754 PrintError("icc_bus: use of logical delivery in self is not yet supported.\n");
760 case 3: { // all and all-but-me
761 // assuming that logical verus physical doesn't matter
762 // although it is odd that both are used
765 for (i = 0; i < apic_dev->num_apics; i++) {
766 dest_apic = &(apic_dev->apics[i]);
768 if ((dest_apic != src_apic) || (icr->dst_shorthand == 2)) {
769 if (deliver_ipi(core, src_apic, dest_apic, icr->vec, icr->del_mode) == -1) {
770 PrintError("Error: Could not deliver IPI\n");
779 PrintError("Error routing IPI, invalid Mode (%d)\n", icr->dst_shorthand);
789 static int apic_read(struct guest_info * core, addr_t guest_addr, void * dst, uint_t length, void * priv_data) {
790 struct apic_dev_state * apic_dev = (struct apic_dev_state *)(priv_data);
791 struct apic_state * apic = &(apic_dev->apics[core->cpu_id]);
792 addr_t reg_addr = guest_addr - apic->base_addr;
793 struct apic_msr * msr = (struct apic_msr *)&(apic->base_addr_msr.value);
797 PrintDebug("apic %u: core %u: at %p: Read apic address space (%p)\n",
798 apic->lapic_id.val, core->cpu_id, apic, (void *)guest_addr);
800 if (msr->apic_enable == 0) {
801 PrintError("apic %u: core %u: Read from APIC address space with disabled APIC, apic msr=0x%llx\n",
802 apic->lapic_id.val, core->cpu_id, apic->base_addr_msr.value);
808 /* Because "May not be supported" doesn't matter to Linux developers... */
809 /* if (length != 4) { */
810 /* PrintError("Invalid apic read length (%d)\n", length); */
814 switch (reg_addr & ~0x3) {
816 // Well, only an idiot would read from a architectural write only register
818 // PrintError("Attempting to read from write only register\n");
824 val = apic->lapic_id.val;
826 case APIC_VERSION_OFFSET:
827 val = apic->apic_ver.val;
830 val = apic->task_prio.val;
833 val = apic->arb_prio.val;
836 val = apic->proc_prio.val;
838 case REMOTE_READ_OFFSET:
839 val = apic->rem_rd_data;
842 val = apic->log_dst.val;
845 val = apic->dst_fmt.val;
847 case SPURIOUS_INT_VEC_OFFSET:
848 val = apic->spurious_int.val;
851 val = apic->err_status.val;
853 case TMR_LOC_VEC_TBL_OFFSET:
854 val = apic->tmr_vec_tbl.val;
856 case LINT0_VEC_TBL_OFFSET:
857 val = apic->lint0_vec_tbl.val;
859 case LINT1_VEC_TBL_OFFSET:
860 val = apic->lint1_vec_tbl.val;
862 case ERR_VEC_TBL_OFFSET:
863 val = apic->err_vec_tbl.val;
865 case TMR_INIT_CNT_OFFSET:
866 val = apic->tmr_init_cnt;
868 case TMR_DIV_CFG_OFFSET:
869 val = apic->tmr_div_cfg.val;
873 val = *(uint32_t *)(apic->int_en_reg);
876 val = *(uint32_t *)(apic->int_en_reg + 4);
879 val = *(uint32_t *)(apic->int_en_reg + 8);
882 val = *(uint32_t *)(apic->int_en_reg + 12);
885 val = *(uint32_t *)(apic->int_en_reg + 16);
888 val = *(uint32_t *)(apic->int_en_reg + 20);
891 val = *(uint32_t *)(apic->int_en_reg + 24);
894 val = *(uint32_t *)(apic->int_en_reg + 28);
898 val = *(uint32_t *)(apic->int_svc_reg);
901 val = *(uint32_t *)(apic->int_svc_reg + 4);
904 val = *(uint32_t *)(apic->int_svc_reg + 8);
907 val = *(uint32_t *)(apic->int_svc_reg + 12);
910 val = *(uint32_t *)(apic->int_svc_reg + 16);
913 val = *(uint32_t *)(apic->int_svc_reg + 20);
916 val = *(uint32_t *)(apic->int_svc_reg + 24);
919 val = *(uint32_t *)(apic->int_svc_reg + 28);
923 val = *(uint32_t *)(apic->trig_mode_reg);
926 val = *(uint32_t *)(apic->trig_mode_reg + 4);
929 val = *(uint32_t *)(apic->trig_mode_reg + 8);
932 val = *(uint32_t *)(apic->trig_mode_reg + 12);
935 val = *(uint32_t *)(apic->trig_mode_reg + 16);
938 val = *(uint32_t *)(apic->trig_mode_reg + 20);
941 val = *(uint32_t *)(apic->trig_mode_reg + 24);
944 val = *(uint32_t *)(apic->trig_mode_reg + 28);
948 val = *(uint32_t *)(apic->int_req_reg);
951 val = *(uint32_t *)(apic->int_req_reg + 4);
954 val = *(uint32_t *)(apic->int_req_reg + 8);
957 val = *(uint32_t *)(apic->int_req_reg + 12);
960 val = *(uint32_t *)(apic->int_req_reg + 16);
963 val = *(uint32_t *)(apic->int_req_reg + 20);
966 val = *(uint32_t *)(apic->int_req_reg + 24);
969 val = *(uint32_t *)(apic->int_req_reg + 28);
971 case TMR_CUR_CNT_OFFSET:
972 val = apic->tmr_cur_cnt;
975 // We are not going to implement these....
976 case THERM_LOC_VEC_TBL_OFFSET:
977 val = apic->therm_loc_vec_tbl.val;
979 case PERF_CTR_LOC_VEC_TBL_OFFSET:
980 val = apic->perf_ctr_loc_vec_tbl.val;
986 case INT_CMD_LO_OFFSET:
987 val = apic->int_cmd.lo;
989 case INT_CMD_HI_OFFSET:
990 val = apic->int_cmd.hi;
993 // handle current timer count
995 // Unhandled Registers
996 case EXT_INT_LOC_VEC_TBL_OFFSET0:
997 val = apic->ext_intr_vec_tbl[0].val;
999 case EXT_INT_LOC_VEC_TBL_OFFSET1:
1000 val = apic->ext_intr_vec_tbl[1].val;
1002 case EXT_INT_LOC_VEC_TBL_OFFSET2:
1003 val = apic->ext_intr_vec_tbl[2].val;
1005 case EXT_INT_LOC_VEC_TBL_OFFSET3:
1006 val = apic->ext_intr_vec_tbl[3].val;
1010 case EXT_APIC_FEATURE_OFFSET:
1011 case EXT_APIC_CMD_OFFSET:
1015 PrintError("apic %u: core %u: Read from Unhandled APIC Register: %x (getting zero)\n",
1016 apic->lapic_id.val, core->cpu_id, (uint32_t)reg_addr);
1022 uint_t byte_addr = reg_addr & 0x3;
1023 uint8_t * val_ptr = (uint8_t *)dst;
1025 *val_ptr = *(((uint8_t *)&val) + byte_addr);
1027 } else if ((length == 2) &&
1028 ((reg_addr & 0x3) == 0x3)) {
1029 uint_t byte_addr = reg_addr & 0x3;
1030 uint16_t * val_ptr = (uint16_t *)dst;
1031 *val_ptr = *(((uint16_t *)&val) + byte_addr);
1033 } else if (length == 4) {
1034 uint32_t * val_ptr = (uint32_t *)dst;
1038 PrintError("apic %u: core %u: Invalid apic read length (%d)\n",
1039 apic->lapic_id.val, core->cpu_id, length);
1043 PrintDebug("apic %u: core %u: Read finished (val=%x)\n",
1044 apic->lapic_id.val, core->cpu_id, *(uint32_t *)dst);
1053 static int apic_write(struct guest_info * core, addr_t guest_addr, void * src, uint_t length, void * priv_data) {
1054 struct apic_dev_state * apic_dev = (struct apic_dev_state *)(priv_data);
1055 struct apic_state * apic = &(apic_dev->apics[core->cpu_id]);
1056 addr_t reg_addr = guest_addr - apic->base_addr;
1057 struct apic_msr * msr = (struct apic_msr *)&(apic->base_addr_msr.value);
1058 uint32_t op_val = *(uint32_t *)src;
1060 PrintDebug("apic %u: core %u: at %p and priv_data is at %p\n",
1061 apic->lapic_id.val, core->cpu_id, apic, priv_data);
1063 PrintDebug("Write to address space (%p) (val=%x)\n",
1064 (void *)guest_addr, *(uint32_t *)src);
1066 if (msr->apic_enable == 0) {
1067 PrintError("apic %u: core %u: Write to APIC address space with disabled APIC, apic msr=0x%llx\n",
1068 apic->lapic_id.val, core->cpu_id, apic->base_addr_msr.value);
1074 PrintError("apic %u: core %u: Invalid apic write length (%d)\n",
1075 apic->lapic_id.val, length, core->cpu_id);
1080 case REMOTE_READ_OFFSET:
1081 case APIC_VERSION_OFFSET:
1108 case EXT_APIC_FEATURE_OFFSET:
1110 PrintError("apic %u: core %u: Attempting to write to read only register %p (error)\n",
1111 apic->lapic_id.val, core->cpu_id, (void *)reg_addr);
1117 case APIC_ID_OFFSET:
1118 PrintDebug("apic %u: core %u: my id is being changed to %u\n",
1119 apic->lapic_id.val, core->cpu_id, op_val);
1121 apic->lapic_id.val = op_val;
1124 apic->task_prio.val = op_val;
1127 PrintDebug("apic %u: core %u: setting log_dst.val to 0x%x\n",
1128 apic->lapic_id.val, core->cpu_id, op_val);
1129 apic->log_dst.val = op_val;
1132 apic->dst_fmt.val = op_val;
1134 case SPURIOUS_INT_VEC_OFFSET:
1135 apic->spurious_int.val = op_val;
1138 apic->err_status.val = op_val;
1140 case TMR_LOC_VEC_TBL_OFFSET:
1141 apic->tmr_vec_tbl.val = op_val;
1143 case THERM_LOC_VEC_TBL_OFFSET:
1144 apic->therm_loc_vec_tbl.val = op_val;
1146 case PERF_CTR_LOC_VEC_TBL_OFFSET:
1147 apic->perf_ctr_loc_vec_tbl.val = op_val;
1149 case LINT0_VEC_TBL_OFFSET:
1150 apic->lint0_vec_tbl.val = op_val;
1152 case LINT1_VEC_TBL_OFFSET:
1153 apic->lint1_vec_tbl.val = op_val;
1155 case ERR_VEC_TBL_OFFSET:
1156 apic->err_vec_tbl.val = op_val;
1158 case TMR_INIT_CNT_OFFSET:
1159 apic->tmr_init_cnt = op_val;
1160 apic->tmr_cur_cnt = op_val;
1162 case TMR_CUR_CNT_OFFSET:
1163 apic->tmr_cur_cnt = op_val;
1165 case TMR_DIV_CFG_OFFSET:
1166 apic->tmr_div_cfg.val = op_val;
1170 // Enable mask (256 bits)
1172 *(uint32_t *)(apic->int_en_reg) = op_val;
1175 *(uint32_t *)(apic->int_en_reg + 4) = op_val;
1178 *(uint32_t *)(apic->int_en_reg + 8) = op_val;
1181 *(uint32_t *)(apic->int_en_reg + 12) = op_val;
1184 *(uint32_t *)(apic->int_en_reg + 16) = op_val;
1187 *(uint32_t *)(apic->int_en_reg + 20) = op_val;
1190 *(uint32_t *)(apic->int_en_reg + 24) = op_val;
1193 *(uint32_t *)(apic->int_en_reg + 28) = op_val;
1196 case EXT_INT_LOC_VEC_TBL_OFFSET0:
1197 apic->ext_intr_vec_tbl[0].val = op_val;
1199 case EXT_INT_LOC_VEC_TBL_OFFSET1:
1200 apic->ext_intr_vec_tbl[1].val = op_val;
1202 case EXT_INT_LOC_VEC_TBL_OFFSET2:
1203 apic->ext_intr_vec_tbl[2].val = op_val;
1205 case EXT_INT_LOC_VEC_TBL_OFFSET3:
1206 apic->ext_intr_vec_tbl[3].val = op_val;
1216 case INT_CMD_LO_OFFSET:
1217 apic->int_cmd.lo = op_val;
1219 PrintDebug("apic %u: core %u: sending cmd 0x%llx to apic %u\n",
1220 apic->lapic_id.val, core->cpu_id,
1221 apic->int_cmd.val, apic->int_cmd.dst);
1223 if (route_ipi(core, apic_dev, apic, apic->int_cmd.val) == -1) {
1224 PrintError("IPI Routing failure\n");
1230 case INT_CMD_HI_OFFSET:
1231 apic->int_cmd.hi = op_val;
1235 // Unhandled Registers
1236 case EXT_APIC_CMD_OFFSET:
1239 PrintError("apic %u: core %u: Write to Unhandled APIC Register: %x (ignored)\n",
1240 apic->lapic_id.val, core->cpu_id, (uint32_t)reg_addr);
1245 PrintDebug("apic %u: core %u: Write finished\n", apic->lapic_id.val, core->cpu_id);
1252 /* Interrupt Controller Functions */
1254 // returns 1 if an interrupt is pending, 0 otherwise
1255 static int apic_intr_pending(struct guest_info * core, void * private_data) {
1256 struct apic_dev_state * apic_dev = (struct apic_dev_state *)(private_data);
1257 struct apic_state * apic = &(apic_dev->apics[core->cpu_id]);
1258 int req_irq = get_highest_irr(apic);
1259 int svc_irq = get_highest_isr(apic);
1261 // PrintDebug("apic %u: core %u: req_irq=%d, svc_irq=%d\n",apic->lapic_id.val,info->cpu_id,req_irq,svc_irq);
1263 if ((req_irq >= 0) &&
1264 (req_irq > svc_irq)) {
1271 static int apic_get_intr_number(struct guest_info * core, void * private_data) {
1272 struct apic_dev_state * apic_dev = (struct apic_dev_state *)(private_data);
1273 struct apic_state * apic = &(apic_dev->apics[core->cpu_id]);
1274 int req_irq = get_highest_irr(apic);
1275 int svc_irq = get_highest_isr(apic);
1277 if (svc_irq == -1) {
1279 } else if (svc_irq < req_irq) {
1287 int v3_apic_raise_intr(struct v3_vm_info * vm, struct vm_device * dev,
1288 uint32_t irq, uint32_t dst) {
1289 struct apic_dev_state * apic_dev = (struct apic_dev_state *)(dev->private_data);
1290 struct apic_state * apic = &(apic_dev->apics[dst]);
1292 PrintDebug("apic %u core ?: raising interrupt IRQ %u (dst = %u).\n", apic->lapic_id.val, irq, dst);
1294 activate_apic_irq(apic, irq);
1296 if (V3_Get_CPU() != dst) {
1297 v3_interrupt_cpu(vm, dst, 0);
1305 static int apic_begin_irq(struct guest_info * core, void * private_data, int irq) {
1306 struct apic_dev_state * apic_dev = (struct apic_dev_state *)(private_data);
1307 struct apic_state * apic = &(apic_dev->apics[core->cpu_id]);
1308 int major_offset = (irq & ~0x00000007) >> 3;
1309 int minor_offset = irq & 0x00000007;
1310 uint8_t * req_location = apic->int_req_reg + major_offset;
1311 uint8_t * svc_location = apic->int_svc_reg + major_offset;
1312 uint8_t flag = 0x01 << minor_offset;
1314 if (*req_location & flag) {
1315 // we will only pay attention to a begin irq if we
1316 // know that we initiated it!
1317 *svc_location |= flag;
1318 *req_location &= ~flag;
1321 //PrintDebug("apic %u: core %u: begin irq for %d ignored since I don't own it\n",
1322 // apic->lapic_id.val, core->cpu_id, irq);
1331 /* Timer Functions */
1332 static void apic_update_time(struct guest_info * core,
1333 uint64_t cpu_cycles, uint64_t cpu_freq,
1335 struct apic_dev_state * apic_dev = (struct apic_dev_state *)(priv_data);
1336 struct apic_state * apic = &(apic_dev->apics[core->cpu_id]);
1338 // The 32 bit GCC runtime is a pile of shit
1340 uint64_t tmr_ticks = 0;
1342 uint32_t tmr_ticks = 0;
1345 uint8_t tmr_div = *(uint8_t *)&(apic->tmr_div_cfg.val);
1346 uint_t shift_num = 0;
1349 // Check whether this is true:
1350 // -> If the Init count is zero then the timer is disabled
1351 // and doesn't just blitz interrupts to the CPU
1352 if ((apic->tmr_init_cnt == 0) ||
1353 ( (apic->tmr_vec_tbl.tmr_mode == APIC_TMR_ONESHOT) &&
1354 (apic->tmr_cur_cnt == 0))) {
1355 //PrintDebug("apic %u: core %u: APIC timer not yet initialized\n",apic->lapic_id.val,info->cpu_id);
1373 case APIC_TMR_DIV16:
1376 case APIC_TMR_DIV32:
1379 case APIC_TMR_DIV64:
1382 case APIC_TMR_DIV128:
1386 PrintError("apic %u: core %u: Invalid Timer Divider configuration\n",
1387 apic->lapic_id.val, core->cpu_id);
1391 tmr_ticks = cpu_cycles >> shift_num;
1392 // PrintDebug("Timer Ticks: %p\n", (void *)tmr_ticks);
1394 if (tmr_ticks < apic->tmr_cur_cnt) {
1395 apic->tmr_cur_cnt -= tmr_ticks;
1397 tmr_ticks -= apic->tmr_cur_cnt;
1398 apic->tmr_cur_cnt = 0;
1401 PrintDebug("apic %u: core %u: Raising APIC Timer interrupt (periodic=%d) (icnt=%d) (div=%d)\n",
1402 apic->lapic_id.val, core->cpu_id,
1403 apic->tmr_vec_tbl.tmr_mode, apic->tmr_init_cnt, shift_num);
1405 if (apic_intr_pending(core, priv_data)) {
1406 PrintDebug("apic %u: core %u: Overriding pending IRQ %d\n",
1407 apic->lapic_id.val, core->cpu_id,
1408 apic_get_intr_number(core, priv_data));
1411 if (activate_internal_irq(apic, APIC_TMR_INT) == -1) {
1412 PrintError("apic %u: core %u: Could not raise Timer interrupt\n",
1413 apic->lapic_id.val, core->cpu_id);
1416 if (apic->tmr_vec_tbl.tmr_mode == APIC_TMR_PERIODIC) {
1417 tmr_ticks = tmr_ticks % apic->tmr_init_cnt;
1418 apic->tmr_cur_cnt = apic->tmr_init_cnt - tmr_ticks;
1426 static struct intr_ctrl_ops intr_ops = {
1427 .intr_pending = apic_intr_pending,
1428 .get_intr_number = apic_get_intr_number,
1429 .begin_irq = apic_begin_irq,
1433 static struct vm_timer_ops timer_ops = {
1434 .update_timer = apic_update_time,
1440 static int apic_free(struct vm_device * dev) {
1442 /* TODO: This should crosscall to force an unhook on each CPU */
1444 // struct apic_state * apic = (struct apic_state *)dev->private_data;
1446 v3_unhook_msr(dev->vm, BASE_ADDR_MSR);
1452 static struct v3_device_ops dev_ops = {
1463 static int apic_init(struct v3_vm_info * vm, v3_cfg_tree_t * cfg) {
1464 char * dev_id = v3_cfg_val(cfg, "ID");
1465 struct apic_dev_state * apic_dev = NULL;
1468 PrintDebug("apic: creating an APIC for each core\n");
1470 apic_dev = (struct apic_dev_state *)V3_Malloc(sizeof(struct apic_dev_state) +
1471 sizeof(struct apic_state) * vm->num_cores);
1473 apic_dev->num_apics = vm->num_cores;
1475 struct vm_device * dev = v3_allocate_device(dev_id, &dev_ops, apic_dev);
1477 if (v3_attach_device(vm, dev) == -1) {
1478 PrintError("apic: Could not attach device %s\n", dev_id);
1483 for (i = 0; i < vm->num_cores; i++) {
1484 struct apic_state * apic = &(apic_dev->apics[i]);
1485 struct guest_info * core = &(vm->cores[i]);
1489 init_apic_state(apic, i);
1491 v3_register_intr_controller(core, &intr_ops, apic_dev);
1493 v3_add_timer(core, &timer_ops, apic_dev);
1495 v3_hook_full_mem(vm, core->cpu_id, apic->base_addr, apic->base_addr + PAGE_SIZE_4KB, apic_read, apic_write, apic_dev);
1497 PrintDebug("apic %u: (setup device): done, my id is %u\n", i, apic->lapic_id.val);
1500 #ifdef CONFIG_DEBUG_APIC
1501 for (i = 0; i < vm->num_cores; i++) {
1502 struct apic_state * apic = &(apic_dev->apics[i]);
1503 PrintDebug("apic: sanity check: apic %u (at %p) has id %u and msr value %llx\n",
1504 i, apic, apic->lapic_id.val, apic->base_addr_msr.value);
1509 PrintDebug("apic: priv_data is at %p\n", apic_dev);
1511 v3_hook_msr(vm, BASE_ADDR_MSR, read_apic_msr, write_apic_msr, apic_dev);
1518 device_register("LAPIC", apic_init)