2 * This file is part of the Palacios Virtual Machine Monitor developed
3 * by the V3VEE Project with funding from the United States National
4 * Science Foundation and the Department of Energy.
6 * The V3VEE Project is a joint project between Northwestern University
7 * and the University of New Mexico. You can find out more at
10 * Copyright (c) 2008, Jack Lange <jarusl@cs.northwestern.edu>
11 * Copyright (c) 2008, The V3VEE Project <http://www.v3vee.org>
12 * All rights reserved.
14 * Author: Jack Lange <jarusl@cs.northwestern.edu>
16 * This is free software. You are permitted to use,
17 * redistribute, and modify it as specified in the file "V3VEE_LICENSE".
21 #include <devices/apic.h>
22 #include <devices/apic_regs.h>
23 #include <devices/icc_bus.h>
24 #include <palacios/vmm.h>
25 #include <palacios/vmm_msr.h>
26 #include <palacios/vmm_sprintf.h>
27 #include <palacios/vm_guest.h>
30 #ifndef CONFIG_DEBUG_APIC
32 #define PrintDebug(fmt, args...)
36 typedef enum { APIC_TMR_INT, APIC_THERM_INT, APIC_PERF_INT,
37 APIC_LINT0_INT, APIC_LINT1_INT, APIC_ERR_INT } apic_irq_type_t;
39 #define APIC_FIXED_DELIVERY 0x0
40 #define APIC_SMI_DELIVERY 0x2
41 #define APIC_NMI_DELIVERY 0x4
42 #define APIC_INIT_DELIVERY 0x5
43 #define APIC_EXTINT_DELIVERY 0x7
46 #define BASE_ADDR_MSR 0x0000001B
47 #define DEFAULT_BASE_ADDR 0xfee00000
49 #define APIC_ID_OFFSET 0x020
50 #define APIC_VERSION_OFFSET 0x030
51 #define TPR_OFFSET 0x080
52 #define APR_OFFSET 0x090
53 #define PPR_OFFSET 0x0a0
54 #define EOI_OFFSET 0x0b0
55 #define REMOTE_READ_OFFSET 0x0c0
56 #define LDR_OFFSET 0x0d0
57 #define DFR_OFFSET 0x0e0
58 #define SPURIOUS_INT_VEC_OFFSET 0x0f0
60 #define ISR_OFFSET0 0x100 // 0x100 - 0x170
61 #define ISR_OFFSET1 0x110 // 0x100 - 0x170
62 #define ISR_OFFSET2 0x120 // 0x100 - 0x170
63 #define ISR_OFFSET3 0x130 // 0x100 - 0x170
64 #define ISR_OFFSET4 0x140 // 0x100 - 0x170
65 #define ISR_OFFSET5 0x150 // 0x100 - 0x170
66 #define ISR_OFFSET6 0x160 // 0x100 - 0x170
67 #define ISR_OFFSET7 0x170 // 0x100 - 0x170
69 #define TRIG_OFFSET0 0x180 // 0x180 - 0x1f0
70 #define TRIG_OFFSET1 0x190 // 0x180 - 0x1f0
71 #define TRIG_OFFSET2 0x1a0 // 0x180 - 0x1f0
72 #define TRIG_OFFSET3 0x1b0 // 0x180 - 0x1f0
73 #define TRIG_OFFSET4 0x1c0 // 0x180 - 0x1f0
74 #define TRIG_OFFSET5 0x1d0 // 0x180 - 0x1f0
75 #define TRIG_OFFSET6 0x1e0 // 0x180 - 0x1f0
76 #define TRIG_OFFSET7 0x1f0 // 0x180 - 0x1f0
79 #define IRR_OFFSET0 0x200 // 0x200 - 0x270
80 #define IRR_OFFSET1 0x210 // 0x200 - 0x270
81 #define IRR_OFFSET2 0x220 // 0x200 - 0x270
82 #define IRR_OFFSET3 0x230 // 0x200 - 0x270
83 #define IRR_OFFSET4 0x240 // 0x200 - 0x270
84 #define IRR_OFFSET5 0x250 // 0x200 - 0x270
85 #define IRR_OFFSET6 0x260 // 0x200 - 0x270
86 #define IRR_OFFSET7 0x270 // 0x200 - 0x270
89 #define ESR_OFFSET 0x280
90 #define INT_CMD_LO_OFFSET 0x300
91 #define INT_CMD_HI_OFFSET 0x310
92 #define TMR_LOC_VEC_TBL_OFFSET 0x320
93 #define THERM_LOC_VEC_TBL_OFFSET 0x330
94 #define PERF_CTR_LOC_VEC_TBL_OFFSET 0x340
95 #define LINT0_VEC_TBL_OFFSET 0x350
96 #define LINT1_VEC_TBL_OFFSET 0x360
97 #define ERR_VEC_TBL_OFFSET 0x370
98 #define TMR_INIT_CNT_OFFSET 0x380
99 #define TMR_CUR_CNT_OFFSET 0x390
100 #define TMR_DIV_CFG_OFFSET 0x3e0
101 #define EXT_APIC_FEATURE_OFFSET 0x400
102 #define EXT_APIC_CMD_OFFSET 0x410
103 #define SEOI_OFFSET 0x420
105 #define IER_OFFSET0 0x480 // 0x480 - 0x4f0
106 #define IER_OFFSET1 0x490 // 0x480 - 0x4f0
107 #define IER_OFFSET2 0x4a0 // 0x480 - 0x4f0
108 #define IER_OFFSET3 0x4b0 // 0x480 - 0x4f0
109 #define IER_OFFSET4 0x4c0 // 0x480 - 0x4f0
110 #define IER_OFFSET5 0x4d0 // 0x480 - 0x4f0
111 #define IER_OFFSET6 0x4e0 // 0x480 - 0x4f0
112 #define IER_OFFSET7 0x4f0 // 0x480 - 0x4f0
114 #define EXT_INT_LOC_VEC_TBL_OFFSET0 0x500 // 0x500 - 0x530
115 #define EXT_INT_LOC_VEC_TBL_OFFSET1 0x510 // 0x500 - 0x530
116 #define EXT_INT_LOC_VEC_TBL_OFFSET2 0x520 // 0x500 - 0x530
117 #define EXT_INT_LOC_VEC_TBL_OFFSET3 0x530 // 0x500 - 0x530
126 uint_t bootstrap_cpu : 1;
128 uint_t apic_enable : 1;
129 ullong_t base_addr : 40;
131 } __attribute__((packed));
132 } __attribute__((packed));
133 } __attribute__((packed));
142 v3_msr_t base_addr_msr;
145 /* memory map registers */
147 struct lapic_id_reg lapic_id;
148 struct apic_ver_reg apic_ver;
149 struct ext_apic_ctrl_reg ext_apic_ctrl;
150 struct local_vec_tbl_reg local_vec_tbl;
151 struct tmr_vec_tbl_reg tmr_vec_tbl;
152 struct tmr_div_cfg_reg tmr_div_cfg;
153 struct lint_vec_tbl_reg lint0_vec_tbl;
154 struct lint_vec_tbl_reg lint1_vec_tbl;
155 struct perf_ctr_loc_vec_tbl_reg perf_ctr_loc_vec_tbl;
156 struct therm_loc_vec_tbl_reg therm_loc_vec_tbl;
157 struct err_vec_tbl_reg err_vec_tbl;
158 struct err_status_reg err_status;
159 struct spurious_int_reg spurious_int;
160 struct int_cmd_reg int_cmd;
161 struct log_dst_reg log_dst;
162 struct dst_fmt_reg dst_fmt;
163 struct arb_prio_reg arb_prio;
164 struct task_prio_reg task_prio;
165 struct proc_prio_reg proc_prio;
166 struct ext_apic_feature_reg ext_apic_feature;
167 struct spec_eoi_reg spec_eoi;
170 uint32_t tmr_cur_cnt;
171 uint32_t tmr_init_cnt;
174 struct local_vec_tbl_reg ext_intr_vec_tbl[4];
176 uint32_t rem_rd_data;
179 uchar_t int_req_reg[32];
180 uchar_t int_svc_reg[32];
181 uchar_t int_en_reg[32];
182 uchar_t trig_mode_reg[32];
186 struct vm_device * icc_bus;
191 static int apic_read(struct guest_info * core, addr_t guest_addr, void * dst, uint_t length, void * priv_data);
192 static int apic_write(struct guest_info * core, addr_t guest_addr, void * src, uint_t length, void * priv_data);
194 static void init_apic_state(struct apic_state * apic, uint32_t id, struct vm_device * icc) {
195 apic->base_addr = DEFAULT_BASE_ADDR;
196 apic->base_addr_msr.value = 0x0000000000000900LL;
197 apic->base_addr_msr.value |= ((uint64_t)DEFAULT_BASE_ADDR);
199 PrintDebug("apic %u: Sizeof Interrupt Request Register %d, should be 32\n", apic->lapic_id.val,
200 (uint_t)sizeof(apic->int_req_reg));
202 memset(apic->int_req_reg, 0, sizeof(apic->int_req_reg));
203 memset(apic->int_svc_reg, 0, sizeof(apic->int_svc_reg));
204 memset(apic->int_en_reg, 0xff, sizeof(apic->int_en_reg));
205 memset(apic->trig_mode_reg, 0, sizeof(apic->trig_mode_reg));
207 apic->eoi = 0x00000000;
208 apic->rem_rd_data = 0x00000000;
209 apic->tmr_init_cnt = 0x00000000;
210 apic->tmr_cur_cnt = 0x00000000;
212 apic->lapic_id.val = id;
216 // The P6 has 6 LVT entries, so we set the value to (6-1)...
217 apic->apic_ver.val = 0x80050010;
219 apic->task_prio.val = 0x00000000;
220 apic->arb_prio.val = 0x00000000;
221 apic->proc_prio.val = 0x00000000;
222 apic->log_dst.val = 0x00000000;
223 apic->dst_fmt.val = 0xffffffff;
224 apic->spurious_int.val = 0x000000ff;
225 apic->err_status.val = 0x00000000;
226 apic->int_cmd.val = 0x0000000000000000LL;
227 apic->tmr_vec_tbl.val = 0x00010000;
228 apic->therm_loc_vec_tbl.val = 0x00010000;
229 apic->perf_ctr_loc_vec_tbl.val = 0x00010000;
230 apic->lint0_vec_tbl.val = 0x00010000;
231 apic->lint1_vec_tbl.val = 0x00010000;
232 apic->err_vec_tbl.val = 0x00010000;
233 apic->tmr_div_cfg.val = 0x00000000;
234 //apic->ext_apic_feature.val = 0x00000007;
235 apic->ext_apic_feature.val = 0x00040007;
236 apic->ext_apic_ctrl.val = 0x00000000;
237 apic->spec_eoi.val = 0x00000000;
239 v3_lock_init(&(apic->lock));
245 static int read_apic_msr(struct guest_info * core, uint_t msr, v3_msr_t * dst, void * priv_data) {
246 struct vm_device * dev = (struct vm_device *)priv_data;
247 struct apic_state * apics = (struct apic_state *)(dev->private_data);
248 struct apic_state * apic = &(apics[core->cpu_id]);
251 dst->value = apic->base_addr;
252 v3_unlock(apic->lock);
257 static int write_apic_msr(struct guest_info * core, uint_t msr, v3_msr_t src, void * priv_data) {
258 struct vm_device * dev = (struct vm_device *)priv_data;
259 struct apic_state * apics = (struct apic_state *)(dev->private_data);
260 struct apic_state * apic = &(apics[core->cpu_id]);
261 struct v3_mem_region * old_reg = v3_get_mem_region(dev->vm, core->cpu_id, apic->base_addr);
264 if (old_reg == NULL) {
266 PrintError("apic %u: APIC Base address region does not exit...\n",apic->lapic_id.val);
272 v3_delete_mem_region(dev->vm, old_reg);
274 apic->base_addr = src.value;
276 if (v3_hook_full_mem(dev->vm, core->cpu_id, apic->base_addr, apic->base_addr + PAGE_SIZE_4KB, apic_read, apic_write, dev) == -1) {
277 PrintError("apic %u: Could not hook new APIC Base address\n",apic->lapic_id.val);
278 v3_unlock(apic->lock);
282 v3_unlock(apic->lock);
287 // irq_num is the bit offset into a 256 bit buffer...
288 static int activate_apic_irq(struct apic_state * apic, uint32_t irq_num) {
289 int major_offset = (irq_num & ~0x00000007) >> 3;
290 int minor_offset = irq_num & 0x00000007;
291 uchar_t * req_location = apic->int_req_reg + major_offset;
292 uchar_t * en_location = apic->int_en_reg + major_offset;
293 uchar_t flag = 0x1 << minor_offset;
299 PrintError("apic %u: Attempting to raise an invalid interrupt: %d\n", apic->lapic_id.val,irq_num);
306 PrintDebug("apic %u: Raising APIC IRQ %d\n", apic->lapic_id.val,irq_num);
308 if (*req_location & flag) {
309 //V3_Print("Interrupts coallescing\n");
312 if (*en_location & flag) {
313 *req_location |= flag;
315 PrintDebug("apic %u: Interrupt not enabled... %.2x\n", apic->lapic_id.val, *en_location);
324 static int get_highest_isr(struct apic_state * apic) {
327 // We iterate backwards to find the highest priority
328 for (i = 31; i >= 0; i--) {
329 uchar_t * svc_major = apic->int_svc_reg + i;
331 if ((*svc_major) & 0xff) {
332 for (j = 7; j >= 0; j--) {
333 uchar_t flag = 0x1 << j;
334 if ((*svc_major) & flag) {
335 return ((i * 8) + j);
346 static int get_highest_irr(struct apic_state * apic) {
349 // We iterate backwards to find the highest priority
350 for (i = 31; i >= 0; i--) {
351 uchar_t * req_major = apic->int_req_reg + i;
353 if ((*req_major) & 0xff) {
354 for (j = 7; j >= 0; j--) {
355 uchar_t flag = 0x1 << j;
356 if ((*req_major) & flag) {
357 return ((i * 8) + j);
369 static int apic_do_eoi(struct apic_state * apic) {
370 int isr_irq = get_highest_isr(apic);
373 int major_offset = (isr_irq & ~0x00000007) >> 3;
374 int minor_offset = isr_irq & 0x00000007;
375 uchar_t flag = 0x1 << minor_offset;
376 uchar_t * svc_location = apic->int_svc_reg + major_offset;
378 PrintDebug("Received APIC EOI for IRQ %d\n", isr_irq);
380 *svc_location &= ~flag;
382 #ifdef CONFIG_CRAY_XT
384 if ((isr_irq == 238) ||
386 PrintError("Acking IRQ %d\n", isr_irq);
389 if (isr_irq == 238) {
394 //PrintError("Spurious EOI...\n");
401 static int activate_internal_irq(struct apic_state * apic, apic_irq_type_t int_type) {
402 uint32_t vec_num = 0;
403 uint32_t del_mode = 0;
409 vec_num = apic->tmr_vec_tbl.vec;
410 del_mode = APIC_FIXED_DELIVERY;
411 masked = apic->tmr_vec_tbl.mask;
414 vec_num = apic->therm_loc_vec_tbl.vec;
415 del_mode = apic->therm_loc_vec_tbl.msg_type;
416 masked = apic->therm_loc_vec_tbl.mask;
419 vec_num = apic->perf_ctr_loc_vec_tbl.vec;
420 del_mode = apic->perf_ctr_loc_vec_tbl.msg_type;
421 masked = apic->perf_ctr_loc_vec_tbl.mask;
424 vec_num = apic->lint0_vec_tbl.vec;
425 del_mode = apic->lint0_vec_tbl.msg_type;
426 masked = apic->lint0_vec_tbl.mask;
429 vec_num = apic->lint1_vec_tbl.vec;
430 del_mode = apic->lint1_vec_tbl.msg_type;
431 masked = apic->lint1_vec_tbl.mask;
434 vec_num = apic->err_vec_tbl.vec;
435 del_mode = APIC_FIXED_DELIVERY;
436 masked = apic->err_vec_tbl.mask;
439 PrintError("apic %u: Invalid APIC interrupt type\n",apic->lapic_id.val);
443 // interrupt is masked, don't send
445 PrintDebug("apic %u: Inerrupt is masked\n",apic->lapic_id.val);
449 if (del_mode == APIC_FIXED_DELIVERY) {
450 //PrintDebug("Activating internal APIC IRQ %d\n", vec_num);
451 return activate_apic_irq(apic, vec_num);
453 PrintError("apic %u: Unhandled Delivery Mode\n",apic->lapic_id.val);
459 static int apic_read(struct guest_info * core, addr_t guest_addr, void * dst, uint_t length, void * priv_data) {
460 struct apic_state * apics = (struct apic_state *)(priv_data);
461 struct apic_state * apic = &(apics[core->cpu_id]);
462 addr_t reg_addr = guest_addr - apic->base_addr;
463 struct apic_msr * msr = (struct apic_msr *)&(apic->base_addr_msr.value);
467 PrintDebug("apic %u: Read apic address space (%p)\n",apic->lapic_id.val,
470 if (msr->apic_enable == 0) {
471 PrintError("apic %u: Write to APIC address space with disabled APIC\n",apic->lapic_id.val);
476 /* Because "May not be supported" doesn't matter to Linux developers... */
477 /* if (length != 4) { */
478 /* PrintError("Invalid apic read length (%d)\n", length); */
482 switch (reg_addr & ~0x3) {
484 // Well, only an idiot would read from a architectural write only register
486 // PrintError("Attempting to read from write only register\n");
492 val = apic->lapic_id.val;
494 case APIC_VERSION_OFFSET:
495 val = apic->apic_ver.val;
498 val = apic->task_prio.val;
501 val = apic->arb_prio.val;
504 val = apic->proc_prio.val;
506 case REMOTE_READ_OFFSET:
507 val = apic->rem_rd_data;
510 val = apic->log_dst.val;
513 val = apic->dst_fmt.val;
515 case SPURIOUS_INT_VEC_OFFSET:
516 val = apic->spurious_int.val;
519 val = apic->err_status.val;
521 case TMR_LOC_VEC_TBL_OFFSET:
522 val = apic->tmr_vec_tbl.val;
524 case LINT0_VEC_TBL_OFFSET:
525 val = apic->lint0_vec_tbl.val;
527 case LINT1_VEC_TBL_OFFSET:
528 val = apic->lint1_vec_tbl.val;
530 case ERR_VEC_TBL_OFFSET:
531 val = apic->err_vec_tbl.val;
533 case TMR_INIT_CNT_OFFSET:
534 val = apic->tmr_init_cnt;
536 case TMR_DIV_CFG_OFFSET:
537 val = apic->tmr_div_cfg.val;
541 val = *(uint32_t *)(apic->int_en_reg);
544 val = *(uint32_t *)(apic->int_en_reg + 4);
547 val = *(uint32_t *)(apic->int_en_reg + 8);
550 val = *(uint32_t *)(apic->int_en_reg + 12);
553 val = *(uint32_t *)(apic->int_en_reg + 16);
556 val = *(uint32_t *)(apic->int_en_reg + 20);
559 val = *(uint32_t *)(apic->int_en_reg + 24);
562 val = *(uint32_t *)(apic->int_en_reg + 28);
566 val = *(uint32_t *)(apic->int_svc_reg);
569 val = *(uint32_t *)(apic->int_svc_reg + 4);
572 val = *(uint32_t *)(apic->int_svc_reg + 8);
575 val = *(uint32_t *)(apic->int_svc_reg + 12);
578 val = *(uint32_t *)(apic->int_svc_reg + 16);
581 val = *(uint32_t *)(apic->int_svc_reg + 20);
584 val = *(uint32_t *)(apic->int_svc_reg + 24);
587 val = *(uint32_t *)(apic->int_svc_reg + 28);
591 val = *(uint32_t *)(apic->trig_mode_reg);
594 val = *(uint32_t *)(apic->trig_mode_reg + 4);
597 val = *(uint32_t *)(apic->trig_mode_reg + 8);
600 val = *(uint32_t *)(apic->trig_mode_reg + 12);
603 val = *(uint32_t *)(apic->trig_mode_reg + 16);
606 val = *(uint32_t *)(apic->trig_mode_reg + 20);
609 val = *(uint32_t *)(apic->trig_mode_reg + 24);
612 val = *(uint32_t *)(apic->trig_mode_reg + 28);
616 val = *(uint32_t *)(apic->int_req_reg);
619 val = *(uint32_t *)(apic->int_req_reg + 4);
622 val = *(uint32_t *)(apic->int_req_reg + 8);
625 val = *(uint32_t *)(apic->int_req_reg + 12);
628 val = *(uint32_t *)(apic->int_req_reg + 16);
631 val = *(uint32_t *)(apic->int_req_reg + 20);
634 val = *(uint32_t *)(apic->int_req_reg + 24);
637 val = *(uint32_t *)(apic->int_req_reg + 28);
639 case TMR_CUR_CNT_OFFSET:
640 val = apic->tmr_cur_cnt;
643 // We are not going to implement these....
644 case THERM_LOC_VEC_TBL_OFFSET:
645 val = apic->therm_loc_vec_tbl.val;
647 case PERF_CTR_LOC_VEC_TBL_OFFSET:
648 val = apic->perf_ctr_loc_vec_tbl.val;
654 case INT_CMD_LO_OFFSET:
655 val = apic->int_cmd.lo;
657 case INT_CMD_HI_OFFSET:
658 val = apic->int_cmd.hi;
661 // handle current timer count
663 // Unhandled Registers
664 case EXT_INT_LOC_VEC_TBL_OFFSET0:
665 val = apic->ext_intr_vec_tbl[0].val;
667 case EXT_INT_LOC_VEC_TBL_OFFSET1:
668 val = apic->ext_intr_vec_tbl[1].val;
670 case EXT_INT_LOC_VEC_TBL_OFFSET2:
671 val = apic->ext_intr_vec_tbl[2].val;
673 case EXT_INT_LOC_VEC_TBL_OFFSET3:
674 val = apic->ext_intr_vec_tbl[3].val;
678 case EXT_APIC_FEATURE_OFFSET:
679 case EXT_APIC_CMD_OFFSET:
683 PrintError("apic %u: Read from Unhandled APIC Register: %x (getting zero)\n", apic->lapic_id.val, (uint32_t)reg_addr);
690 uint_t byte_addr = reg_addr & 0x3;
691 uint8_t * val_ptr = (uint8_t *)dst;
693 *val_ptr = *(((uint8_t *)&val) + byte_addr);
695 } else if ((length == 2) &&
696 ((reg_addr & 0x3) == 0x3)) {
697 uint_t byte_addr = reg_addr & 0x3;
698 uint16_t * val_ptr = (uint16_t *)dst;
699 *val_ptr = *(((uint16_t *)&val) + byte_addr);
701 } else if (length == 4) {
702 uint32_t * val_ptr = (uint32_t *)dst;
706 PrintError("apic %u: Invalid apic read length (%d)\n", apic->lapic_id.val, length);
710 PrintDebug("apic %u: Read finished (val=%x)\n", apic->lapic_id.val, *(uint32_t *)dst);
719 static int apic_write(struct guest_info * core, addr_t guest_addr, void * src, uint_t length, void * priv_data) {
720 struct apic_state * apics = (struct apic_state *)(priv_data);
721 struct apic_state * apic = &(apics[core->cpu_id]);
722 addr_t reg_addr = guest_addr - apic->base_addr;
723 struct apic_msr * msr = (struct apic_msr *)&(apic->base_addr_msr.value);
724 uint32_t op_val = *(uint32_t *)src;
726 PrintDebug("apic %u: Write to address space (%p) (val=%x)\n",
728 (void *)guest_addr, *(uint32_t *)src);
730 if (msr->apic_enable == 0) {
731 PrintError("apic %u: Write to APIC address space with disabled APIC\n",apic->lapic_id.val);
737 PrintError("apic %u: Invalid apic write length (%d)\n", apic->lapic_id.val, length);
742 case REMOTE_READ_OFFSET:
743 case APIC_VERSION_OFFSET:
770 case EXT_APIC_FEATURE_OFFSET:
772 PrintError("apic %u: Attempting to write to read only register %p (ignored)\n", apic->lapic_id.val, (void *)reg_addr);
774 PrintError("apic %u: Attempting to write to read only register %p (error)\n", apic->lapic_id.val, (void *)reg_addr);
781 apic->lapic_id.val = op_val;
784 apic->task_prio.val = op_val;
787 apic->log_dst.val = op_val;
790 apic->dst_fmt.val = op_val;
792 case SPURIOUS_INT_VEC_OFFSET:
793 apic->spurious_int.val = op_val;
796 apic->err_status.val = op_val;
798 case TMR_LOC_VEC_TBL_OFFSET:
799 apic->tmr_vec_tbl.val = op_val;
801 case THERM_LOC_VEC_TBL_OFFSET:
802 apic->therm_loc_vec_tbl.val = op_val;
804 case PERF_CTR_LOC_VEC_TBL_OFFSET:
805 apic->perf_ctr_loc_vec_tbl.val = op_val;
807 case LINT0_VEC_TBL_OFFSET:
808 apic->lint0_vec_tbl.val = op_val;
810 case LINT1_VEC_TBL_OFFSET:
811 apic->lint1_vec_tbl.val = op_val;
813 case ERR_VEC_TBL_OFFSET:
814 apic->err_vec_tbl.val = op_val;
816 case TMR_INIT_CNT_OFFSET:
817 apic->tmr_init_cnt = op_val;
818 apic->tmr_cur_cnt = op_val;
820 case TMR_CUR_CNT_OFFSET:
821 apic->tmr_cur_cnt = op_val;
823 case TMR_DIV_CFG_OFFSET:
824 apic->tmr_div_cfg.val = op_val;
828 // Enable mask (256 bits)
830 *(uint32_t *)(apic->int_en_reg) = op_val;
833 *(uint32_t *)(apic->int_en_reg + 4) = op_val;
836 *(uint32_t *)(apic->int_en_reg + 8) = op_val;
839 *(uint32_t *)(apic->int_en_reg + 12) = op_val;
842 *(uint32_t *)(apic->int_en_reg + 16) = op_val;
845 *(uint32_t *)(apic->int_en_reg + 20) = op_val;
848 *(uint32_t *)(apic->int_en_reg + 24) = op_val;
851 *(uint32_t *)(apic->int_en_reg + 28) = op_val;
854 case EXT_INT_LOC_VEC_TBL_OFFSET0:
855 apic->ext_intr_vec_tbl[0].val = op_val;
857 case EXT_INT_LOC_VEC_TBL_OFFSET1:
858 apic->ext_intr_vec_tbl[1].val = op_val;
860 case EXT_INT_LOC_VEC_TBL_OFFSET2:
861 apic->ext_intr_vec_tbl[2].val = op_val;
863 case EXT_INT_LOC_VEC_TBL_OFFSET3:
864 apic->ext_intr_vec_tbl[3].val = op_val;
874 case INT_CMD_LO_OFFSET:
875 apic->int_cmd.lo = op_val;
877 PrintDebug("apic %u: sending cmd 0x%llx to apic %u\n",apic->lapic_id.val,
878 apic->int_cmd.val, apic->int_cmd.dst);
879 v3_icc_send_ipi(apic->icc_bus, apic->lapic_id.val, apic->int_cmd.val);
881 case INT_CMD_HI_OFFSET:
882 apic->int_cmd.hi = op_val;
884 // Unhandled Registers
886 case EXT_APIC_CMD_OFFSET:
889 PrintError("apic %u: Write to Unhandled APIC Register: %x (ignored)\n", apic->lapic_id.val, (uint32_t)reg_addr);
893 PrintDebug("apic %u: Write finished\n",apic->lapic_id.val);
900 /* Interrupt Controller Functions */
902 // returns 1 if an interrupt is pending, 0 otherwise
903 static int apic_intr_pending(struct guest_info * info, void * private_data) {
904 struct apic_state * apic = (struct apic_state *)private_data;
905 int req_irq = get_highest_irr(apic);
906 int svc_irq = get_highest_isr(apic);
908 if ((req_irq >= 0) &&
909 (req_irq > svc_irq)) {
916 static int apic_get_intr_number(struct guest_info * info, void * private_data) {
917 struct apic_state * apic = (struct apic_state *)private_data;
918 int req_irq = get_highest_irr(apic);
919 int svc_irq = get_highest_isr(apic);
923 } else if (svc_irq < req_irq) {
931 static int apic_raise_intr(struct guest_info * info, int irq, void * private_data) {
932 struct apic_state * apic = (struct apic_state *)private_data;
934 return activate_apic_irq(apic, irq);
939 static int apic_begin_irq(struct guest_info * info, void * private_data, int irq) {
940 struct apic_state * apic = (struct apic_state *)private_data;
941 int major_offset = (irq & ~0x00000007) >> 3;
942 int minor_offset = irq & 0x00000007;
943 uchar_t * req_location = apic->int_req_reg + major_offset;
944 uchar_t * svc_location = apic->int_svc_reg + major_offset;
945 uchar_t flag = 0x01 << minor_offset;
947 *svc_location |= flag;
948 *req_location &= ~flag;
958 /* Timer Functions */
959 static void apic_update_time(struct guest_info * info, ullong_t cpu_cycles, ullong_t cpu_freq, void * priv_data) {
960 struct apic_state * apics = (struct apic_state *)(priv_data);
961 struct apic_state * apic = &(apics[info->cpu_id]);
962 // The 32 bit GCC runtime is a pile of shit
964 uint64_t tmr_ticks = 0;
966 uint32_t tmr_ticks = 0;
969 uchar_t tmr_div = *(uchar_t *)&(apic->tmr_div_cfg.val);
970 uint_t shift_num = 0;
973 // Check whether this is true:
974 // -> If the Init count is zero then the timer is disabled
975 // and doesn't just blitz interrupts to the CPU
976 if ((apic->tmr_init_cnt == 0) ||
977 ( (apic->tmr_vec_tbl.tmr_mode == APIC_TMR_ONESHOT) &&
978 (apic->tmr_cur_cnt == 0))) {
979 //PrintDebug("apic %u: APIC timer not yet initialized\n",apic->lapic_id.val);
1000 case APIC_TMR_DIV32:
1003 case APIC_TMR_DIV64:
1006 case APIC_TMR_DIV128:
1010 PrintError("apic %u: Invalid Timer Divider configuration\n",apic->lapic_id.val);
1014 tmr_ticks = cpu_cycles >> shift_num;
1015 // PrintDebug("Timer Ticks: %p\n", (void *)tmr_ticks);
1017 if (tmr_ticks < apic->tmr_cur_cnt) {
1018 apic->tmr_cur_cnt -= tmr_ticks;
1020 tmr_ticks -= apic->tmr_cur_cnt;
1021 apic->tmr_cur_cnt = 0;
1024 PrintDebug("apic %u: Raising APIC Timer interrupt (periodic=%d) (icnt=%d) (div=%d)\n", apic->lapic_id.val,
1025 apic->tmr_vec_tbl.tmr_mode, apic->tmr_init_cnt, shift_num);
1027 if (apic_intr_pending(info, priv_data)) {
1028 PrintDebug("apic %u: Overriding pending IRQ %d\n", apic->lapic_id.val, apic_get_intr_number(info, priv_data));
1031 if (activate_internal_irq(apic, APIC_TMR_INT) == -1) {
1032 PrintError("apic %u: Could not raise Timer interrupt\n",apic->lapic_id.val);
1035 if (apic->tmr_vec_tbl.tmr_mode == APIC_TMR_PERIODIC) {
1036 tmr_ticks = tmr_ticks % apic->tmr_init_cnt;
1037 apic->tmr_cur_cnt = apic->tmr_init_cnt - tmr_ticks;
1045 static struct intr_ctrl_ops intr_ops = {
1046 .intr_pending = apic_intr_pending,
1047 .get_intr_number = apic_get_intr_number,
1048 .begin_irq = apic_begin_irq,
1052 static struct vm_timer_ops timer_ops = {
1053 .update_time = apic_update_time,
1059 static int apic_free(struct vm_device * dev) {
1061 /* TODO: This should crosscall to force an unhook on each CPU */
1063 // struct apic_state * apic = (struct apic_state *)dev->private_data;
1065 v3_unhook_msr(dev->vm, BASE_ADDR_MSR);
1071 static struct v3_device_ops dev_ops = {
1080 static struct v3_icc_ops icc_ops = {
1081 .raise_intr = apic_raise_intr,
1086 static int apic_init(struct v3_vm_info * vm, v3_cfg_tree_t * cfg) {
1087 PrintDebug("apic: creating an APIC for each core\n");
1088 char * name = v3_cfg_val(cfg, "name");
1089 char * icc_name = v3_cfg_val(cfg,"bus");
1090 struct vm_device * icc = v3_find_dev(vm, icc_name);
1094 PrintError("apic: Cannot find ICC Bus (%s)\n", icc_name);
1098 // We allocate one apic per core
1099 // APICs are accessed via index which correlates with the core's cpu_id
1100 // 0..num_cores-1 at num_cores is the ioapic (one only)
1101 struct apic_state * apic = (struct apic_state *)V3_Malloc(sizeof(struct apic_state) * vm->num_cores);
1103 struct vm_device * dev = v3_allocate_device(name, &dev_ops, apic);
1105 if (v3_attach_device(vm, dev) == -1) {
1106 PrintError("apic: Could not attach device %s\n", name);
1111 for (i = 0; i < vm->num_cores; i++) {
1112 struct guest_info * core = &(vm->cores[i]);
1114 init_apic_state(&(apic[i]),i,icc);
1116 v3_register_intr_controller(core, &intr_ops, &(apic[i]));
1118 v3_add_timer(core, &timer_ops, &(apic[i]));
1120 v3_hook_full_mem(vm, core->cpu_id, apic->base_addr, apic->base_addr + PAGE_SIZE_4KB, apic_read, apic_write, &(apic[i]));
1122 v3_icc_register_apic(core, icc, i, &icc_ops, &(apic[i]));
1128 v3_hook_msr(vm, BASE_ADDR_MSR, read_apic_msr, write_apic_msr, dev);
1135 device_register("LAPIC", apic_init)