2 * This file is part of the Palacios Virtual Machine Monitor developed
3 * by the V3VEE Project with funding from the United States National
4 * Science Foundation and the Department of Energy.
6 * The V3VEE Project is a joint project between Northwestern University
7 * and the University of New Mexico. You can find out more at
10 * Copyright (c) 2008, Jack Lange <jarusl@cs.northwestern.edu>
11 * Copyright (c) 2008, The V3VEE Project <http://www.v3vee.org>
12 * All rights reserved.
14 * Author: Jack Lange <jarusl@cs.northwestern.edu>
16 * This is free software. You are permitted to use,
17 * redistribute, and modify it as specified in the file "V3VEE_LICENSE".
21 #include <devices/apic.h>
22 #include <devices/apic_regs.h>
23 #include <palacios/vmm.h>
24 #include <palacios/vmm_msr.h>
25 #include <palacios/vmm_sprintf.h>
26 #include <palacios/vm_guest.h>
28 #ifndef CONFIG_DEBUG_APIC
30 #define PrintDebug(fmt, args...)
34 typedef enum { APIC_TMR_INT, APIC_THERM_INT, APIC_PERF_INT,
35 APIC_LINT0_INT, APIC_LINT1_INT, APIC_ERR_INT } apic_irq_type_t;
37 #define APIC_FIXED_DELIVERY 0x0
38 #define APIC_SMI_DELIVERY 0x2
39 #define APIC_NMI_DELIVERY 0x4
40 #define APIC_INIT_DELIVERY 0x5
41 #define APIC_EXTINT_DELIVERY 0x7
44 #define BASE_ADDR_MSR 0x0000001B
45 #define DEFAULT_BASE_ADDR 0xfee00000
47 #define APIC_ID_OFFSET 0x020
48 #define APIC_VERSION_OFFSET 0x030
49 #define TPR_OFFSET 0x080
50 #define APR_OFFSET 0x090
51 #define PPR_OFFSET 0x0a0
52 #define EOI_OFFSET 0x0b0
53 #define REMOTE_READ_OFFSET 0x0c0
54 #define LDR_OFFSET 0x0d0
55 #define DFR_OFFSET 0x0e0
56 #define SPURIOUS_INT_VEC_OFFSET 0x0f0
58 #define ISR_OFFSET0 0x100 // 0x100 - 0x170
59 #define ISR_OFFSET1 0x110 // 0x100 - 0x170
60 #define ISR_OFFSET2 0x120 // 0x100 - 0x170
61 #define ISR_OFFSET3 0x130 // 0x100 - 0x170
62 #define ISR_OFFSET4 0x140 // 0x100 - 0x170
63 #define ISR_OFFSET5 0x150 // 0x100 - 0x170
64 #define ISR_OFFSET6 0x160 // 0x100 - 0x170
65 #define ISR_OFFSET7 0x170 // 0x100 - 0x170
67 #define TRIG_OFFSET0 0x180 // 0x180 - 0x1f0
68 #define TRIG_OFFSET1 0x190 // 0x180 - 0x1f0
69 #define TRIG_OFFSET2 0x1a0 // 0x180 - 0x1f0
70 #define TRIG_OFFSET3 0x1b0 // 0x180 - 0x1f0
71 #define TRIG_OFFSET4 0x1c0 // 0x180 - 0x1f0
72 #define TRIG_OFFSET5 0x1d0 // 0x180 - 0x1f0
73 #define TRIG_OFFSET6 0x1e0 // 0x180 - 0x1f0
74 #define TRIG_OFFSET7 0x1f0 // 0x180 - 0x1f0
77 #define IRR_OFFSET0 0x200 // 0x200 - 0x270
78 #define IRR_OFFSET1 0x210 // 0x200 - 0x270
79 #define IRR_OFFSET2 0x220 // 0x200 - 0x270
80 #define IRR_OFFSET3 0x230 // 0x200 - 0x270
81 #define IRR_OFFSET4 0x240 // 0x200 - 0x270
82 #define IRR_OFFSET5 0x250 // 0x200 - 0x270
83 #define IRR_OFFSET6 0x260 // 0x200 - 0x270
84 #define IRR_OFFSET7 0x270 // 0x200 - 0x270
87 #define ESR_OFFSET 0x280
88 #define INT_CMD_LO_OFFSET 0x300
89 #define INT_CMD_HI_OFFSET 0x310
90 #define TMR_LOC_VEC_TBL_OFFSET 0x320
91 #define THERM_LOC_VEC_TBL_OFFSET 0x330
92 #define PERF_CTR_LOC_VEC_TBL_OFFSET 0x340
93 #define LINT0_VEC_TBL_OFFSET 0x350
94 #define LINT1_VEC_TBL_OFFSET 0x360
95 #define ERR_VEC_TBL_OFFSET 0x370
96 #define TMR_INIT_CNT_OFFSET 0x380
97 #define TMR_CUR_CNT_OFFSET 0x390
98 #define TMR_DIV_CFG_OFFSET 0x3e0
99 #define EXT_APIC_FEATURE_OFFSET 0x400
100 #define EXT_APIC_CMD_OFFSET 0x410
101 #define SEOI_OFFSET 0x420
103 #define IER_OFFSET0 0x480 // 0x480 - 0x4f0
104 #define IER_OFFSET1 0x490 // 0x480 - 0x4f0
105 #define IER_OFFSET2 0x4a0 // 0x480 - 0x4f0
106 #define IER_OFFSET3 0x4b0 // 0x480 - 0x4f0
107 #define IER_OFFSET4 0x4c0 // 0x480 - 0x4f0
108 #define IER_OFFSET5 0x4d0 // 0x480 - 0x4f0
109 #define IER_OFFSET6 0x4e0 // 0x480 - 0x4f0
110 #define IER_OFFSET7 0x4f0 // 0x480 - 0x4f0
112 #define EXT_INT_LOC_VEC_TBL_OFFSET0 0x500 // 0x500 - 0x530
113 #define EXT_INT_LOC_VEC_TBL_OFFSET1 0x510 // 0x500 - 0x530
114 #define EXT_INT_LOC_VEC_TBL_OFFSET2 0x520 // 0x500 - 0x530
115 #define EXT_INT_LOC_VEC_TBL_OFFSET3 0x530 // 0x500 - 0x530
124 uint_t bootstrap_cpu : 1;
126 uint_t apic_enable : 1;
127 ullong_t base_addr : 40;
129 } __attribute__((packed));
130 } __attribute__((packed));
131 } __attribute__((packed));
140 v3_msr_t base_addr_msr;
143 /* memory map registers */
145 struct lapic_id_reg lapic_id;
146 struct apic_ver_reg apic_ver;
147 struct ext_apic_ctrl_reg ext_apic_ctrl;
148 struct local_vec_tbl_reg local_vec_tbl;
149 struct tmr_vec_tbl_reg tmr_vec_tbl;
150 struct tmr_div_cfg_reg tmr_div_cfg;
151 struct lint_vec_tbl_reg lint0_vec_tbl;
152 struct lint_vec_tbl_reg lint1_vec_tbl;
153 struct perf_ctr_loc_vec_tbl_reg perf_ctr_loc_vec_tbl;
154 struct therm_loc_vec_tbl_reg therm_loc_vec_tbl;
155 struct err_vec_tbl_reg err_vec_tbl;
156 struct err_status_reg err_status;
157 struct spurious_int_reg spurious_int;
158 struct int_cmd_reg int_cmd;
159 struct log_dst_reg log_dst;
160 struct dst_fmt_reg dst_fmt;
161 struct arb_prio_reg arb_prio;
162 struct task_prio_reg task_prio;
163 struct proc_prio_reg proc_prio;
164 struct ext_apic_feature_reg ext_apic_feature;
165 struct spec_eoi_reg spec_eoi;
168 uint32_t tmr_cur_cnt;
169 uint32_t tmr_init_cnt;
172 struct local_vec_tbl_reg ext_intr_vec_tbl[4];
174 uint32_t rem_rd_data;
177 uchar_t int_req_reg[32];
178 uchar_t int_svc_reg[32];
179 uchar_t int_en_reg[32];
180 uchar_t trig_mode_reg[32];
187 static void apic_incoming_ipi(void *val);
188 static int apic_read(addr_t guest_addr, void * dst, uint_t length, void * priv_data);
189 static int apic_write(addr_t guest_addr, void * src, uint_t length, void * priv_data);
191 static void init_apic_state(struct apic_state * apic) {
192 apic->base_addr = DEFAULT_BASE_ADDR;
193 apic->base_addr_msr.value = 0x0000000000000900LL;
194 apic->base_addr_msr.value |= ((uint64_t)DEFAULT_BASE_ADDR);
196 PrintDebug("Sizeof Interrupt Request Register %d, should be 32\n",
197 (uint_t)sizeof(apic->int_req_reg));
199 memset(apic->int_req_reg, 0, sizeof(apic->int_req_reg));
200 memset(apic->int_svc_reg, 0, sizeof(apic->int_svc_reg));
201 memset(apic->int_en_reg, 0xff, sizeof(apic->int_en_reg));
202 memset(apic->trig_mode_reg, 0, sizeof(apic->trig_mode_reg));
204 apic->eoi = 0x00000000;
205 apic->rem_rd_data = 0x00000000;
206 apic->tmr_init_cnt = 0x00000000;
207 apic->tmr_cur_cnt = 0x00000000;
210 // We need to figure out what the APIC ID is....
211 apic->lapic_id.val = 0x00000000;
213 // The P6 has 6 LVT entries, so we set the value to (6-1)...
214 apic->apic_ver.val = 0x80050010;
216 apic->task_prio.val = 0x00000000;
217 apic->arb_prio.val = 0x00000000;
218 apic->proc_prio.val = 0x00000000;
219 apic->log_dst.val = 0x00000000;
220 apic->dst_fmt.val = 0xffffffff;
221 apic->spurious_int.val = 0x000000ff;
222 apic->err_status.val = 0x00000000;
223 apic->int_cmd.val = 0x0000000000000000LL;
224 apic->tmr_vec_tbl.val = 0x00010000;
225 apic->therm_loc_vec_tbl.val = 0x00010000;
226 apic->perf_ctr_loc_vec_tbl.val = 0x00010000;
227 apic->lint0_vec_tbl.val = 0x00010000;
228 apic->lint1_vec_tbl.val = 0x00010000;
229 apic->err_vec_tbl.val = 0x00010000;
230 apic->tmr_div_cfg.val = 0x00000000;
231 //apic->ext_apic_feature.val = 0x00000007;
232 apic->ext_apic_feature.val = 0x00040007;
233 apic->ext_apic_ctrl.val = 0x00000000;
234 apic->spec_eoi.val = 0x00000000;
240 static int read_apic_msr(uint_t msr, v3_msr_t * dst, void * priv_data) {
241 struct vm_device * dev = (struct vm_device *)priv_data;
242 struct apic_state * apic = (struct apic_state *)dev->private_data;
243 dst->value = apic->base_addr;
248 static int write_apic_msr(uint_t msr, v3_msr_t src, void * priv_data) {
249 struct vm_device * dev = (struct vm_device *)priv_data;
250 struct apic_state * apic = (struct apic_state *)dev->private_data;
251 struct v3_shadow_region * old_reg = v3_get_shadow_region(dev->vm, apic->base_addr);
253 if (old_reg == NULL) {
255 PrintError("APIC Base address region does not exit...\n");
259 v3_delete_shadow_region(dev->vm, old_reg);
261 apic->base_addr = src.value;
263 if (v3_hook_full_mem(dev->vm, apic->base_addr, apic->base_addr + PAGE_SIZE_4KB, apic_read, apic_write, dev) == -1) {
264 PrintError("Could not hook new APIC Base address\n");
272 // irq_num is the bit offset into a 256 bit buffer...
273 static int activate_apic_irq(struct apic_state * apic, uint32_t irq_num) {
274 int major_offset = (irq_num & ~0x00000007) >> 3;
275 int minor_offset = irq_num & 0x00000007;
276 uchar_t * req_location = apic->int_req_reg + major_offset;
277 uchar_t * en_location = apic->int_en_reg + major_offset;
278 uchar_t flag = 0x1 << minor_offset;
281 PrintError("Attempting to raise an invalid interrupt: %d\n", irq_num);
285 PrintDebug("Raising APIC IRQ %d\n", irq_num);
287 if (*req_location & flag) {
288 //V3_Print("Interrupts coallescing\n");
291 if (*en_location & flag) {
292 *req_location |= flag;
294 PrintDebug("Interrupt not enabled... %.2x\n", *en_location);
303 static int get_highest_isr(struct apic_state * apic) {
306 // We iterate backwards to find the highest priority
307 for (i = 31; i >= 0; i--) {
308 uchar_t * svc_major = apic->int_svc_reg + i;
310 if ((*svc_major) & 0xff) {
311 for (j = 7; j >= 0; j--) {
312 uchar_t flag = 0x1 << j;
313 if ((*svc_major) & flag) {
314 return ((i * 8) + j);
325 static int get_highest_irr(struct apic_state * apic) {
328 // We iterate backwards to find the highest priority
329 for (i = 31; i >= 0; i--) {
330 uchar_t * req_major = apic->int_req_reg + i;
332 if ((*req_major) & 0xff) {
333 for (j = 7; j >= 0; j--) {
334 uchar_t flag = 0x1 << j;
335 if ((*req_major) & flag) {
336 return ((i * 8) + j);
348 static int apic_do_eoi(struct apic_state * apic) {
349 int isr_irq = get_highest_isr(apic);
352 int major_offset = (isr_irq & ~0x00000007) >> 3;
353 int minor_offset = isr_irq & 0x00000007;
354 uchar_t flag = 0x1 << minor_offset;
355 uchar_t * svc_location = apic->int_svc_reg + major_offset;
357 PrintDebug("Received APIC EOI for IRQ %d\n", isr_irq);
359 *svc_location &= ~flag;
361 #ifdef CONFIG_CRAY_XT
363 if ((isr_irq == 238) ||
365 PrintError("Acking IRQ %d\n", isr_irq);
368 if (isr_irq == 238) {
373 //PrintError("Spurious EOI...\n");
380 static int activate_internal_irq(struct apic_state * apic, apic_irq_type_t int_type) {
381 uint32_t vec_num = 0;
382 uint32_t del_mode = 0;
388 vec_num = apic->tmr_vec_tbl.vec;
389 del_mode = APIC_FIXED_DELIVERY;
390 masked = apic->tmr_vec_tbl.mask;
393 vec_num = apic->therm_loc_vec_tbl.vec;
394 del_mode = apic->therm_loc_vec_tbl.msg_type;
395 masked = apic->therm_loc_vec_tbl.mask;
398 vec_num = apic->perf_ctr_loc_vec_tbl.vec;
399 del_mode = apic->perf_ctr_loc_vec_tbl.msg_type;
400 masked = apic->perf_ctr_loc_vec_tbl.mask;
403 vec_num = apic->lint0_vec_tbl.vec;
404 del_mode = apic->lint0_vec_tbl.msg_type;
405 masked = apic->lint0_vec_tbl.mask;
408 vec_num = apic->lint1_vec_tbl.vec;
409 del_mode = apic->lint1_vec_tbl.msg_type;
410 masked = apic->lint1_vec_tbl.mask;
413 vec_num = apic->err_vec_tbl.vec;
414 del_mode = APIC_FIXED_DELIVERY;
415 masked = apic->err_vec_tbl.mask;
418 PrintError("Invalid APIC interrupt type\n");
422 // interrupt is masked, don't send
424 PrintDebug("Inerrupt is masked\n");
428 if (del_mode == APIC_FIXED_DELIVERY) {
429 //PrintDebug("Activating internal APIC IRQ %d\n", vec_num);
430 return activate_apic_irq(apic, vec_num);
432 PrintError("Unhandled Delivery Mode\n");
438 static int apic_read(addr_t guest_addr, void * dst, uint_t length, void * priv_data) {
439 struct vm_device * dev = (struct vm_device *)priv_data;
440 struct apic_state * apic = (struct apic_state *)dev->private_data;
441 addr_t reg_addr = guest_addr - apic->base_addr;
442 struct apic_msr * msr = (struct apic_msr *)&(apic->base_addr_msr.value);
446 PrintDebug("Read apic address space (%p)\n",
449 if (msr->apic_enable == 0) {
450 PrintError("Write to APIC address space with disabled APIC\n");
455 /* Because "May not be supported" doesn't matter to Linux developers... */
456 /* if (length != 4) { */
457 /* PrintError("Invalid apic read length (%d)\n", length); */
461 switch (reg_addr & ~0x3) {
463 // Well, only an idiot would read from a architectural write only register
465 // PrintError("Attempting to read from write only register\n");
471 val = apic->lapic_id.val;
473 case APIC_VERSION_OFFSET:
474 val = apic->apic_ver.val;
477 val = apic->task_prio.val;
480 val = apic->arb_prio.val;
483 val = apic->proc_prio.val;
485 case REMOTE_READ_OFFSET:
486 val = apic->rem_rd_data;
489 val = apic->log_dst.val;
492 val = apic->dst_fmt.val;
494 case SPURIOUS_INT_VEC_OFFSET:
495 val = apic->spurious_int.val;
498 val = apic->err_status.val;
500 case TMR_LOC_VEC_TBL_OFFSET:
501 val = apic->tmr_vec_tbl.val;
503 case LINT0_VEC_TBL_OFFSET:
504 val = apic->lint0_vec_tbl.val;
506 case LINT1_VEC_TBL_OFFSET:
507 val = apic->lint1_vec_tbl.val;
509 case ERR_VEC_TBL_OFFSET:
510 val = apic->err_vec_tbl.val;
512 case TMR_INIT_CNT_OFFSET:
513 val = apic->tmr_init_cnt;
515 case TMR_DIV_CFG_OFFSET:
516 val = apic->tmr_div_cfg.val;
520 val = *(uint32_t *)(apic->int_en_reg);
523 val = *(uint32_t *)(apic->int_en_reg + 4);
526 val = *(uint32_t *)(apic->int_en_reg + 8);
529 val = *(uint32_t *)(apic->int_en_reg + 12);
532 val = *(uint32_t *)(apic->int_en_reg + 16);
535 val = *(uint32_t *)(apic->int_en_reg + 20);
538 val = *(uint32_t *)(apic->int_en_reg + 24);
541 val = *(uint32_t *)(apic->int_en_reg + 28);
545 val = *(uint32_t *)(apic->int_svc_reg);
548 val = *(uint32_t *)(apic->int_svc_reg + 4);
551 val = *(uint32_t *)(apic->int_svc_reg + 8);
554 val = *(uint32_t *)(apic->int_svc_reg + 12);
557 val = *(uint32_t *)(apic->int_svc_reg + 16);
560 val = *(uint32_t *)(apic->int_svc_reg + 20);
563 val = *(uint32_t *)(apic->int_svc_reg + 24);
566 val = *(uint32_t *)(apic->int_svc_reg + 28);
570 val = *(uint32_t *)(apic->trig_mode_reg);
573 val = *(uint32_t *)(apic->trig_mode_reg + 4);
576 val = *(uint32_t *)(apic->trig_mode_reg + 8);
579 val = *(uint32_t *)(apic->trig_mode_reg + 12);
582 val = *(uint32_t *)(apic->trig_mode_reg + 16);
585 val = *(uint32_t *)(apic->trig_mode_reg + 20);
588 val = *(uint32_t *)(apic->trig_mode_reg + 24);
591 val = *(uint32_t *)(apic->trig_mode_reg + 28);
595 val = *(uint32_t *)(apic->int_req_reg);
598 val = *(uint32_t *)(apic->int_req_reg + 4);
601 val = *(uint32_t *)(apic->int_req_reg + 8);
604 val = *(uint32_t *)(apic->int_req_reg + 12);
607 val = *(uint32_t *)(apic->int_req_reg + 16);
610 val = *(uint32_t *)(apic->int_req_reg + 20);
613 val = *(uint32_t *)(apic->int_req_reg + 24);
616 val = *(uint32_t *)(apic->int_req_reg + 28);
618 case TMR_CUR_CNT_OFFSET:
619 val = apic->tmr_cur_cnt;
622 // We are not going to implement these....
623 case THERM_LOC_VEC_TBL_OFFSET:
624 val = apic->therm_loc_vec_tbl.val;
626 case PERF_CTR_LOC_VEC_TBL_OFFSET:
627 val = apic->perf_ctr_loc_vec_tbl.val;
633 case INT_CMD_LO_OFFSET:
634 val = apic->int_cmd.lo;
636 case INT_CMD_HI_OFFSET:
637 val = apic->int_cmd.hi;
640 // handle current timer count
642 // Unhandled Registers
643 case EXT_INT_LOC_VEC_TBL_OFFSET0:
644 val = apic->ext_intr_vec_tbl[0].val;
646 case EXT_INT_LOC_VEC_TBL_OFFSET1:
647 val = apic->ext_intr_vec_tbl[1].val;
649 case EXT_INT_LOC_VEC_TBL_OFFSET2:
650 val = apic->ext_intr_vec_tbl[2].val;
652 case EXT_INT_LOC_VEC_TBL_OFFSET3:
653 val = apic->ext_intr_vec_tbl[3].val;
657 case EXT_APIC_FEATURE_OFFSET:
658 case EXT_APIC_CMD_OFFSET:
662 PrintError("Read from Unhandled APIC Register: %x\n", (uint32_t)reg_addr);
668 uint_t byte_addr = reg_addr & 0x3;
669 uint8_t * val_ptr = (uint8_t *)dst;
671 *val_ptr = *(((uint8_t *)&val) + byte_addr);
673 } else if ((length == 2) &&
674 ((reg_addr & 0x3) == 0x3)) {
675 uint_t byte_addr = reg_addr & 0x3;
676 uint16_t * val_ptr = (uint16_t *)dst;
677 *val_ptr = *(((uint16_t *)&val) + byte_addr);
679 } else if (length == 4) {
680 uint32_t * val_ptr = (uint32_t *)dst;
684 PrintError("Invalid apic read length (%d)\n", length);
688 PrintDebug("Read finished (val=%x)\n", *(uint32_t *)dst);
694 static int apic_write(addr_t guest_addr, void * src, uint_t length, void * priv_data) {
695 struct vm_device * dev = (struct vm_device *)priv_data;
696 struct apic_state * apic = (struct apic_state *)dev->private_data;
697 addr_t reg_addr = guest_addr - apic->base_addr;
698 struct apic_msr * msr = (struct apic_msr *)&(apic->base_addr_msr.value);
699 uint32_t op_val = *(uint32_t *)src;
701 PrintDebug("Write to apic address space (%p) (val=%x)\n",
702 (void *)guest_addr, *(uint32_t *)src);
704 if (msr->apic_enable == 0) {
705 PrintError("Write to APIC address space with disabled APIC\n");
711 PrintError("Invalid apic write length (%d)\n", length);
716 case REMOTE_READ_OFFSET:
717 case APIC_VERSION_OFFSET:
744 case EXT_APIC_FEATURE_OFFSET:
746 PrintError("Attempting to write to read only register %p (ignored)\n", (void *)reg_addr);
748 PrintError("Attempting to write to read only register %p (error)\n", (void *)reg_addr);
755 apic->lapic_id.val = op_val;
758 apic->task_prio.val = op_val;
761 apic->log_dst.val = op_val;
764 apic->dst_fmt.val = op_val;
766 case SPURIOUS_INT_VEC_OFFSET:
767 apic->spurious_int.val = op_val;
770 apic->err_status.val = op_val;
772 case TMR_LOC_VEC_TBL_OFFSET:
773 apic->tmr_vec_tbl.val = op_val;
775 case THERM_LOC_VEC_TBL_OFFSET:
776 apic->therm_loc_vec_tbl.val = op_val;
778 case PERF_CTR_LOC_VEC_TBL_OFFSET:
779 apic->perf_ctr_loc_vec_tbl.val = op_val;
781 case LINT0_VEC_TBL_OFFSET:
782 apic->lint0_vec_tbl.val = op_val;
784 case LINT1_VEC_TBL_OFFSET:
785 apic->lint1_vec_tbl.val = op_val;
787 case ERR_VEC_TBL_OFFSET:
788 apic->err_vec_tbl.val = op_val;
790 case TMR_INIT_CNT_OFFSET:
791 apic->tmr_init_cnt = op_val;
792 apic->tmr_cur_cnt = op_val;
794 case TMR_CUR_CNT_OFFSET:
795 apic->tmr_cur_cnt = op_val;
797 case TMR_DIV_CFG_OFFSET:
798 apic->tmr_div_cfg.val = op_val;
802 // Enable mask (256 bits)
804 *(uint32_t *)(apic->int_en_reg) = op_val;
807 *(uint32_t *)(apic->int_en_reg + 4) = op_val;
810 *(uint32_t *)(apic->int_en_reg + 8) = op_val;
813 *(uint32_t *)(apic->int_en_reg + 12) = op_val;
816 *(uint32_t *)(apic->int_en_reg + 16) = op_val;
819 *(uint32_t *)(apic->int_en_reg + 20) = op_val;
822 *(uint32_t *)(apic->int_en_reg + 24) = op_val;
825 *(uint32_t *)(apic->int_en_reg + 28) = op_val;
828 case EXT_INT_LOC_VEC_TBL_OFFSET0:
829 apic->ext_intr_vec_tbl[0].val = op_val;
831 case EXT_INT_LOC_VEC_TBL_OFFSET1:
832 apic->ext_intr_vec_tbl[1].val = op_val;
834 case EXT_INT_LOC_VEC_TBL_OFFSET2:
835 apic->ext_intr_vec_tbl[2].val = op_val;
837 case EXT_INT_LOC_VEC_TBL_OFFSET3:
838 apic->ext_intr_vec_tbl[3].val = op_val;
848 case INT_CMD_LO_OFFSET:
849 apic->int_cmd.lo = op_val;
850 V3_Call_On_CPU(apic->int_cmd.dst, apic_incoming_ipi, (void *)apic->int_cmd.val);
853 case INT_CMD_HI_OFFSET:
854 apic->int_cmd.hi = op_val;
856 // Unhandled Registers
858 case EXT_APIC_CMD_OFFSET:
861 PrintError("Write to Unhandled APIC Register: %x\n", (uint32_t)reg_addr);
865 PrintDebug("Write finished\n");
872 /* Interrupt Controller Functions */
874 // returns 1 if an interrupt is pending, 0 otherwise
875 static int apic_intr_pending(struct guest_info * info, void * private_data) {
876 struct vm_device * dev = (struct vm_device *)private_data;
877 struct apic_state * apic = (struct apic_state *)dev->private_data;
878 int req_irq = get_highest_irr(apic);
879 int svc_irq = get_highest_isr(apic);
881 if ((req_irq >= 0) &&
882 (req_irq > svc_irq)) {
889 static int apic_get_intr_number(struct guest_info * info, void * private_data) {
890 struct vm_device * dev = (struct vm_device *)private_data;
891 struct apic_state * apic = (struct apic_state *)dev->private_data;
892 int req_irq = get_highest_irr(apic);
893 int svc_irq = get_highest_isr(apic);
897 } else if (svc_irq < req_irq) {
904 static int apic_raise_intr(struct guest_info * info, void * private_data, int irq) {
905 #ifdef CONFIG_CRAY_XT
906 // The Seastar is connected directly to the LAPIC via LINT0 on the ICC bus
909 struct vm_device * dev = (struct vm_device *)private_data;
910 struct apic_state * apic = (struct apic_state *)dev->private_data;
912 return activate_apic_irq(apic, irq);
919 static int apic_lower_intr(struct guest_info * info, void * private_data, int irq) {
923 static int apic_begin_irq(struct guest_info * info, void * private_data, int irq) {
924 struct vm_device * dev = (struct vm_device *)private_data;
925 struct apic_state * apic = (struct apic_state *)dev->private_data;
926 int major_offset = (irq & ~0x00000007) >> 3;
927 int minor_offset = irq & 0x00000007;
928 uchar_t * req_location = apic->int_req_reg + major_offset;
929 uchar_t * svc_location = apic->int_svc_reg + major_offset;
930 uchar_t flag = 0x01 << minor_offset;
932 *svc_location |= flag;
933 *req_location &= ~flag;
935 #ifdef CONFIG_CRAY_XT
936 if ((irq == 238) || (irq == 239)) {
937 PrintError("APIC: Begin IRQ %d (ISR=%x), (IRR=%x)\n", irq, *svc_location, *req_location);
946 int v3_apic_raise_intr(struct guest_info * info, struct vm_device * apic_dev, int intr_num) {
947 struct apic_state * apic = (struct apic_state *)apic_dev->private_data;
949 if (activate_apic_irq(apic, intr_num) == -1) {
950 PrintError("Error: Could not activate apic_irq\n");
954 v3_interrupt_cpu(info, 0);
961 /* Timer Functions */
962 static void apic_update_time(ullong_t cpu_cycles, ullong_t cpu_freq, void * priv_data) {
963 struct vm_device * dev = (struct vm_device *)priv_data;
964 struct apic_state * apic = (struct apic_state *)dev->private_data;
965 // The 32 bit GCC runtime is a pile of shit
967 uint64_t tmr_ticks = 0;
969 uint32_t tmr_ticks = 0;
972 uchar_t tmr_div = *(uchar_t *)&(apic->tmr_div_cfg.val);
973 uint_t shift_num = 0;
976 // Check whether this is true:
977 // -> If the Init count is zero then the timer is disabled
978 // and doesn't just blitz interrupts to the CPU
979 if ((apic->tmr_init_cnt == 0) ||
980 ( (apic->tmr_vec_tbl.tmr_mode == APIC_TMR_ONESHOT) &&
981 (apic->tmr_cur_cnt == 0))) {
982 //PrintDebug("APIC timer not yet initialized\n");
1000 case APIC_TMR_DIV16:
1003 case APIC_TMR_DIV32:
1006 case APIC_TMR_DIV64:
1009 case APIC_TMR_DIV128:
1013 PrintError("Invalid Timer Divider configuration\n");
1017 tmr_ticks = cpu_cycles >> shift_num;
1018 // PrintDebug("Timer Ticks: %p\n", (void *)tmr_ticks);
1020 if (tmr_ticks < apic->tmr_cur_cnt) {
1021 apic->tmr_cur_cnt -= tmr_ticks;
1023 tmr_ticks -= apic->tmr_cur_cnt;
1024 apic->tmr_cur_cnt = 0;
1027 PrintDebug("Raising APIC Timer interrupt (periodic=%d) (icnt=%d) (div=%d)\n",
1028 apic->tmr_vec_tbl.tmr_mode, apic->tmr_init_cnt, shift_num);
1030 if (apic_intr_pending(dev->vm, priv_data)) {
1031 PrintDebug("Overriding pending IRQ %d\n", apic_get_intr_number(dev->vm, priv_data));
1034 if (activate_internal_irq(apic, APIC_TMR_INT) == -1) {
1035 PrintError("Could not raise Timer interrupt\n");
1038 if (apic->tmr_vec_tbl.tmr_mode == APIC_TMR_PERIODIC) {
1039 tmr_ticks = tmr_ticks % apic->tmr_init_cnt;
1040 apic->tmr_cur_cnt = apic->tmr_init_cnt - tmr_ticks;
1047 static void apic_incoming_ipi(void *val)
1049 PrintError("In apic_incoming_ipi, val=%p\n", val);
1050 struct int_cmd_reg int_cmd;
1051 char *type = NULL, *dest;
1053 int_cmd.val = (uint64_t)val;
1054 switch (int_cmd.dst_shorthand)
1057 sprintf(foo, "%d", int_cmd.dst);
1064 dest = "(broadcast inclusive)";
1067 dest = "(broadcast)";
1070 switch (int_cmd.msg_type)
1085 PrintError("Receieved IPI on CPU %d type=%s dest=%s\n",
1086 V3_Get_CPU(), type, dest);
1087 //%p %s to CPU %d on CPU %d.\n", val, foo, type, dest, (int)V3_Get_CPU());
1092 static struct intr_ctrl_ops intr_ops = {
1093 .intr_pending = apic_intr_pending,
1094 .get_intr_number = apic_get_intr_number,
1095 .raise_intr = apic_raise_intr,
1096 .begin_irq = apic_begin_irq,
1097 .lower_intr = apic_lower_intr,
1101 static struct vm_timer_ops timer_ops = {
1102 .update_time = apic_update_time,
1108 static int apic_free(struct vm_device * dev) {
1109 struct guest_info * info = dev->vm;
1111 v3_unhook_msr(info, BASE_ADDR_MSR);
1117 static struct v3_device_ops dev_ops = {
1126 static int apic_init(struct guest_info * vm, v3_cfg_tree_t * cfg) {
1127 PrintDebug("Creating APIC\n");
1128 char * name = v3_cfg_val(cfg, "name");
1130 struct apic_state * apic = (struct apic_state *)V3_Malloc(sizeof(struct apic_state));
1132 struct vm_device * dev = v3_allocate_device(name, &dev_ops, apic);
1134 if (v3_attach_device(vm, dev) == -1) {
1135 PrintError("Could not attach device %s\n", name);
1139 v3_register_intr_controller(vm, &intr_ops, dev);
1140 v3_add_timer(vm, &timer_ops, dev);
1142 init_apic_state(apic);
1144 v3_hook_msr(vm, BASE_ADDR_MSR, read_apic_msr, write_apic_msr, dev);
1146 v3_hook_full_mem(vm, apic->base_addr, apic->base_addr + PAGE_SIZE_4KB, apic_read, apic_write, dev);
1153 device_register("LAPIC", apic_init)