2 * This file is part of the Palacios Virtual Machine Monitor developed
3 * by the V3VEE Project with funding from the United States National
4 * Science Foundation and the Department of Energy.
6 * The V3VEE Project is a joint project between Northwestern University
7 * and the University of New Mexico. You can find out more at
10 * Copyright (c) 2008, Jack Lange <jarusl@cs.northwestern.edu>
11 * Copyright (c) 2008, The V3VEE Project <http://www.v3vee.org>
12 * All rights reserved.
14 * Author: Jack Lange <jarusl@cs.northwestern.edu>
16 * This is free software. You are permitted to use,
17 * redistribute, and modify it as specified in the file "V3VEE_LICENSE".
21 #include <devices/apic.h>
22 #include <devices/apic_regs.h>
23 #include <palacios/vmm.h>
24 #include <palacios/vmm_msr.h>
27 #ifndef CONFIG_DEBUG_APIC
29 #define PrintDebug(fmt, args...)
33 typedef enum { APIC_TMR_INT, APIC_THERM_INT, APIC_PERF_INT,
34 APIC_LINT0_INT, APIC_LINT1_INT, APIC_ERR_INT } apic_irq_type_t;
36 #define APIC_FIXED_DELIVERY 0x0
37 #define APIC_SMI_DELIVERY 0x2
38 #define APIC_NMI_DELIVERY 0x4
39 #define APIC_INIT_DELIVERY 0x5
40 #define APIC_EXTINT_DELIVERY 0x7
43 #define BASE_ADDR_MSR 0x0000001B
44 #define DEFAULT_BASE_ADDR 0xfee00000
46 #define APIC_ID_OFFSET 0x020
47 #define APIC_VERSION_OFFSET 0x030
48 #define TPR_OFFSET 0x080
49 #define APR_OFFSET 0x090
50 #define PPR_OFFSET 0x0a0
51 #define EOI_OFFSET 0x0b0
52 #define REMOTE_READ_OFFSET 0x0c0
53 #define LDR_OFFSET 0x0d0
54 #define DFR_OFFSET 0x0e0
55 #define SPURIOUS_INT_VEC_OFFSET 0x0f0
57 #define ISR_OFFSET0 0x100 // 0x100 - 0x170
58 #define ISR_OFFSET1 0x110 // 0x100 - 0x170
59 #define ISR_OFFSET2 0x120 // 0x100 - 0x170
60 #define ISR_OFFSET3 0x130 // 0x100 - 0x170
61 #define ISR_OFFSET4 0x140 // 0x100 - 0x170
62 #define ISR_OFFSET5 0x150 // 0x100 - 0x170
63 #define ISR_OFFSET6 0x160 // 0x100 - 0x170
64 #define ISR_OFFSET7 0x170 // 0x100 - 0x170
66 #define TRIG_OFFSET0 0x180 // 0x180 - 0x1f0
67 #define TRIG_OFFSET1 0x190 // 0x180 - 0x1f0
68 #define TRIG_OFFSET2 0x1a0 // 0x180 - 0x1f0
69 #define TRIG_OFFSET3 0x1b0 // 0x180 - 0x1f0
70 #define TRIG_OFFSET4 0x1c0 // 0x180 - 0x1f0
71 #define TRIG_OFFSET5 0x1d0 // 0x180 - 0x1f0
72 #define TRIG_OFFSET6 0x1e0 // 0x180 - 0x1f0
73 #define TRIG_OFFSET7 0x1f0 // 0x180 - 0x1f0
76 #define IRR_OFFSET0 0x200 // 0x200 - 0x270
77 #define IRR_OFFSET1 0x210 // 0x200 - 0x270
78 #define IRR_OFFSET2 0x220 // 0x200 - 0x270
79 #define IRR_OFFSET3 0x230 // 0x200 - 0x270
80 #define IRR_OFFSET4 0x240 // 0x200 - 0x270
81 #define IRR_OFFSET5 0x250 // 0x200 - 0x270
82 #define IRR_OFFSET6 0x260 // 0x200 - 0x270
83 #define IRR_OFFSET7 0x270 // 0x200 - 0x270
86 #define ESR_OFFSET 0x280
87 #define INT_CMD_LO_OFFSET 0x300
88 #define INT_CMD_HI_OFFSET 0x310
89 #define TMR_LOC_VEC_TBL_OFFSET 0x320
90 #define THERM_LOC_VEC_TBL_OFFSET 0x330
91 #define PERF_CTR_LOC_VEC_TBL_OFFSET 0x340
92 #define LINT0_VEC_TBL_OFFSET 0x350
93 #define LINT1_VEC_TBL_OFFSET 0x360
94 #define ERR_VEC_TBL_OFFSET 0x370
95 #define TMR_INIT_CNT_OFFSET 0x380
96 #define TMR_CUR_CNT_OFFSET 0x390
97 #define TMR_DIV_CFG_OFFSET 0x3e0
98 #define EXT_APIC_FEATURE_OFFSET 0x400
99 #define EXT_APIC_CMD_OFFSET 0x410
100 #define SEOI_OFFSET 0x420
102 #define IER_OFFSET0 0x480 // 0x480 - 0x4f0
103 #define IER_OFFSET1 0x490 // 0x480 - 0x4f0
104 #define IER_OFFSET2 0x4a0 // 0x480 - 0x4f0
105 #define IER_OFFSET3 0x4b0 // 0x480 - 0x4f0
106 #define IER_OFFSET4 0x4c0 // 0x480 - 0x4f0
107 #define IER_OFFSET5 0x4d0 // 0x480 - 0x4f0
108 #define IER_OFFSET6 0x4e0 // 0x480 - 0x4f0
109 #define IER_OFFSET7 0x4f0 // 0x480 - 0x4f0
111 #define EXT_INT_LOC_VEC_TBL_OFFSET0 0x500 // 0x500 - 0x530
112 #define EXT_INT_LOC_VEC_TBL_OFFSET1 0x510 // 0x500 - 0x530
113 #define EXT_INT_LOC_VEC_TBL_OFFSET2 0x520 // 0x500 - 0x530
114 #define EXT_INT_LOC_VEC_TBL_OFFSET3 0x530 // 0x500 - 0x530
123 uint_t bootstrap_cpu : 1;
125 uint_t apic_enable : 1;
126 ullong_t base_addr : 40;
128 } __attribute__((packed));
129 } __attribute__((packed));
130 } __attribute__((packed));
139 v3_msr_t base_addr_msr;
142 /* memory map registers */
144 struct lapic_id_reg lapic_id;
145 struct apic_ver_reg apic_ver;
146 struct ext_apic_ctrl_reg ext_apic_ctrl;
147 struct local_vec_tbl_reg local_vec_tbl;
148 struct tmr_vec_tbl_reg tmr_vec_tbl;
149 struct tmr_div_cfg_reg tmr_div_cfg;
150 struct lint_vec_tbl_reg lint0_vec_tbl;
151 struct lint_vec_tbl_reg lint1_vec_tbl;
152 struct perf_ctr_loc_vec_tbl_reg perf_ctr_loc_vec_tbl;
153 struct therm_loc_vec_tbl_reg therm_loc_vec_tbl;
154 struct err_vec_tbl_reg err_vec_tbl;
155 struct err_status_reg err_status;
156 struct spurious_int_reg spurious_int;
157 struct int_cmd_reg int_cmd;
158 struct log_dst_reg log_dst;
159 struct dst_fmt_reg dst_fmt;
160 struct arb_prio_reg arb_prio;
161 struct task_prio_reg task_prio;
162 struct proc_prio_reg proc_prio;
163 struct ext_apic_feature_reg ext_apic_feature;
164 struct spec_eoi_reg spec_eoi;
167 uint32_t tmr_cur_cnt;
168 uint32_t tmr_init_cnt;
171 struct local_vec_tbl_reg ext_intr_vec_tbl[4];
173 uint32_t rem_rd_data;
176 uchar_t int_req_reg[32];
177 uchar_t int_svc_reg[32];
178 uchar_t int_en_reg[32];
179 uchar_t trig_mode_reg[32];
187 static void init_apic_state(struct apic_state * apic) {
188 apic->base_addr = DEFAULT_BASE_ADDR;
189 apic->base_addr_msr.value = 0x0000000000000900LL;
190 apic->base_addr_msr.value |= ((uint64_t)DEFAULT_BASE_ADDR);
192 PrintDebug("Sizeof Interrupt Request Register %d, should be 32\n",
193 (uint_t)sizeof(apic->int_req_reg));
195 memset(apic->int_req_reg, 0, sizeof(apic->int_req_reg));
196 memset(apic->int_svc_reg, 0, sizeof(apic->int_svc_reg));
197 memset(apic->int_en_reg, 0xff, sizeof(apic->int_en_reg));
198 memset(apic->trig_mode_reg, 0, sizeof(apic->trig_mode_reg));
200 apic->eoi = 0x00000000;
201 apic->rem_rd_data = 0x00000000;
202 apic->tmr_init_cnt = 0x00000000;
203 apic->tmr_cur_cnt = 0x00000000;
206 // We need to figure out what the APIC ID is....
207 apic->lapic_id.val = 0x00000000;
209 // The P6 has 6 LVT entries, so we set the value to (6-1)...
210 apic->apic_ver.val = 0x80050010;
212 apic->task_prio.val = 0x00000000;
213 apic->arb_prio.val = 0x00000000;
214 apic->proc_prio.val = 0x00000000;
215 apic->log_dst.val = 0x00000000;
216 apic->dst_fmt.val = 0xffffffff;
217 apic->spurious_int.val = 0x000000ff;
218 apic->err_status.val = 0x00000000;
219 apic->int_cmd.val = 0x0000000000000000LL;
220 apic->tmr_vec_tbl.val = 0x00010000;
221 apic->therm_loc_vec_tbl.val = 0x00010000;
222 apic->perf_ctr_loc_vec_tbl.val = 0x00010000;
223 apic->lint0_vec_tbl.val = 0x00010000;
224 apic->lint1_vec_tbl.val = 0x00010000;
225 apic->err_vec_tbl.val = 0x00010000;
226 apic->tmr_div_cfg.val = 0x00000000;
227 //apic->ext_apic_feature.val = 0x00000007;
228 apic->ext_apic_feature.val = 0x00040007;
229 apic->ext_apic_ctrl.val = 0x00000000;
230 apic->spec_eoi.val = 0x00000000;
236 static int read_apic_msr(uint_t msr, v3_msr_t * dst, void * priv_data) {
237 struct vm_device * dev = (struct vm_device *)priv_data;
238 struct apic_state * apic = (struct apic_state *)dev->private_data;
239 dst->value = apic->base_addr;
244 static int write_apic_msr(uint_t msr, v3_msr_t src, void * priv_data) {
245 // struct vm_device * dev = (struct vm_device *)priv_data;
246 // struct apic_state * apic = (struct apic_state *)dev->private_data;
248 PrintError("WRITING APIC BASE ADDR: HI=%x LO=%x\n", src.hi, src.lo);
254 // irq_num is the bit offset into a 256 bit buffer...
255 static int activate_apic_irq(struct apic_state * apic, uint32_t irq_num) {
256 int major_offset = (irq_num & ~0x00000007) >> 3;
257 int minor_offset = irq_num & 0x00000007;
258 uchar_t * req_location = apic->int_req_reg + major_offset;
259 uchar_t * en_location = apic->int_en_reg + major_offset;
260 uchar_t flag = 0x1 << minor_offset;
263 PrintError("Attempting to raise an invalid interrupt: %d\n", irq_num);
267 PrintDebug("Raising APIC IRQ %d\n", irq_num);
269 if (*en_location & flag) {
270 *req_location |= flag;
272 PrintDebug("Interrupt not enabled... %.2x\n", *en_location);
281 static int get_highest_isr(struct apic_state * apic) {
284 // We iterate backwards to find the highest priority
285 for (i = 31; i >= 0; i--) {
286 uchar_t * svc_major = apic->int_svc_reg + i;
288 if ((*svc_major) & 0xff) {
289 for (j = 7; j >= 0; j--) {
290 uchar_t flag = 0x1 << j;
291 if ((*svc_major) & flag) {
292 return ((i * 8) + j);
303 static int get_highest_irr(struct apic_state * apic) {
306 // We iterate backwards to find the highest priority
307 for (i = 31; i >= 0; i--) {
308 uchar_t * req_major = apic->int_req_reg + i;
310 if ((*req_major) & 0xff) {
311 for (j = 7; j >= 0; j--) {
312 uchar_t flag = 0x1 << j;
313 if ((*req_major) & flag) {
314 return ((i * 8) + j);
326 static int apic_do_eoi(struct apic_state * apic) {
327 int isr_irq = get_highest_isr(apic);
330 int major_offset = (isr_irq & ~0x00000007) >> 3;
331 int minor_offset = isr_irq & 0x00000007;
332 uchar_t flag = 0x1 << minor_offset;
333 uchar_t * svc_location = apic->int_svc_reg + major_offset;
335 PrintDebug("Received APIC EOI for IRQ %d\n", isr_irq);
337 *svc_location &= ~flag;
339 #ifdef CONFIG_CRAY_XT
341 if ((isr_irq == 238) ||
343 PrintError("Acking IRQ %d\n", isr_irq);
346 if (isr_irq == 238) {
351 PrintError("Spurious EOI...\n");
358 static int activate_internal_irq(struct apic_state * apic, apic_irq_type_t int_type) {
359 uint32_t vec_num = 0;
360 uint32_t del_mode = 0;
366 vec_num = apic->tmr_vec_tbl.vec;
367 del_mode = APIC_FIXED_DELIVERY;
368 masked = apic->tmr_vec_tbl.mask;
371 vec_num = apic->therm_loc_vec_tbl.vec;
372 del_mode = apic->therm_loc_vec_tbl.msg_type;
373 masked = apic->therm_loc_vec_tbl.mask;
376 vec_num = apic->perf_ctr_loc_vec_tbl.vec;
377 del_mode = apic->perf_ctr_loc_vec_tbl.msg_type;
378 masked = apic->perf_ctr_loc_vec_tbl.mask;
381 vec_num = apic->lint0_vec_tbl.vec;
382 del_mode = apic->lint0_vec_tbl.msg_type;
383 masked = apic->lint0_vec_tbl.mask;
386 vec_num = apic->lint1_vec_tbl.vec;
387 del_mode = apic->lint1_vec_tbl.msg_type;
388 masked = apic->lint1_vec_tbl.mask;
391 vec_num = apic->err_vec_tbl.vec;
392 del_mode = APIC_FIXED_DELIVERY;
393 masked = apic->err_vec_tbl.mask;
396 PrintError("Invalid APIC interrupt type\n");
400 // interrupt is masked, don't send
402 PrintDebug("Inerrupt is masked\n");
406 if (del_mode == APIC_FIXED_DELIVERY) {
407 //PrintDebug("Activating internal APIC IRQ %d\n", vec_num);
408 return activate_apic_irq(apic, vec_num);
410 PrintError("Unhandled Delivery Mode\n");
416 static int apic_read(addr_t guest_addr, void * dst, uint_t length, void * priv_data) {
417 struct vm_device * dev = (struct vm_device *)priv_data;
418 struct apic_state * apic = (struct apic_state *)dev->private_data;
419 addr_t reg_addr = guest_addr - apic->base_addr;
420 struct apic_msr * msr = (struct apic_msr *)&(apic->base_addr_msr.value);
424 PrintDebug("Read apic address space (%p)\n",
427 if (msr->apic_enable == 0) {
428 PrintError("Write to APIC address space with disabled APIC\n");
433 /* Because "May not be supported" doesn't matter to Linux developers... */
434 /* if (length != 4) { */
435 /* PrintError("Invalid apic read length (%d)\n", length); */
439 switch (reg_addr & ~0x3) {
441 // Well, only an idiot would read from a architectural write only register
443 // PrintError("Attempting to read from write only register\n");
449 val = apic->lapic_id.val;
451 case APIC_VERSION_OFFSET:
452 val = apic->apic_ver.val;
455 val = apic->task_prio.val;
458 val = apic->arb_prio.val;
461 val = apic->proc_prio.val;
463 case REMOTE_READ_OFFSET:
464 val = apic->rem_rd_data;
467 val = apic->log_dst.val;
470 val = apic->dst_fmt.val;
472 case SPURIOUS_INT_VEC_OFFSET:
473 val = apic->spurious_int.val;
476 val = apic->err_status.val;
478 case TMR_LOC_VEC_TBL_OFFSET:
479 val = apic->tmr_vec_tbl.val;
481 case LINT0_VEC_TBL_OFFSET:
482 val = apic->lint0_vec_tbl.val;
484 case LINT1_VEC_TBL_OFFSET:
485 val = apic->lint1_vec_tbl.val;
487 case ERR_VEC_TBL_OFFSET:
488 val = apic->err_vec_tbl.val;
490 case TMR_INIT_CNT_OFFSET:
491 val = apic->tmr_init_cnt;
493 case TMR_DIV_CFG_OFFSET:
494 val = apic->tmr_div_cfg.val;
498 val = *(uint32_t *)(apic->int_en_reg);
501 val = *(uint32_t *)(apic->int_en_reg + 4);
504 val = *(uint32_t *)(apic->int_en_reg + 8);
507 val = *(uint32_t *)(apic->int_en_reg + 12);
510 val = *(uint32_t *)(apic->int_en_reg + 16);
513 val = *(uint32_t *)(apic->int_en_reg + 20);
516 val = *(uint32_t *)(apic->int_en_reg + 24);
519 val = *(uint32_t *)(apic->int_en_reg + 28);
523 val = *(uint32_t *)(apic->int_svc_reg);
526 val = *(uint32_t *)(apic->int_svc_reg + 4);
529 val = *(uint32_t *)(apic->int_svc_reg + 8);
532 val = *(uint32_t *)(apic->int_svc_reg + 12);
535 val = *(uint32_t *)(apic->int_svc_reg + 16);
538 val = *(uint32_t *)(apic->int_svc_reg + 20);
541 val = *(uint32_t *)(apic->int_svc_reg + 24);
544 val = *(uint32_t *)(apic->int_svc_reg + 28);
548 val = *(uint32_t *)(apic->trig_mode_reg);
551 val = *(uint32_t *)(apic->trig_mode_reg + 4);
554 val = *(uint32_t *)(apic->trig_mode_reg + 8);
557 val = *(uint32_t *)(apic->trig_mode_reg + 12);
560 val = *(uint32_t *)(apic->trig_mode_reg + 16);
563 val = *(uint32_t *)(apic->trig_mode_reg + 20);
566 val = *(uint32_t *)(apic->trig_mode_reg + 24);
569 val = *(uint32_t *)(apic->trig_mode_reg + 28);
573 val = *(uint32_t *)(apic->int_req_reg);
576 val = *(uint32_t *)(apic->int_req_reg + 4);
579 val = *(uint32_t *)(apic->int_req_reg + 8);
582 val = *(uint32_t *)(apic->int_req_reg + 12);
585 val = *(uint32_t *)(apic->int_req_reg + 16);
588 val = *(uint32_t *)(apic->int_req_reg + 20);
591 val = *(uint32_t *)(apic->int_req_reg + 24);
594 val = *(uint32_t *)(apic->int_req_reg + 28);
596 case TMR_CUR_CNT_OFFSET:
597 val = apic->tmr_cur_cnt;
600 // We are not going to implement these....
601 case THERM_LOC_VEC_TBL_OFFSET:
602 val = apic->therm_loc_vec_tbl.val;
604 case PERF_CTR_LOC_VEC_TBL_OFFSET:
605 val = apic->perf_ctr_loc_vec_tbl.val;
611 case INT_CMD_LO_OFFSET:
612 val = apic->int_cmd.lo;
614 case INT_CMD_HI_OFFSET:
615 val = apic->int_cmd.hi;
618 // handle current timer count
620 // Unhandled Registers
621 case EXT_INT_LOC_VEC_TBL_OFFSET0:
622 val = apic->ext_intr_vec_tbl[0].val;
624 case EXT_INT_LOC_VEC_TBL_OFFSET1:
625 val = apic->ext_intr_vec_tbl[1].val;
627 case EXT_INT_LOC_VEC_TBL_OFFSET2:
628 val = apic->ext_intr_vec_tbl[2].val;
630 case EXT_INT_LOC_VEC_TBL_OFFSET3:
631 val = apic->ext_intr_vec_tbl[3].val;
635 case EXT_APIC_FEATURE_OFFSET:
636 case EXT_APIC_CMD_OFFSET:
640 PrintError("Read from Unhandled APIC Register: %x\n", (uint32_t)reg_addr);
646 uint_t byte_addr = reg_addr & 0x3;
647 uint8_t * val_ptr = (uint8_t *)dst;
649 *val_ptr = *(((uint8_t *)&val) + byte_addr);
651 } else if ((length == 2) &&
652 ((reg_addr & 0x3) == 0x3)) {
653 uint_t byte_addr = reg_addr & 0x3;
654 uint16_t * val_ptr = (uint16_t *)dst;
655 *val_ptr = *(((uint16_t *)&val) + byte_addr);
657 } else if (length == 4) {
658 uint32_t * val_ptr = (uint32_t *)dst;
662 PrintError("Invalid apic read length (%d)\n", length);
666 PrintDebug("Read finished (val=%x)\n", *(uint32_t *)dst);
672 static int apic_write(addr_t guest_addr, void * src, uint_t length, void * priv_data) {
673 struct vm_device * dev = (struct vm_device *)priv_data;
674 struct apic_state * apic = (struct apic_state *)dev->private_data;
675 addr_t reg_addr = guest_addr - apic->base_addr;
676 struct apic_msr * msr = (struct apic_msr *)&(apic->base_addr_msr.value);
677 uint32_t op_val = *(uint32_t *)src;
679 PrintDebug("Write to apic address space (%p) (val=%x)\n",
680 (void *)guest_addr, *(uint32_t *)src);
682 if (msr->apic_enable == 0) {
683 PrintError("Write to APIC address space with disabled APIC\n");
689 PrintError("Invalid apic write length (%d)\n", length);
694 case REMOTE_READ_OFFSET:
695 case APIC_VERSION_OFFSET:
722 case EXT_APIC_FEATURE_OFFSET:
724 PrintError("Attempting to write to read only register %p (ignored)\n", (void *)reg_addr);
726 PrintError("Attempting to write to read only register %p (error)\n", (void *)reg_addr);
733 apic->lapic_id.val = op_val;
736 apic->task_prio.val = op_val;
739 apic->log_dst.val = op_val;
742 apic->dst_fmt.val = op_val;
744 case SPURIOUS_INT_VEC_OFFSET:
745 apic->spurious_int.val = op_val;
748 apic->err_status.val = op_val;
750 case TMR_LOC_VEC_TBL_OFFSET:
751 apic->tmr_vec_tbl.val = op_val;
753 case THERM_LOC_VEC_TBL_OFFSET:
754 apic->therm_loc_vec_tbl.val = op_val;
756 case PERF_CTR_LOC_VEC_TBL_OFFSET:
757 apic->perf_ctr_loc_vec_tbl.val = op_val;
759 case LINT0_VEC_TBL_OFFSET:
760 apic->lint0_vec_tbl.val = op_val;
762 case LINT1_VEC_TBL_OFFSET:
763 apic->lint1_vec_tbl.val = op_val;
765 case ERR_VEC_TBL_OFFSET:
766 apic->err_vec_tbl.val = op_val;
768 case TMR_INIT_CNT_OFFSET:
769 apic->tmr_init_cnt = op_val;
770 apic->tmr_cur_cnt = op_val;
772 case TMR_CUR_CNT_OFFSET:
773 apic->tmr_cur_cnt = op_val;
775 case TMR_DIV_CFG_OFFSET:
776 apic->tmr_div_cfg.val = op_val;
780 // Enable mask (256 bits)
782 *(uint32_t *)(apic->int_en_reg) = op_val;
785 *(uint32_t *)(apic->int_en_reg + 4) = op_val;
788 *(uint32_t *)(apic->int_en_reg + 8) = op_val;
791 *(uint32_t *)(apic->int_en_reg + 12) = op_val;
794 *(uint32_t *)(apic->int_en_reg + 16) = op_val;
797 *(uint32_t *)(apic->int_en_reg + 20) = op_val;
800 *(uint32_t *)(apic->int_en_reg + 24) = op_val;
803 *(uint32_t *)(apic->int_en_reg + 28) = op_val;
806 case EXT_INT_LOC_VEC_TBL_OFFSET0:
807 apic->ext_intr_vec_tbl[0].val = op_val;
809 case EXT_INT_LOC_VEC_TBL_OFFSET1:
810 apic->ext_intr_vec_tbl[1].val = op_val;
812 case EXT_INT_LOC_VEC_TBL_OFFSET2:
813 apic->ext_intr_vec_tbl[2].val = op_val;
815 case EXT_INT_LOC_VEC_TBL_OFFSET3:
816 apic->ext_intr_vec_tbl[3].val = op_val;
826 case INT_CMD_LO_OFFSET:
827 case INT_CMD_HI_OFFSET:
828 // Unhandled Registers
830 case EXT_APIC_CMD_OFFSET:
833 PrintError("Write to Unhandled APIC Register: %x\n", (uint32_t)reg_addr);
837 PrintDebug("Write finished\n");
844 /* Interrupt Controller Functions */
846 // returns 1 if an interrupt is pending, 0 otherwise
847 static int apic_intr_pending(struct guest_info * info, void * private_data) {
848 struct vm_device * dev = (struct vm_device *)private_data;
849 struct apic_state * apic = (struct apic_state *)dev->private_data;
850 int req_irq = get_highest_irr(apic);
851 int svc_irq = get_highest_isr(apic);
853 if ((req_irq >= 0) &&
854 (req_irq > svc_irq)) {
861 static int apic_get_intr_number(struct guest_info * info, void * private_data) {
862 struct vm_device * dev = (struct vm_device *)private_data;
863 struct apic_state * apic = (struct apic_state *)dev->private_data;
864 int req_irq = get_highest_irr(apic);
865 int svc_irq = get_highest_isr(apic);
869 } else if (svc_irq < req_irq) {
876 static int apic_raise_intr(struct guest_info * info, void * private_data, int irq) {
877 #ifdef CONFIG_CRAY_XT
878 // The Seastar is connected directly to the LAPIC via LINT0 on the ICC bus
881 struct vm_device * dev = (struct vm_device *)private_data;
882 struct apic_state * apic = (struct apic_state *)dev->private_data;
884 return activate_apic_irq(apic, irq);
891 static int apic_lower_intr(struct guest_info * info, void * private_data, int irq) {
895 static int apic_begin_irq(struct guest_info * info, void * private_data, int irq) {
896 struct vm_device * dev = (struct vm_device *)private_data;
897 struct apic_state * apic = (struct apic_state *)dev->private_data;
898 int major_offset = (irq & ~0x00000007) >> 3;
899 int minor_offset = irq & 0x00000007;
900 uchar_t * req_location = apic->int_req_reg + major_offset;
901 uchar_t * svc_location = apic->int_svc_reg + major_offset;
902 uchar_t flag = 0x01 << minor_offset;
904 *svc_location |= flag;
905 *req_location &= ~flag;
907 #ifdef CONFIG_CRAY_XT
908 if ((irq == 238) || (irq == 239)) {
909 PrintError("APIC: Begin IRQ %d (ISR=%x), (IRR=%x)\n", irq, *svc_location, *req_location);
918 int v3_apic_raise_intr(struct guest_info * info, struct vm_device * apic_dev, int intr_num) {
919 struct apic_state * apic = (struct apic_state *)apic_dev->private_data;
921 if (activate_apic_irq(apic, intr_num) == -1) {
922 PrintError("Error: Could not activate apic_irq\n");
926 v3_interrupt_cpu(info, 0);
933 /* Timer Functions */
934 static void apic_update_time(ullong_t cpu_cycles, ullong_t cpu_freq, void * priv_data) {
935 struct vm_device * dev = (struct vm_device *)priv_data;
936 struct apic_state * apic = (struct apic_state *)dev->private_data;
937 // The 32 bit GCC runtime is a pile of shit
939 uint64_t tmr_ticks = 0;
941 uint32_t tmr_ticks = 0;
944 uchar_t tmr_div = *(uchar_t *)&(apic->tmr_div_cfg.val);
945 uint_t shift_num = 0;
948 // Check whether this is true:
949 // -> If the Init count is zero then the timer is disabled
950 // and doesn't just blitz interrupts to the CPU
951 if ((apic->tmr_init_cnt == 0) ||
952 ( (apic->tmr_vec_tbl.tmr_mode == APIC_TMR_ONESHOT) &&
953 (apic->tmr_cur_cnt == 0))) {
954 //PrintDebug("APIC timer not yet initialized\n");
981 case APIC_TMR_DIV128:
985 PrintError("Invalid Timer Divider configuration\n");
989 tmr_ticks = cpu_cycles >> shift_num;
990 // PrintDebug("Timer Ticks: %p\n", (void *)tmr_ticks);
992 if (tmr_ticks < apic->tmr_cur_cnt) {
993 apic->tmr_cur_cnt -= tmr_ticks;
995 tmr_ticks -= apic->tmr_cur_cnt;
996 apic->tmr_cur_cnt = 0;
999 PrintDebug("Raising APIC Timer interrupt (periodic=%d) (icnt=%d) (div=%d)\n",
1000 apic->tmr_vec_tbl.tmr_mode, apic->tmr_init_cnt, shift_num);
1002 if (apic_intr_pending(dev->vm, priv_data)) {
1003 PrintDebug("Overriding pending IRQ %d\n", apic_get_intr_number(priv_data));
1006 if (activate_internal_irq(apic, APIC_TMR_INT) == -1) {
1007 PrintError("Could not raise Timer interrupt\n");
1010 if (apic->tmr_vec_tbl.tmr_mode == APIC_TMR_PERIODIC) {
1011 tmr_ticks = tmr_ticks % apic->tmr_init_cnt;
1012 apic->tmr_cur_cnt = apic->tmr_init_cnt - tmr_ticks;
1021 static struct intr_ctrl_ops intr_ops = {
1022 .intr_pending = apic_intr_pending,
1023 .get_intr_number = apic_get_intr_number,
1024 .raise_intr = apic_raise_intr,
1025 .begin_irq = apic_begin_irq,
1026 .lower_intr = apic_lower_intr,
1030 static struct vm_timer_ops timer_ops = {
1031 .update_time = apic_update_time,
1037 static int apic_free(struct vm_device * dev) {
1038 struct guest_info * info = dev->vm;
1040 v3_unhook_msr(info, BASE_ADDR_MSR);
1046 static struct v3_device_ops dev_ops = {
1055 static int apic_init(struct guest_info * vm, void * cfg_data) {
1056 PrintDebug("Creating APIC\n");
1058 struct apic_state * apic = (struct apic_state *)V3_Malloc(sizeof(struct apic_state));
1060 struct vm_device * dev = v3_allocate_device("LAPIC", &dev_ops, apic);
1062 if (v3_attach_device(vm, dev) == -1) {
1063 PrintError("Could not attach device %s\n", "LAPIC");
1067 v3_register_intr_controller(vm, &intr_ops, dev);
1068 v3_add_timer(vm, &timer_ops, dev);
1070 init_apic_state(apic);
1072 v3_hook_msr(vm, BASE_ADDR_MSR, read_apic_msr, write_apic_msr, dev);
1074 v3_hook_full_mem(vm, apic->base_addr, apic->base_addr + PAGE_SIZE_4KB, apic_read, apic_write, dev);
1081 device_register("LAPIC", apic_init)