2 * This file is part of the Palacios Virtual Machine Monitor developed
3 * by the V3VEE Project with funding from the United States National
4 * Science Foundation and the Department of Energy.
6 * The V3VEE Project is a joint project between Northwestern University
7 * and the University of New Mexico. You can find out more at
10 * Copyright (c) 2008, Jack Lange <jarusl@cs.northwestern.edu>
11 * Copyright (c) 2008, The V3VEE Project <http://www.v3vee.org>
12 * All rights reserved.
14 * Author: Jack Lange <jarusl@cs.northwestern.edu>
16 * This is free software. You are permitted to use,
17 * redistribute, and modify it as specified in the file "V3VEE_LICENSE".
21 #include <devices/apic.h>
22 #include <devices/apic_regs.h>
23 #include <palacios/vmm.h>
24 #include <palacios/vmm_msr.h>
25 #include <palacios/vmm_sprintf.h>
26 #include <palacios/vm_guest.h>
27 #include <palacios/vmm_types.h>
30 #ifndef CONFIG_DEBUG_APIC
32 #define PrintDebug(fmt, args...)
36 typedef enum { APIC_TMR_INT, APIC_THERM_INT, APIC_PERF_INT,
37 APIC_LINT0_INT, APIC_LINT1_INT, APIC_ERR_INT } apic_irq_type_t;
39 #define APIC_FIXED_DELIVERY 0x0
40 #define APIC_SMI_DELIVERY 0x2
41 #define APIC_NMI_DELIVERY 0x4
42 #define APIC_INIT_DELIVERY 0x5
43 #define APIC_EXTINT_DELIVERY 0x7
46 #define BASE_ADDR_MSR 0x0000001B
47 #define DEFAULT_BASE_ADDR 0xfee00000
49 #define APIC_ID_OFFSET 0x020
50 #define APIC_VERSION_OFFSET 0x030
51 #define TPR_OFFSET 0x080
52 #define APR_OFFSET 0x090
53 #define PPR_OFFSET 0x0a0
54 #define EOI_OFFSET 0x0b0
55 #define REMOTE_READ_OFFSET 0x0c0
56 #define LDR_OFFSET 0x0d0
57 #define DFR_OFFSET 0x0e0
58 #define SPURIOUS_INT_VEC_OFFSET 0x0f0
60 #define ISR_OFFSET0 0x100 // 0x100 - 0x170
61 #define ISR_OFFSET1 0x110 // 0x100 - 0x170
62 #define ISR_OFFSET2 0x120 // 0x100 - 0x170
63 #define ISR_OFFSET3 0x130 // 0x100 - 0x170
64 #define ISR_OFFSET4 0x140 // 0x100 - 0x170
65 #define ISR_OFFSET5 0x150 // 0x100 - 0x170
66 #define ISR_OFFSET6 0x160 // 0x100 - 0x170
67 #define ISR_OFFSET7 0x170 // 0x100 - 0x170
69 #define TRIG_OFFSET0 0x180 // 0x180 - 0x1f0
70 #define TRIG_OFFSET1 0x190 // 0x180 - 0x1f0
71 #define TRIG_OFFSET2 0x1a0 // 0x180 - 0x1f0
72 #define TRIG_OFFSET3 0x1b0 // 0x180 - 0x1f0
73 #define TRIG_OFFSET4 0x1c0 // 0x180 - 0x1f0
74 #define TRIG_OFFSET5 0x1d0 // 0x180 - 0x1f0
75 #define TRIG_OFFSET6 0x1e0 // 0x180 - 0x1f0
76 #define TRIG_OFFSET7 0x1f0 // 0x180 - 0x1f0
79 #define IRR_OFFSET0 0x200 // 0x200 - 0x270
80 #define IRR_OFFSET1 0x210 // 0x200 - 0x270
81 #define IRR_OFFSET2 0x220 // 0x200 - 0x270
82 #define IRR_OFFSET3 0x230 // 0x200 - 0x270
83 #define IRR_OFFSET4 0x240 // 0x200 - 0x270
84 #define IRR_OFFSET5 0x250 // 0x200 - 0x270
85 #define IRR_OFFSET6 0x260 // 0x200 - 0x270
86 #define IRR_OFFSET7 0x270 // 0x200 - 0x270
89 #define ESR_OFFSET 0x280
90 #define INT_CMD_LO_OFFSET 0x300
91 #define INT_CMD_HI_OFFSET 0x310
92 #define TMR_LOC_VEC_TBL_OFFSET 0x320
93 #define THERM_LOC_VEC_TBL_OFFSET 0x330
94 #define PERF_CTR_LOC_VEC_TBL_OFFSET 0x340
95 #define LINT0_VEC_TBL_OFFSET 0x350
96 #define LINT1_VEC_TBL_OFFSET 0x360
97 #define ERR_VEC_TBL_OFFSET 0x370
98 #define TMR_INIT_CNT_OFFSET 0x380
99 #define TMR_CUR_CNT_OFFSET 0x390
100 #define TMR_DIV_CFG_OFFSET 0x3e0
101 #define EXT_APIC_FEATURE_OFFSET 0x400
102 #define EXT_APIC_CMD_OFFSET 0x410
103 #define SEOI_OFFSET 0x420
105 #define IER_OFFSET0 0x480 // 0x480 - 0x4f0
106 #define IER_OFFSET1 0x490 // 0x480 - 0x4f0
107 #define IER_OFFSET2 0x4a0 // 0x480 - 0x4f0
108 #define IER_OFFSET3 0x4b0 // 0x480 - 0x4f0
109 #define IER_OFFSET4 0x4c0 // 0x480 - 0x4f0
110 #define IER_OFFSET5 0x4d0 // 0x480 - 0x4f0
111 #define IER_OFFSET6 0x4e0 // 0x480 - 0x4f0
112 #define IER_OFFSET7 0x4f0 // 0x480 - 0x4f0
114 #define EXT_INT_LOC_VEC_TBL_OFFSET0 0x500 // 0x500 - 0x530
115 #define EXT_INT_LOC_VEC_TBL_OFFSET1 0x510 // 0x500 - 0x530
116 #define EXT_INT_LOC_VEC_TBL_OFFSET2 0x520 // 0x500 - 0x530
117 #define EXT_INT_LOC_VEC_TBL_OFFSET3 0x530 // 0x500 - 0x530
128 uint8_t bootstrap_cpu : 1;
130 uint8_t apic_enable : 1;
131 uint64_t base_addr : 40;
133 } __attribute__((packed));
134 } __attribute__((packed));
135 } __attribute__((packed));
139 typedef enum {INIT, SIPI, STARTED} ipi_state_t;
141 struct apic_dev_state;
147 struct apic_msr base_addr_msr;
150 /* memory map registers */
152 struct lapic_id_reg lapic_id;
153 struct apic_ver_reg apic_ver;
154 struct ext_apic_ctrl_reg ext_apic_ctrl;
155 struct local_vec_tbl_reg local_vec_tbl;
156 struct tmr_vec_tbl_reg tmr_vec_tbl;
157 struct tmr_div_cfg_reg tmr_div_cfg;
158 struct lint_vec_tbl_reg lint0_vec_tbl;
159 struct lint_vec_tbl_reg lint1_vec_tbl;
160 struct perf_ctr_loc_vec_tbl_reg perf_ctr_loc_vec_tbl;
161 struct therm_loc_vec_tbl_reg therm_loc_vec_tbl;
162 struct err_vec_tbl_reg err_vec_tbl;
163 struct err_status_reg err_status;
164 struct spurious_int_reg spurious_int;
165 struct int_cmd_reg int_cmd;
166 struct log_dst_reg log_dst;
167 struct dst_fmt_reg dst_fmt;
168 struct arb_prio_reg arb_prio;
169 struct task_prio_reg task_prio;
170 struct proc_prio_reg proc_prio;
171 struct ext_apic_feature_reg ext_apic_feature;
172 struct spec_eoi_reg spec_eoi;
175 uint32_t tmr_cur_cnt;
176 uint32_t tmr_init_cnt;
179 struct local_vec_tbl_reg ext_intr_vec_tbl[4];
181 uint32_t rem_rd_data;
184 ipi_state_t ipi_state;
186 uint8_t int_req_reg[32];
187 uint8_t int_svc_reg[32];
188 uint8_t int_en_reg[32];
189 uint8_t trig_mode_reg[32];
191 struct guest_info * core;
201 struct apic_dev_state {
204 struct apic_state apics[0];
205 } __attribute__((packed));
209 static int apic_read(struct guest_info * core, addr_t guest_addr, void * dst, uint_t length, void * priv_data);
210 static int apic_write(struct guest_info * core, addr_t guest_addr, void * src, uint_t length, void * priv_data);
212 static void init_apic_state(struct apic_state * apic, uint32_t id) {
213 apic->base_addr = DEFAULT_BASE_ADDR;
216 // boot processor, enabled
217 apic->base_addr_msr.value = 0x0000000000000900LL;
219 // ap processor, enabled
220 apic->base_addr_msr.value = 0x0000000000000800LL;
223 // same base address regardless of ap or main
224 apic->base_addr_msr.value |= ((uint64_t)DEFAULT_BASE_ADDR);
226 PrintDebug("apic %u: (init_apic_state): msr=0x%llx\n",id, apic->base_addr_msr.value);
228 PrintDebug("apic %u: (init_apic_state): Sizeof Interrupt Request Register %d, should be 32\n",
229 id, (uint_t)sizeof(apic->int_req_reg));
231 memset(apic->int_req_reg, 0, sizeof(apic->int_req_reg));
232 memset(apic->int_svc_reg, 0, sizeof(apic->int_svc_reg));
233 memset(apic->int_en_reg, 0xff, sizeof(apic->int_en_reg));
234 memset(apic->trig_mode_reg, 0, sizeof(apic->trig_mode_reg));
236 apic->eoi = 0x00000000;
237 apic->rem_rd_data = 0x00000000;
238 apic->tmr_init_cnt = 0x00000000;
239 apic->tmr_cur_cnt = 0x00000000;
241 apic->lapic_id.val = id;
243 apic->ipi_state = INIT;
245 // The P6 has 6 LVT entries, so we set the value to (6-1)...
246 apic->apic_ver.val = 0x80050010;
248 apic->task_prio.val = 0x00000000;
249 apic->arb_prio.val = 0x00000000;
250 apic->proc_prio.val = 0x00000000;
251 apic->log_dst.val = 0x00000000;
252 apic->dst_fmt.val = 0xffffffff;
253 apic->spurious_int.val = 0x000000ff;
254 apic->err_status.val = 0x00000000;
255 apic->int_cmd.val = 0x0000000000000000LL;
256 apic->tmr_vec_tbl.val = 0x00010000;
257 apic->therm_loc_vec_tbl.val = 0x00010000;
258 apic->perf_ctr_loc_vec_tbl.val = 0x00010000;
259 apic->lint0_vec_tbl.val = 0x00010000;
260 apic->lint1_vec_tbl.val = 0x00010000;
261 apic->err_vec_tbl.val = 0x00010000;
262 apic->tmr_div_cfg.val = 0x00000000;
263 //apic->ext_apic_feature.val = 0x00000007;
264 apic->ext_apic_feature.val = 0x00040007;
265 apic->ext_apic_ctrl.val = 0x00000000;
266 apic->spec_eoi.val = 0x00000000;
268 v3_lock_init(&(apic->lock));
274 static int read_apic_msr(struct guest_info * core, uint_t msr, v3_msr_t * dst, void * priv_data) {
275 struct apic_dev_state * apic_dev = (struct apic_dev_state *)priv_data;
276 struct apic_state * apic = &(apic_dev->apics[core->cpu_id]);
278 PrintDebug("apic %u: core %u: MSR read\n", apic->lapic_id.val, core->cpu_id);
280 dst->value = apic->base_addr;
281 v3_unlock(apic->lock);
286 static int write_apic_msr(struct guest_info * core, uint_t msr, v3_msr_t src, void * priv_data) {
287 struct apic_dev_state * apic_dev = (struct apic_dev_state *)priv_data;
288 struct apic_state * apic = &(apic_dev->apics[core->cpu_id]);
289 struct v3_mem_region * old_reg = v3_get_mem_region(core->vm_info, core->cpu_id, apic->base_addr);
292 PrintDebug("apic %u: core %u: MSR write\n", apic->lapic_id.val, core->cpu_id);
294 if (old_reg == NULL) {
296 PrintError("apic %u: core %u: APIC Base address region does not exit...\n",
297 apic->lapic_id.val, core->cpu_id);
303 v3_delete_mem_region(core->vm_info, old_reg);
305 apic->base_addr = src.value;
307 if (v3_hook_full_mem(core->vm_info, core->cpu_id, apic->base_addr, apic->base_addr + PAGE_SIZE_4KB, apic_read, apic_write, apic_dev) == -1) {
308 PrintError("apic %u: core %u: Could not hook new APIC Base address\n",
309 apic->lapic_id.val, core->cpu_id);
310 v3_unlock(apic->lock);
314 v3_unlock(apic->lock);
319 // irq_num is the bit offset into a 256 bit buffer...
320 static int activate_apic_irq(struct apic_state * apic, uint32_t irq_num) {
321 int major_offset = (irq_num & ~0x00000007) >> 3;
322 int minor_offset = irq_num & 0x00000007;
323 uint8_t * req_location = apic->int_req_reg + major_offset;
324 uint8_t * en_location = apic->int_en_reg + major_offset;
325 uint8_t flag = 0x1 << minor_offset;
330 // PrintError("apic %u: core ?: Attempting to raise an invalid interrupt: %d\n", apic->lapic_id.val,irq_num);
335 PrintDebug("apic %u: core ?: Raising APIC IRQ %d\n", apic->lapic_id.val, irq_num);
337 if (*req_location & flag) {
338 //V3_Print("Interrupts coallescing\n");
341 if (*en_location & flag) {
342 *req_location |= flag;
344 PrintDebug("apic %u: core ?: Interrupt not enabled... %.2x\n",
345 apic->lapic_id.val, *en_location);
354 static int get_highest_isr(struct apic_state * apic) {
357 // We iterate backwards to find the highest priority
358 for (i = 31; i >= 0; i--) {
359 uint8_t * svc_major = apic->int_svc_reg + i;
361 if ((*svc_major) & 0xff) {
362 for (j = 7; j >= 0; j--) {
363 uint8_t flag = 0x1 << j;
364 if ((*svc_major) & flag) {
365 return ((i * 8) + j);
376 static int get_highest_irr(struct apic_state * apic) {
379 // We iterate backwards to find the highest priority
380 for (i = 31; i >= 0; i--) {
381 uint8_t * req_major = apic->int_req_reg + i;
383 if ((*req_major) & 0xff) {
384 for (j = 7; j >= 0; j--) {
385 uint8_t flag = 0x1 << j;
386 if ((*req_major) & flag) {
387 return ((i * 8) + j);
399 static int apic_do_eoi(struct apic_state * apic) {
400 int isr_irq = get_highest_isr(apic);
403 int major_offset = (isr_irq & ~0x00000007) >> 3;
404 int minor_offset = isr_irq & 0x00000007;
405 uint8_t flag = 0x1 << minor_offset;
406 uint8_t * svc_location = apic->int_svc_reg + major_offset;
408 PrintDebug("apic %u: core ?: Received APIC EOI for IRQ %d\n", apic->lapic_id.val,isr_irq);
410 *svc_location &= ~flag;
412 #ifdef CONFIG_CRAY_XT
414 if ((isr_irq == 238) ||
416 PrintDebug("apic %u: core ?: Acking IRQ %d\n", apic->lapic_id.val,isr_irq);
419 if (isr_irq == 238) {
424 //PrintError("apic %u: core ?: Spurious EOI...\n",apic->lapic_id.val);
431 static int activate_internal_irq(struct apic_state * apic, apic_irq_type_t int_type) {
432 uint32_t vec_num = 0;
433 uint32_t del_mode = 0;
439 vec_num = apic->tmr_vec_tbl.vec;
440 del_mode = APIC_FIXED_DELIVERY;
441 masked = apic->tmr_vec_tbl.mask;
444 vec_num = apic->therm_loc_vec_tbl.vec;
445 del_mode = apic->therm_loc_vec_tbl.msg_type;
446 masked = apic->therm_loc_vec_tbl.mask;
449 vec_num = apic->perf_ctr_loc_vec_tbl.vec;
450 del_mode = apic->perf_ctr_loc_vec_tbl.msg_type;
451 masked = apic->perf_ctr_loc_vec_tbl.mask;
454 vec_num = apic->lint0_vec_tbl.vec;
455 del_mode = apic->lint0_vec_tbl.msg_type;
456 masked = apic->lint0_vec_tbl.mask;
459 vec_num = apic->lint1_vec_tbl.vec;
460 del_mode = apic->lint1_vec_tbl.msg_type;
461 masked = apic->lint1_vec_tbl.mask;
464 vec_num = apic->err_vec_tbl.vec;
465 del_mode = APIC_FIXED_DELIVERY;
466 masked = apic->err_vec_tbl.mask;
469 PrintError("apic %u: core ?: Invalid APIC interrupt type\n", apic->lapic_id.val);
473 // interrupt is masked, don't send
475 PrintDebug("apic %u: core ?: Inerrupt is masked\n", apic->lapic_id.val);
479 if (del_mode == APIC_FIXED_DELIVERY) {
480 //PrintDebug("Activating internal APIC IRQ %d\n", vec_num);
481 return activate_apic_irq(apic, vec_num);
483 PrintError("apic %u: core ?: Unhandled Delivery Mode\n", apic->lapic_id.val);
490 static inline int should_deliver_cluster_ipi(struct guest_info * dst_core,
491 struct apic_state * dst_apic, uint8_t mda) {
493 if ( ((mda & 0xf0) == (dst_apic->log_dst.dst_log_id & 0xf0)) && // (I am in the cluster and
494 ((mda & 0x0f) & (dst_apic->log_dst.dst_log_id & 0x0f)) ) { // I am in the set)
496 PrintDebug("apic %u core %u: accepting clustered IRQ (mda 0x%x == log_dst 0x%x)\n",
497 dst_apic->lapic_id.val, dst_core->cpu_id, mda,
498 dst_apic->log_dst.dst_log_id);
502 PrintDebug("apic %u core %u: rejecting clustered IRQ (mda 0x%x != log_dst 0x%x)\n",
503 dst_apic->lapic_id.val, dst_core->cpu_id, mda, dst_
504 dst_apic->log_dst.dst_log_id);
509 static inline int should_deliver_flat_ipi(struct guest_info * dst_core,
510 struct apic_state * dst_apic, uint8_t mda) {
512 if (dst_apic->log_dst.dst_log_id & mda) { // I am in the set
514 PrintDebug("apic %u core %u: accepting flat IRQ (mda 0x%x == log_dst 0x%x)\n",
515 dst_apic->lapic_id.val, dst_core->cpu_id, mda,
516 dst_apic->log_dst.dst_log_id);
519 PrintDebug("apic %u core %u: rejecting flat IRQ (mda 0x%x != log_dst 0x%x)\n",
520 dst_apic->lapic_id.val, dst_core->cpu_id, mda,
521 dst_apic->log_dst.dst_log_id);
528 static int should_deliver_ipi(struct guest_info * dst_core,
529 struct apic_state * dst_apic, uint8_t mda) {
532 // always deliver broadcast
536 if (dst_apic->dst_fmt.model == 0xf) {
537 return should_deliver_cluster_ipi(dst_core, dst_apic, mda);
538 } else if (dst_apic->dst_fmt.model == 0x0) {
539 return should_deliver_flat_ipi(dst_core, dst_apic, mda);
541 PrintError("apic %u core %u: invalid destination format register value 0x%x for logical mode delivery.\n",
542 dst_apic->lapic_id.val, dst_core->cpu_id, dst_apic->dst_fmt.model);
548 static int deliver_ipi(struct guest_info * core,
549 struct apic_state * src_apic,
550 struct apic_state * dst_apic,
551 uint32_t vector, uint8_t del_mode) {
553 struct guest_info * dst_core = dst_apic->core;
558 case 1: // lowest priority
559 PrintDebug(" delivering IRQ to core %u\n", dst_core->cpu_id);
561 activate_apic_irq(dst_apic, vector);
563 if (dst_apic != src_apic) {
564 // Assume core # is same as logical processor for now
565 // TODO FIX THIS FIX THIS
566 // THERE SHOULD BE: guestapicid->virtualapicid map,
567 // cpu_id->logical processor map
568 // host maitains logical proc->phsysical proc
569 PrintDebug(" non-local core, forcing it to exit\n");
571 v3_interrupt_cpu(core->vm_info, dst_core->cpu_id, 0);
577 PrintDebug(" INIT delivery to core %u\n", dst_core->cpu_id);
579 // TODO: any APIC reset on dest core (shouldn't be needed, but not sure...)
582 if (dst_apic->ipi_state != INIT) {
583 PrintError(" Warning: core %u is not in INIT state (mode = %d), ignored\n",
584 dst_core->cpu_id, dst_core->cpu_mode);
585 // Only a warning, since INIT INIT SIPI is common
589 // We transition the target core to SIPI state
590 dst_apic->ipi_state = SIPI; // note: locking should not be needed here
592 // That should be it since the target core should be
593 // waiting in host on this transition
594 // either it's on another core or on a different preemptive thread
595 // in both cases, it will quickly notice this transition
596 // in particular, we should not need to force an exit here
598 PrintDebug(" INIT delivery done\n");
605 if (dst_apic->ipi_state != SIPI) {
606 PrintError(" core %u is not in SIPI state (mode = %d), ignored!\n",
607 dst_core->cpu_id, dst_core->cpu_mode);
611 // Write the RIP, CS, and descriptor
612 // assume the rest is already good to go
614 // vector VV -> rip at 0
616 // This means we start executing at linear address VV000
618 // So the selector needs to be VV00
619 // and the base needs to be VV000
622 dst_core->segments.cs.selector = vector << 8;
623 dst_core->segments.cs.limit = 0xffff;
624 dst_core->segments.cs.base = vector << 12;
626 PrintDebug(" SIPI delivery (0x%x -> 0x%x:0x0) to core %u\n",
627 vec, dst_core->segments.cs.selector, dst_core->cpu_id);
628 // Maybe need to adjust the APIC?
630 // We transition the target core to SIPI state
631 dst_core->core_run_state = CORE_RUNNING; // note: locking should not be needed here
632 dst_apic->ipi_state = STARTED;
634 // As with INIT, we should not need to do anything else
636 PrintDebug(" SIPI delivery done\n");
645 PrintError("IPI %d delivery is unsupported\n", del_mode);
654 static int route_ipi(struct guest_info * core, struct apic_dev_state * apic_dev,
655 struct apic_state * src_apic, uint32_t icr_val) {
656 struct int_cmd_reg * icr = (struct int_cmd_reg *)&icr_val;
657 struct apic_state * dest_apic = NULL;
659 PrintDebug("icc_bus: icc_bus=%p, src_apic=%u, icr_data=%llx, extirq=%u\n",
660 icc_bus, src_apic, icr_data, extirq);
663 // initial sanity checks
664 if (src_apic == NULL) {
665 PrintError("icc_bus: Apparently sending from unregistered apic id=%d\n",
666 src_apic->core->cpu_id);
671 if ((icr->dst_mode == 0) && (icr->dst >= apic_dev->num_apics)) {
672 PrintError("icc_bus: Attempted send to unregistered apic id=%u\n",
677 dest_apic = &(apic_dev->apics[icr->dst]);
680 PrintDebug("icc_bus: IPI %s %u from %s %u to %s %s %u (icr=0x%llx, extirq=%u)\n",
681 deliverymode_str[icr->del_mode],
683 (src_apic == state->ioapic_id) ? "ioapic" : "apic",
685 (icr->dst_mode == 0) ? "(physical)" : "(logical)",
686 shorthand_str[icr->dst_shorthand],
692 switch (icr->dst_shorthand) {
694 case 0: // no shorthand
695 if (icr->dst_mode == 0) {
698 if (deliver_ipi(core, src_apic, dest_apic,
699 icr->vec, icr->del_mode) == -1) {
700 PrintError("Error: Could not deliver IPI\n");
707 uint8_t mda = icr->dst;
709 for (i = 0; i < apic_dev->num_apics; i++) {
710 dest_apic = &(apic_dev->apics[i]);
711 int del_flag = should_deliver_ipi(dest_apic->core, dest_apic, mda);
713 if (del_flag == -1) {
714 PrintError("Error checking delivery mode\n");
716 } else if (del_flag == 1) {
717 if (deliver_ipi(core, src_apic, dest_apic,
718 icr->vec, icr->del_mode) == -1) {
719 PrintError("Error: Could not deliver IPI\n");
730 if (icr->dst_mode == 0) {
731 if (deliver_ipi(core, src_apic, src_apic, icr->vec, icr->del_mode) == -1) {
732 PrintError("Could not deliver IPI\n");
737 PrintError("icc_bus: use of logical delivery in self is not yet supported.\n");
743 case 3: { // all and all-but-me
744 // assuming that logical verus physical doesn't matter
745 // although it is odd that both are used
748 for (i = 0; i < apic_dev->num_apics; i++) {
749 dest_apic = &(apic_dev->apics[i]);
751 if ((dest_apic != src_apic) || (icr->dst_shorthand == 2)) {
752 if (deliver_ipi(core, src_apic, dest_apic, icr->vec, icr->del_mode) == -1) {
753 PrintError("Error: Could not deliver IPI\n");
762 PrintError("Error routing IPI, invalid Mode (%d)\n", icr->dst_shorthand);
772 static int apic_read(struct guest_info * core, addr_t guest_addr, void * dst, uint_t length, void * priv_data) {
773 struct apic_dev_state * apic_dev = (struct apic_dev_state *)(priv_data);
774 struct apic_state * apic = &(apic_dev->apics[core->cpu_id]);
775 addr_t reg_addr = guest_addr - apic->base_addr;
776 struct apic_msr * msr = (struct apic_msr *)&(apic->base_addr_msr.value);
780 PrintDebug("apic %u: core %u: at %p: Read apic address space (%p)\n",
781 apic->lapic_id.val, core->cpu_id, apic, (void *)guest_addr);
783 if (msr->apic_enable == 0) {
784 PrintError("apic %u: core %u: Read from APIC address space with disabled APIC, apic msr=0x%llx\n",
785 apic->lapic_id.val, core->cpu_id, apic->base_addr_msr.value);
791 /* Because "May not be supported" doesn't matter to Linux developers... */
792 /* if (length != 4) { */
793 /* PrintError("Invalid apic read length (%d)\n", length); */
797 switch (reg_addr & ~0x3) {
799 // Well, only an idiot would read from a architectural write only register
801 // PrintError("Attempting to read from write only register\n");
807 val = apic->lapic_id.val;
809 case APIC_VERSION_OFFSET:
810 val = apic->apic_ver.val;
813 val = apic->task_prio.val;
816 val = apic->arb_prio.val;
819 val = apic->proc_prio.val;
821 case REMOTE_READ_OFFSET:
822 val = apic->rem_rd_data;
825 val = apic->log_dst.val;
828 val = apic->dst_fmt.val;
830 case SPURIOUS_INT_VEC_OFFSET:
831 val = apic->spurious_int.val;
834 val = apic->err_status.val;
836 case TMR_LOC_VEC_TBL_OFFSET:
837 val = apic->tmr_vec_tbl.val;
839 case LINT0_VEC_TBL_OFFSET:
840 val = apic->lint0_vec_tbl.val;
842 case LINT1_VEC_TBL_OFFSET:
843 val = apic->lint1_vec_tbl.val;
845 case ERR_VEC_TBL_OFFSET:
846 val = apic->err_vec_tbl.val;
848 case TMR_INIT_CNT_OFFSET:
849 val = apic->tmr_init_cnt;
851 case TMR_DIV_CFG_OFFSET:
852 val = apic->tmr_div_cfg.val;
856 val = *(uint32_t *)(apic->int_en_reg);
859 val = *(uint32_t *)(apic->int_en_reg + 4);
862 val = *(uint32_t *)(apic->int_en_reg + 8);
865 val = *(uint32_t *)(apic->int_en_reg + 12);
868 val = *(uint32_t *)(apic->int_en_reg + 16);
871 val = *(uint32_t *)(apic->int_en_reg + 20);
874 val = *(uint32_t *)(apic->int_en_reg + 24);
877 val = *(uint32_t *)(apic->int_en_reg + 28);
881 val = *(uint32_t *)(apic->int_svc_reg);
884 val = *(uint32_t *)(apic->int_svc_reg + 4);
887 val = *(uint32_t *)(apic->int_svc_reg + 8);
890 val = *(uint32_t *)(apic->int_svc_reg + 12);
893 val = *(uint32_t *)(apic->int_svc_reg + 16);
896 val = *(uint32_t *)(apic->int_svc_reg + 20);
899 val = *(uint32_t *)(apic->int_svc_reg + 24);
902 val = *(uint32_t *)(apic->int_svc_reg + 28);
906 val = *(uint32_t *)(apic->trig_mode_reg);
909 val = *(uint32_t *)(apic->trig_mode_reg + 4);
912 val = *(uint32_t *)(apic->trig_mode_reg + 8);
915 val = *(uint32_t *)(apic->trig_mode_reg + 12);
918 val = *(uint32_t *)(apic->trig_mode_reg + 16);
921 val = *(uint32_t *)(apic->trig_mode_reg + 20);
924 val = *(uint32_t *)(apic->trig_mode_reg + 24);
927 val = *(uint32_t *)(apic->trig_mode_reg + 28);
931 val = *(uint32_t *)(apic->int_req_reg);
934 val = *(uint32_t *)(apic->int_req_reg + 4);
937 val = *(uint32_t *)(apic->int_req_reg + 8);
940 val = *(uint32_t *)(apic->int_req_reg + 12);
943 val = *(uint32_t *)(apic->int_req_reg + 16);
946 val = *(uint32_t *)(apic->int_req_reg + 20);
949 val = *(uint32_t *)(apic->int_req_reg + 24);
952 val = *(uint32_t *)(apic->int_req_reg + 28);
954 case TMR_CUR_CNT_OFFSET:
955 val = apic->tmr_cur_cnt;
958 // We are not going to implement these....
959 case THERM_LOC_VEC_TBL_OFFSET:
960 val = apic->therm_loc_vec_tbl.val;
962 case PERF_CTR_LOC_VEC_TBL_OFFSET:
963 val = apic->perf_ctr_loc_vec_tbl.val;
969 case INT_CMD_LO_OFFSET:
970 val = apic->int_cmd.lo;
972 case INT_CMD_HI_OFFSET:
973 val = apic->int_cmd.hi;
976 // handle current timer count
978 // Unhandled Registers
979 case EXT_INT_LOC_VEC_TBL_OFFSET0:
980 val = apic->ext_intr_vec_tbl[0].val;
982 case EXT_INT_LOC_VEC_TBL_OFFSET1:
983 val = apic->ext_intr_vec_tbl[1].val;
985 case EXT_INT_LOC_VEC_TBL_OFFSET2:
986 val = apic->ext_intr_vec_tbl[2].val;
988 case EXT_INT_LOC_VEC_TBL_OFFSET3:
989 val = apic->ext_intr_vec_tbl[3].val;
993 case EXT_APIC_FEATURE_OFFSET:
994 case EXT_APIC_CMD_OFFSET:
998 PrintError("apic %u: core %u: Read from Unhandled APIC Register: %x (getting zero)\n",
999 apic->lapic_id.val, core->cpu_id, (uint32_t)reg_addr);
1005 uint_t byte_addr = reg_addr & 0x3;
1006 uint8_t * val_ptr = (uint8_t *)dst;
1008 *val_ptr = *(((uint8_t *)&val) + byte_addr);
1010 } else if ((length == 2) &&
1011 ((reg_addr & 0x3) == 0x3)) {
1012 uint_t byte_addr = reg_addr & 0x3;
1013 uint16_t * val_ptr = (uint16_t *)dst;
1014 *val_ptr = *(((uint16_t *)&val) + byte_addr);
1016 } else if (length == 4) {
1017 uint32_t * val_ptr = (uint32_t *)dst;
1021 PrintError("apic %u: core %u: Invalid apic read length (%d)\n",
1022 apic->lapic_id.val, core->cpu_id, length);
1026 PrintDebug("apic %u: core %u: Read finished (val=%x)\n",
1027 apic->lapic_id.val, core->cpu_id, *(uint32_t *)dst);
1036 static int apic_write(struct guest_info * core, addr_t guest_addr, void * src, uint_t length, void * priv_data) {
1037 struct apic_dev_state * apic_dev = (struct apic_dev_state *)(priv_data);
1038 struct apic_state * apic = &(apic_dev->apics[core->cpu_id]);
1039 addr_t reg_addr = guest_addr - apic->base_addr;
1040 struct apic_msr * msr = (struct apic_msr *)&(apic->base_addr_msr.value);
1041 uint32_t op_val = *(uint32_t *)src;
1043 PrintDebug("apic %u: core %u: at %p and priv_data is at %p\n",
1044 apic->lapic_id.val, core->cpu_id, apic, priv_data);
1046 PrintDebug("Write to address space (%p) (val=%x)\n",
1047 (void *)guest_addr, *(uint32_t *)src);
1049 if (msr->apic_enable == 0) {
1050 PrintError("apic %u: core %u: Write to APIC address space with disabled APIC, apic msr=0x%llx\n",
1051 apic->lapic_id.val, core->cpu_id, apic->base_addr_msr.value);
1057 PrintError("apic %u: core %u: Invalid apic write length (%d)\n",
1058 apic->lapic_id.val, length, core->cpu_id);
1063 case REMOTE_READ_OFFSET:
1064 case APIC_VERSION_OFFSET:
1091 case EXT_APIC_FEATURE_OFFSET:
1093 PrintError("apic %u: core %u: Attempting to write to read only register %p (error)\n",
1094 apic->lapic_id.val, core->cpu_id, (void *)reg_addr);
1100 case APIC_ID_OFFSET:
1101 PrintDebug("apic %u: core %u: my id is being changed to %u\n",
1102 apic->lapic_id.val, core->cpu_id, op_val);
1104 apic->lapic_id.val = op_val;
1107 apic->task_prio.val = op_val;
1110 PrintDebug("apic %u: core %u: setting log_dst.val to 0x%x\n",
1111 apic->lapic_id.val, core->cpu_id, op_val);
1112 apic->log_dst.val = op_val;
1115 apic->dst_fmt.val = op_val;
1117 case SPURIOUS_INT_VEC_OFFSET:
1118 apic->spurious_int.val = op_val;
1121 apic->err_status.val = op_val;
1123 case TMR_LOC_VEC_TBL_OFFSET:
1124 apic->tmr_vec_tbl.val = op_val;
1126 case THERM_LOC_VEC_TBL_OFFSET:
1127 apic->therm_loc_vec_tbl.val = op_val;
1129 case PERF_CTR_LOC_VEC_TBL_OFFSET:
1130 apic->perf_ctr_loc_vec_tbl.val = op_val;
1132 case LINT0_VEC_TBL_OFFSET:
1133 apic->lint0_vec_tbl.val = op_val;
1135 case LINT1_VEC_TBL_OFFSET:
1136 apic->lint1_vec_tbl.val = op_val;
1138 case ERR_VEC_TBL_OFFSET:
1139 apic->err_vec_tbl.val = op_val;
1141 case TMR_INIT_CNT_OFFSET:
1142 apic->tmr_init_cnt = op_val;
1143 apic->tmr_cur_cnt = op_val;
1145 case TMR_CUR_CNT_OFFSET:
1146 apic->tmr_cur_cnt = op_val;
1148 case TMR_DIV_CFG_OFFSET:
1149 apic->tmr_div_cfg.val = op_val;
1153 // Enable mask (256 bits)
1155 *(uint32_t *)(apic->int_en_reg) = op_val;
1158 *(uint32_t *)(apic->int_en_reg + 4) = op_val;
1161 *(uint32_t *)(apic->int_en_reg + 8) = op_val;
1164 *(uint32_t *)(apic->int_en_reg + 12) = op_val;
1167 *(uint32_t *)(apic->int_en_reg + 16) = op_val;
1170 *(uint32_t *)(apic->int_en_reg + 20) = op_val;
1173 *(uint32_t *)(apic->int_en_reg + 24) = op_val;
1176 *(uint32_t *)(apic->int_en_reg + 28) = op_val;
1179 case EXT_INT_LOC_VEC_TBL_OFFSET0:
1180 apic->ext_intr_vec_tbl[0].val = op_val;
1182 case EXT_INT_LOC_VEC_TBL_OFFSET1:
1183 apic->ext_intr_vec_tbl[1].val = op_val;
1185 case EXT_INT_LOC_VEC_TBL_OFFSET2:
1186 apic->ext_intr_vec_tbl[2].val = op_val;
1188 case EXT_INT_LOC_VEC_TBL_OFFSET3:
1189 apic->ext_intr_vec_tbl[3].val = op_val;
1199 case INT_CMD_LO_OFFSET:
1200 apic->int_cmd.lo = op_val;
1202 PrintDebug("apic %u: core %u: sending cmd 0x%llx to apic %u\n",
1203 apic->lapic_id.val, core->cpu_id,
1204 apic->int_cmd.val, apic->int_cmd.dst);
1206 if (route_ipi(core, apic_dev, apic, apic->int_cmd.val) == -1) {
1207 PrintError("IPI Routing failure\n");
1213 case INT_CMD_HI_OFFSET:
1214 apic->int_cmd.hi = op_val;
1218 // Unhandled Registers
1219 case EXT_APIC_CMD_OFFSET:
1222 PrintError("apic %u: core %u: Write to Unhandled APIC Register: %x (ignored)\n",
1223 apic->lapic_id.val, core->cpu_id, (uint32_t)reg_addr);
1228 PrintDebug("apic %u: core %u: Write finished\n", apic->lapic_id.val, core->cpu_id);
1235 /* Interrupt Controller Functions */
1237 // returns 1 if an interrupt is pending, 0 otherwise
1238 static int apic_intr_pending(struct guest_info * core, void * private_data) {
1239 struct apic_dev_state * apic_dev = (struct apic_dev_state *)(private_data);
1240 struct apic_state * apic = &(apic_dev->apics[core->cpu_id]);
1241 int req_irq = get_highest_irr(apic);
1242 int svc_irq = get_highest_isr(apic);
1244 // PrintDebug("apic %u: core %u: req_irq=%d, svc_irq=%d\n",apic->lapic_id.val,info->cpu_id,req_irq,svc_irq);
1246 if ((req_irq >= 0) &&
1247 (req_irq > svc_irq)) {
1254 static int apic_get_intr_number(struct guest_info * core, void * private_data) {
1255 struct apic_dev_state * apic_dev = (struct apic_dev_state *)(private_data);
1256 struct apic_state * apic = &(apic_dev->apics[core->cpu_id]);
1257 int req_irq = get_highest_irr(apic);
1258 int svc_irq = get_highest_isr(apic);
1260 if (svc_irq == -1) {
1262 } else if (svc_irq < req_irq) {
1270 int v3_apic_raise_intr(struct v3_vm_info * vm, struct vm_device * dev,
1271 uint32_t irq, uint32_t dst) {
1272 struct apic_dev_state * apic_dev = (struct apic_dev_state *)(dev->private_data);
1273 struct apic_state * apic = &(apic_dev->apics[dst]);
1275 activate_apic_irq(apic, irq);
1277 if (V3_Get_CPU() != dst) {
1278 v3_interrupt_cpu(vm, dst, 0);
1286 static int apic_begin_irq(struct guest_info * core, void * private_data, int irq) {
1287 struct apic_dev_state * apic_dev = (struct apic_dev_state *)(private_data);
1288 struct apic_state * apic = &(apic_dev->apics[core->cpu_id]);
1289 int major_offset = (irq & ~0x00000007) >> 3;
1290 int minor_offset = irq & 0x00000007;
1291 uint8_t * req_location = apic->int_req_reg + major_offset;
1292 uint8_t * svc_location = apic->int_svc_reg + major_offset;
1293 uint8_t flag = 0x01 << minor_offset;
1295 if (*req_location & flag) {
1296 // we will only pay attention to a begin irq if we
1297 // know that we initiated it!
1298 *svc_location |= flag;
1299 *req_location &= ~flag;
1302 PrintDebug("apic %u: core %u: begin irq for %d ignored since I don't own it\n",
1303 apic->lapic_id.val, info->cpu_id, irq);
1312 /* Timer Functions */
1313 static void apic_update_time(struct guest_info * core,
1314 uint64_t cpu_cycles, uint64_t cpu_freq,
1316 struct apic_dev_state * apic_dev = (struct apic_dev_state *)(priv_data);
1317 struct apic_state * apic = &(apic_dev->apics[core->cpu_id]);
1319 // The 32 bit GCC runtime is a pile of shit
1321 uint64_t tmr_ticks = 0;
1323 uint32_t tmr_ticks = 0;
1326 uint8_t tmr_div = *(uint8_t *)&(apic->tmr_div_cfg.val);
1327 uint_t shift_num = 0;
1330 // Check whether this is true:
1331 // -> If the Init count is zero then the timer is disabled
1332 // and doesn't just blitz interrupts to the CPU
1333 if ((apic->tmr_init_cnt == 0) ||
1334 ( (apic->tmr_vec_tbl.tmr_mode == APIC_TMR_ONESHOT) &&
1335 (apic->tmr_cur_cnt == 0))) {
1336 //PrintDebug("apic %u: core %u: APIC timer not yet initialized\n",apic->lapic_id.val,info->cpu_id);
1354 case APIC_TMR_DIV16:
1357 case APIC_TMR_DIV32:
1360 case APIC_TMR_DIV64:
1363 case APIC_TMR_DIV128:
1367 PrintError("apic %u: core %u: Invalid Timer Divider configuration\n",
1368 apic->lapic_id.val, core->cpu_id);
1372 tmr_ticks = cpu_cycles >> shift_num;
1373 // PrintDebug("Timer Ticks: %p\n", (void *)tmr_ticks);
1375 if (tmr_ticks < apic->tmr_cur_cnt) {
1376 apic->tmr_cur_cnt -= tmr_ticks;
1378 tmr_ticks -= apic->tmr_cur_cnt;
1379 apic->tmr_cur_cnt = 0;
1382 PrintDebug("apic %u: core %u: Raising APIC Timer interrupt (periodic=%d) (icnt=%d) (div=%d)\n",
1383 apic->lapic_id.val, info->cpu_id,
1384 apic->tmr_vec_tbl.tmr_mode, apic->tmr_init_cnt, shift_num);
1386 if (apic_intr_pending(core, priv_data)) {
1387 PrintDebug("apic %u: core %u: Overriding pending IRQ %d\n",
1388 apic->lapic_id.val, info->cpu_id,
1389 apic_get_intr_number(info, priv_data));
1392 if (activate_internal_irq(apic, APIC_TMR_INT) == -1) {
1393 PrintError("apic %u: core %u: Could not raise Timer interrupt\n",
1394 apic->lapic_id.val, core->cpu_id);
1397 if (apic->tmr_vec_tbl.tmr_mode == APIC_TMR_PERIODIC) {
1398 tmr_ticks = tmr_ticks % apic->tmr_init_cnt;
1399 apic->tmr_cur_cnt = apic->tmr_init_cnt - tmr_ticks;
1407 static struct intr_ctrl_ops intr_ops = {
1408 .intr_pending = apic_intr_pending,
1409 .get_intr_number = apic_get_intr_number,
1410 .begin_irq = apic_begin_irq,
1414 static struct vm_timer_ops timer_ops = {
1415 .update_timer = apic_update_time,
1421 static int apic_free(struct vm_device * dev) {
1423 /* TODO: This should crosscall to force an unhook on each CPU */
1425 // struct apic_state * apic = (struct apic_state *)dev->private_data;
1427 v3_unhook_msr(dev->vm, BASE_ADDR_MSR);
1433 static struct v3_device_ops dev_ops = {
1444 static int apic_init(struct v3_vm_info * vm, v3_cfg_tree_t * cfg) {
1445 char * dev_id = v3_cfg_val(cfg, "ID");
1446 struct apic_dev_state * apic_dev = NULL;
1449 PrintDebug("apic: creating an APIC for each core\n");
1451 apic_dev = (struct apic_dev_state *)V3_Malloc(sizeof(struct apic_dev_state) +
1452 sizeof(struct apic_state) * vm->num_cores);
1454 apic_dev->num_apics = vm->num_cores;
1456 struct vm_device * dev = v3_allocate_device(dev_id, &dev_ops, apic_dev);
1458 if (v3_attach_device(vm, dev) == -1) {
1459 PrintError("apic: Could not attach device %s\n", dev_id);
1464 for (i = 0; i < vm->num_cores; i++) {
1465 struct apic_state * apic = &(apic_dev->apics[i]);
1466 struct guest_info * core = &(vm->cores[i]);
1470 init_apic_state(apic, i);
1472 v3_register_intr_controller(core, &intr_ops, apic_dev);
1474 v3_add_timer(core, &timer_ops, apic_dev);
1476 v3_hook_full_mem(vm, core->cpu_id, apic->base_addr, apic->base_addr + PAGE_SIZE_4KB, apic_read, apic_write, apic_dev);
1478 PrintDebug("apic %u: (setup device): done, my id is %u\n", i, apic->lapic_id.val);
1481 #ifdef CONFIG_DEBUG_APIC
1482 for (i = 0; i < vm->num_cores; i++) {
1483 struct apic_state * apic = &(apic_dev->apics[i]);
1484 PrintDebug("apic: sanity check: apic %u (at %p) has id %u and msr value %llx\n",
1485 i, apic, apic->lapic_id.val, apic->base_addr_msr.value);
1490 PrintDebug("apic: priv_data is at %p\n", apic_dev);
1492 v3_hook_msr(vm, BASE_ADDR_MSR, read_apic_msr, write_apic_msr, apic_dev);
1499 device_register("LAPIC", apic_init)