2 * This file is part of the Palacios Virtual Machine Monitor developed
3 * by the V3VEE Project with funding from the United States National
4 * Science Foundation and the Department of Energy.
6 * The V3VEE Project is a joint project between Northwestern University
7 * and the University of New Mexico. You can find out more at
10 * Copyright (c) 2008, Jack Lange <jarusl@cs.northwestern.edu>
11 * Copyright (c) 2008, The V3VEE Project <http://www.v3vee.org>
12 * All rights reserved.
14 * Author: Jack Lange <jarusl@cs.northwestern.edu>
16 * This is free software. You are permitted to use,
17 * redistribute, and modify it as specified in the file "V3VEE_LICENSE".
21 #include <devices/apic.h>
22 #include <devices/apic_regs.h>
23 #include <devices/icc_bus.h>
24 #include <palacios/vmm.h>
25 #include <palacios/vmm_msr.h>
26 #include <palacios/vmm_sprintf.h>
27 #include <palacios/vm_guest.h>
30 #ifndef CONFIG_DEBUG_APIC
32 #define PrintDebug(fmt, args...)
36 typedef enum { APIC_TMR_INT, APIC_THERM_INT, APIC_PERF_INT,
37 APIC_LINT0_INT, APIC_LINT1_INT, APIC_ERR_INT } apic_irq_type_t;
39 #define APIC_FIXED_DELIVERY 0x0
40 #define APIC_SMI_DELIVERY 0x2
41 #define APIC_NMI_DELIVERY 0x4
42 #define APIC_INIT_DELIVERY 0x5
43 #define APIC_EXTINT_DELIVERY 0x7
46 #define BASE_ADDR_MSR 0x0000001B
47 #define DEFAULT_BASE_ADDR 0xfee00000
49 #define APIC_ID_OFFSET 0x020
50 #define APIC_VERSION_OFFSET 0x030
51 #define TPR_OFFSET 0x080
52 #define APR_OFFSET 0x090
53 #define PPR_OFFSET 0x0a0
54 #define EOI_OFFSET 0x0b0
55 #define REMOTE_READ_OFFSET 0x0c0
56 #define LDR_OFFSET 0x0d0
57 #define DFR_OFFSET 0x0e0
58 #define SPURIOUS_INT_VEC_OFFSET 0x0f0
60 #define ISR_OFFSET0 0x100 // 0x100 - 0x170
61 #define ISR_OFFSET1 0x110 // 0x100 - 0x170
62 #define ISR_OFFSET2 0x120 // 0x100 - 0x170
63 #define ISR_OFFSET3 0x130 // 0x100 - 0x170
64 #define ISR_OFFSET4 0x140 // 0x100 - 0x170
65 #define ISR_OFFSET5 0x150 // 0x100 - 0x170
66 #define ISR_OFFSET6 0x160 // 0x100 - 0x170
67 #define ISR_OFFSET7 0x170 // 0x100 - 0x170
69 #define TRIG_OFFSET0 0x180 // 0x180 - 0x1f0
70 #define TRIG_OFFSET1 0x190 // 0x180 - 0x1f0
71 #define TRIG_OFFSET2 0x1a0 // 0x180 - 0x1f0
72 #define TRIG_OFFSET3 0x1b0 // 0x180 - 0x1f0
73 #define TRIG_OFFSET4 0x1c0 // 0x180 - 0x1f0
74 #define TRIG_OFFSET5 0x1d0 // 0x180 - 0x1f0
75 #define TRIG_OFFSET6 0x1e0 // 0x180 - 0x1f0
76 #define TRIG_OFFSET7 0x1f0 // 0x180 - 0x1f0
79 #define IRR_OFFSET0 0x200 // 0x200 - 0x270
80 #define IRR_OFFSET1 0x210 // 0x200 - 0x270
81 #define IRR_OFFSET2 0x220 // 0x200 - 0x270
82 #define IRR_OFFSET3 0x230 // 0x200 - 0x270
83 #define IRR_OFFSET4 0x240 // 0x200 - 0x270
84 #define IRR_OFFSET5 0x250 // 0x200 - 0x270
85 #define IRR_OFFSET6 0x260 // 0x200 - 0x270
86 #define IRR_OFFSET7 0x270 // 0x200 - 0x270
89 #define ESR_OFFSET 0x280
90 #define INT_CMD_LO_OFFSET 0x300
91 #define INT_CMD_HI_OFFSET 0x310
92 #define TMR_LOC_VEC_TBL_OFFSET 0x320
93 #define THERM_LOC_VEC_TBL_OFFSET 0x330
94 #define PERF_CTR_LOC_VEC_TBL_OFFSET 0x340
95 #define LINT0_VEC_TBL_OFFSET 0x350
96 #define LINT1_VEC_TBL_OFFSET 0x360
97 #define ERR_VEC_TBL_OFFSET 0x370
98 #define TMR_INIT_CNT_OFFSET 0x380
99 #define TMR_CUR_CNT_OFFSET 0x390
100 #define TMR_DIV_CFG_OFFSET 0x3e0
101 #define EXT_APIC_FEATURE_OFFSET 0x400
102 #define EXT_APIC_CMD_OFFSET 0x410
103 #define SEOI_OFFSET 0x420
105 #define IER_OFFSET0 0x480 // 0x480 - 0x4f0
106 #define IER_OFFSET1 0x490 // 0x480 - 0x4f0
107 #define IER_OFFSET2 0x4a0 // 0x480 - 0x4f0
108 #define IER_OFFSET3 0x4b0 // 0x480 - 0x4f0
109 #define IER_OFFSET4 0x4c0 // 0x480 - 0x4f0
110 #define IER_OFFSET5 0x4d0 // 0x480 - 0x4f0
111 #define IER_OFFSET6 0x4e0 // 0x480 - 0x4f0
112 #define IER_OFFSET7 0x4f0 // 0x480 - 0x4f0
114 #define EXT_INT_LOC_VEC_TBL_OFFSET0 0x500 // 0x500 - 0x530
115 #define EXT_INT_LOC_VEC_TBL_OFFSET1 0x510 // 0x500 - 0x530
116 #define EXT_INT_LOC_VEC_TBL_OFFSET2 0x520 // 0x500 - 0x530
117 #define EXT_INT_LOC_VEC_TBL_OFFSET3 0x530 // 0x500 - 0x530
128 uint_t bootstrap_cpu : 1;
130 uint_t apic_enable : 1;
131 ullong_t base_addr : 40;
133 } __attribute__((packed));
134 } __attribute__((packed));
135 } __attribute__((packed));
142 struct apic_msr base_addr_msr;
145 /* memory map registers */
147 struct lapic_id_reg lapic_id;
148 struct apic_ver_reg apic_ver;
149 struct ext_apic_ctrl_reg ext_apic_ctrl;
150 struct local_vec_tbl_reg local_vec_tbl;
151 struct tmr_vec_tbl_reg tmr_vec_tbl;
152 struct tmr_div_cfg_reg tmr_div_cfg;
153 struct lint_vec_tbl_reg lint0_vec_tbl;
154 struct lint_vec_tbl_reg lint1_vec_tbl;
155 struct perf_ctr_loc_vec_tbl_reg perf_ctr_loc_vec_tbl;
156 struct therm_loc_vec_tbl_reg therm_loc_vec_tbl;
157 struct err_vec_tbl_reg err_vec_tbl;
158 struct err_status_reg err_status;
159 struct spurious_int_reg spurious_int;
160 struct int_cmd_reg int_cmd;
161 struct log_dst_reg log_dst;
162 struct dst_fmt_reg dst_fmt;
163 struct arb_prio_reg arb_prio;
164 struct task_prio_reg task_prio;
165 struct proc_prio_reg proc_prio;
166 struct ext_apic_feature_reg ext_apic_feature;
167 struct spec_eoi_reg spec_eoi;
170 uint32_t tmr_cur_cnt;
171 uint32_t tmr_init_cnt;
174 struct local_vec_tbl_reg ext_intr_vec_tbl[4];
176 uint32_t rem_rd_data;
179 uchar_t int_req_reg[32];
180 uchar_t int_svc_reg[32];
181 uchar_t int_en_reg[32];
182 uchar_t trig_mode_reg[32];
186 struct vm_device * icc_bus;
195 static int apic_read(struct guest_info * core, addr_t guest_addr, void * dst, uint_t length, void * priv_data);
196 static int apic_write(struct guest_info * core, addr_t guest_addr, void * src, uint_t length, void * priv_data);
198 static void init_apic_state(struct apic_state * apic, uint32_t id, struct vm_device * icc) {
199 apic->base_addr = DEFAULT_BASE_ADDR;
201 // boot processor, enabled
202 apic->base_addr_msr.value = 0x0000000000000900LL;
204 // ap processor, enabled
205 apic->base_addr_msr.value = 0x0000000000000800LL;
208 // same base address regardless of ap or main
209 apic->base_addr_msr.value |= ((uint64_t)DEFAULT_BASE_ADDR);
211 PrintDebug("apic %u: (init_apic_state): msr=0x%llx\n",id, apic->base_addr_msr.value);
213 PrintDebug("apic %u: (init_apic_state): Sizeof Interrupt Request Register %d, should be 32\n",
214 id, (uint_t)sizeof(apic->int_req_reg));
216 memset(apic->int_req_reg, 0, sizeof(apic->int_req_reg));
217 memset(apic->int_svc_reg, 0, sizeof(apic->int_svc_reg));
218 memset(apic->int_en_reg, 0xff, sizeof(apic->int_en_reg));
219 memset(apic->trig_mode_reg, 0, sizeof(apic->trig_mode_reg));
221 apic->eoi = 0x00000000;
222 apic->rem_rd_data = 0x00000000;
223 apic->tmr_init_cnt = 0x00000000;
224 apic->tmr_cur_cnt = 0x00000000;
226 apic->lapic_id.val = id;
230 // The P6 has 6 LVT entries, so we set the value to (6-1)...
231 apic->apic_ver.val = 0x80050010;
233 apic->task_prio.val = 0x00000000;
234 apic->arb_prio.val = 0x00000000;
235 apic->proc_prio.val = 0x00000000;
236 apic->log_dst.val = 0x00000000;
237 apic->dst_fmt.val = 0xffffffff;
238 apic->spurious_int.val = 0x000000ff;
239 apic->err_status.val = 0x00000000;
240 apic->int_cmd.val = 0x0000000000000000LL;
241 apic->tmr_vec_tbl.val = 0x00010000;
242 apic->therm_loc_vec_tbl.val = 0x00010000;
243 apic->perf_ctr_loc_vec_tbl.val = 0x00010000;
244 apic->lint0_vec_tbl.val = 0x00010000;
245 apic->lint1_vec_tbl.val = 0x00010000;
246 apic->err_vec_tbl.val = 0x00010000;
247 apic->tmr_div_cfg.val = 0x00000000;
248 //apic->ext_apic_feature.val = 0x00000007;
249 apic->ext_apic_feature.val = 0x00040007;
250 apic->ext_apic_ctrl.val = 0x00000000;
251 apic->spec_eoi.val = 0x00000000;
253 v3_lock_init(&(apic->lock));
259 static int read_apic_msr(struct guest_info * core, uint_t msr, v3_msr_t * dst, void * priv_data) {
260 struct vm_device * dev = (struct vm_device *)priv_data;
261 struct apic_state * apics = (struct apic_state *)(dev->private_data);
262 struct apic_state * apic = &(apics[core->cpu_id]);
264 PrintDebug("apic %u: core %u: MSR read\n",apic->lapic_id.val,core->cpu_id);
266 dst->value = apic->base_addr;
267 v3_unlock(apic->lock);
272 static int write_apic_msr(struct guest_info * core, uint_t msr, v3_msr_t src, void * priv_data) {
273 struct vm_device * dev = (struct vm_device *)priv_data;
274 struct apic_state * apics = (struct apic_state *)(dev->private_data);
275 struct apic_state * apic = &(apics[core->cpu_id]);
276 struct v3_mem_region * old_reg = v3_get_mem_region(dev->vm, core->cpu_id, apic->base_addr);
279 PrintDebug("apic %u: core %u: MSR write\n",apic->lapic_id.val,core->cpu_id);
281 if (old_reg == NULL) {
283 PrintError("apic %u: core %u: APIC Base address region does not exit...\n",apic->lapic_id.val,core->cpu_id);
289 v3_delete_mem_region(dev->vm, old_reg);
291 apic->base_addr = src.value;
293 if (v3_hook_full_mem(dev->vm, core->cpu_id, apic->base_addr, apic->base_addr + PAGE_SIZE_4KB, apic_read, apic_write, dev) == -1) {
294 PrintError("apic %u: core %u: Could not hook new APIC Base address\n",apic->lapic_id.val,core->cpu_id);
295 v3_unlock(apic->lock);
299 v3_unlock(apic->lock);
304 // irq_num is the bit offset into a 256 bit buffer...
305 static int activate_apic_irq(struct apic_state * apic, uint32_t irq_num) {
306 int major_offset = (irq_num & ~0x00000007) >> 3;
307 int minor_offset = irq_num & 0x00000007;
308 uchar_t * req_location = apic->int_req_reg + major_offset;
309 uchar_t * en_location = apic->int_en_reg + major_offset;
310 uchar_t flag = 0x1 << minor_offset;
316 PrintError("apic %u: core ?: Attempting to raise an invalid interrupt: %d\n", apic->lapic_id.val,irq_num);
323 PrintDebug("apic %u: core ?: Raising APIC IRQ %d\n", apic->lapic_id.val,irq_num);
325 if (*req_location & flag) {
326 //V3_Print("Interrupts coallescing\n");
329 if (*en_location & flag) {
330 *req_location |= flag;
332 PrintDebug("apic %u: core ?: Interrupt not enabled... %.2x\n", apic->lapic_id.val, *en_location);
341 static int get_highest_isr(struct apic_state * apic) {
344 // We iterate backwards to find the highest priority
345 for (i = 31; i >= 0; i--) {
346 uchar_t * svc_major = apic->int_svc_reg + i;
348 if ((*svc_major) & 0xff) {
349 for (j = 7; j >= 0; j--) {
350 uchar_t flag = 0x1 << j;
351 if ((*svc_major) & flag) {
352 return ((i * 8) + j);
363 static int get_highest_irr(struct apic_state * apic) {
366 // We iterate backwards to find the highest priority
367 for (i = 31; i >= 0; i--) {
368 uchar_t * req_major = apic->int_req_reg + i;
370 if ((*req_major) & 0xff) {
371 for (j = 7; j >= 0; j--) {
372 uchar_t flag = 0x1 << j;
373 if ((*req_major) & flag) {
374 return ((i * 8) + j);
386 static int apic_do_eoi(struct apic_state * apic) {
387 int isr_irq = get_highest_isr(apic);
390 int major_offset = (isr_irq & ~0x00000007) >> 3;
391 int minor_offset = isr_irq & 0x00000007;
392 uchar_t flag = 0x1 << minor_offset;
393 uchar_t * svc_location = apic->int_svc_reg + major_offset;
395 PrintDebug("apic %u: core ?: Received APIC EOI for IRQ %d\n", apic->lapic_id.val,isr_irq);
397 *svc_location &= ~flag;
399 #ifdef CONFIG_CRAY_XT
401 if ((isr_irq == 238) ||
403 PrintError("apic %u: core ?: Acking IRQ %d\n", apic->lapic_id.val,isr_irq);
406 if (isr_irq == 238) {
411 //PrintError("apic %u: core ?: Spurious EOI...\n",apic->lapic_id.val);
418 static int activate_internal_irq(struct apic_state * apic, apic_irq_type_t int_type) {
419 uint32_t vec_num = 0;
420 uint32_t del_mode = 0;
426 vec_num = apic->tmr_vec_tbl.vec;
427 del_mode = APIC_FIXED_DELIVERY;
428 masked = apic->tmr_vec_tbl.mask;
431 vec_num = apic->therm_loc_vec_tbl.vec;
432 del_mode = apic->therm_loc_vec_tbl.msg_type;
433 masked = apic->therm_loc_vec_tbl.mask;
436 vec_num = apic->perf_ctr_loc_vec_tbl.vec;
437 del_mode = apic->perf_ctr_loc_vec_tbl.msg_type;
438 masked = apic->perf_ctr_loc_vec_tbl.mask;
441 vec_num = apic->lint0_vec_tbl.vec;
442 del_mode = apic->lint0_vec_tbl.msg_type;
443 masked = apic->lint0_vec_tbl.mask;
446 vec_num = apic->lint1_vec_tbl.vec;
447 del_mode = apic->lint1_vec_tbl.msg_type;
448 masked = apic->lint1_vec_tbl.mask;
451 vec_num = apic->err_vec_tbl.vec;
452 del_mode = APIC_FIXED_DELIVERY;
453 masked = apic->err_vec_tbl.mask;
456 PrintError("apic %u: core ?: Invalid APIC interrupt type\n",apic->lapic_id.val);
460 // interrupt is masked, don't send
462 PrintDebug("apic %u: core ?: Inerrupt is masked\n",apic->lapic_id.val);
466 if (del_mode == APIC_FIXED_DELIVERY) {
467 //PrintDebug("Activating internal APIC IRQ %d\n", vec_num);
468 return activate_apic_irq(apic, vec_num);
470 PrintError("apic %u: core ?: Unhandled Delivery Mode\n",apic->lapic_id.val);
476 static int apic_read(struct guest_info * core, addr_t guest_addr, void * dst, uint_t length, void * priv_data) {
477 struct apic_state * apic = (struct apic_state *)(priv_data);
478 addr_t reg_addr = guest_addr - apic->base_addr;
479 struct apic_msr * msr = (struct apic_msr *)&(apic->base_addr_msr.value);
483 PrintDebug("apic %u: core %u: at %p: Read apic address space (%p)\n",apic->lapic_id.val,core->cpu_id, apic, (void *)guest_addr);
485 if (msr->apic_enable == 0) {
486 PrintError("apic %u: core %u: Read from APIC address space with disabled APIC, apic msr=0x%llx\n",apic->lapic_id.val,core->cpu_id,apic->base_addr_msr.value);
492 /* Because "May not be supported" doesn't matter to Linux developers... */
493 /* if (length != 4) { */
494 /* PrintError("Invalid apic read length (%d)\n", length); */
498 switch (reg_addr & ~0x3) {
500 // Well, only an idiot would read from a architectural write only register
502 // PrintError("Attempting to read from write only register\n");
508 val = apic->lapic_id.val;
510 case APIC_VERSION_OFFSET:
511 val = apic->apic_ver.val;
514 val = apic->task_prio.val;
517 val = apic->arb_prio.val;
520 val = apic->proc_prio.val;
522 case REMOTE_READ_OFFSET:
523 val = apic->rem_rd_data;
526 val = apic->log_dst.val;
529 val = apic->dst_fmt.val;
531 case SPURIOUS_INT_VEC_OFFSET:
532 val = apic->spurious_int.val;
535 val = apic->err_status.val;
537 case TMR_LOC_VEC_TBL_OFFSET:
538 val = apic->tmr_vec_tbl.val;
540 case LINT0_VEC_TBL_OFFSET:
541 val = apic->lint0_vec_tbl.val;
543 case LINT1_VEC_TBL_OFFSET:
544 val = apic->lint1_vec_tbl.val;
546 case ERR_VEC_TBL_OFFSET:
547 val = apic->err_vec_tbl.val;
549 case TMR_INIT_CNT_OFFSET:
550 val = apic->tmr_init_cnt;
552 case TMR_DIV_CFG_OFFSET:
553 val = apic->tmr_div_cfg.val;
557 val = *(uint32_t *)(apic->int_en_reg);
560 val = *(uint32_t *)(apic->int_en_reg + 4);
563 val = *(uint32_t *)(apic->int_en_reg + 8);
566 val = *(uint32_t *)(apic->int_en_reg + 12);
569 val = *(uint32_t *)(apic->int_en_reg + 16);
572 val = *(uint32_t *)(apic->int_en_reg + 20);
575 val = *(uint32_t *)(apic->int_en_reg + 24);
578 val = *(uint32_t *)(apic->int_en_reg + 28);
582 val = *(uint32_t *)(apic->int_svc_reg);
585 val = *(uint32_t *)(apic->int_svc_reg + 4);
588 val = *(uint32_t *)(apic->int_svc_reg + 8);
591 val = *(uint32_t *)(apic->int_svc_reg + 12);
594 val = *(uint32_t *)(apic->int_svc_reg + 16);
597 val = *(uint32_t *)(apic->int_svc_reg + 20);
600 val = *(uint32_t *)(apic->int_svc_reg + 24);
603 val = *(uint32_t *)(apic->int_svc_reg + 28);
607 val = *(uint32_t *)(apic->trig_mode_reg);
610 val = *(uint32_t *)(apic->trig_mode_reg + 4);
613 val = *(uint32_t *)(apic->trig_mode_reg + 8);
616 val = *(uint32_t *)(apic->trig_mode_reg + 12);
619 val = *(uint32_t *)(apic->trig_mode_reg + 16);
622 val = *(uint32_t *)(apic->trig_mode_reg + 20);
625 val = *(uint32_t *)(apic->trig_mode_reg + 24);
628 val = *(uint32_t *)(apic->trig_mode_reg + 28);
632 val = *(uint32_t *)(apic->int_req_reg);
635 val = *(uint32_t *)(apic->int_req_reg + 4);
638 val = *(uint32_t *)(apic->int_req_reg + 8);
641 val = *(uint32_t *)(apic->int_req_reg + 12);
644 val = *(uint32_t *)(apic->int_req_reg + 16);
647 val = *(uint32_t *)(apic->int_req_reg + 20);
650 val = *(uint32_t *)(apic->int_req_reg + 24);
653 val = *(uint32_t *)(apic->int_req_reg + 28);
655 case TMR_CUR_CNT_OFFSET:
656 val = apic->tmr_cur_cnt;
659 // We are not going to implement these....
660 case THERM_LOC_VEC_TBL_OFFSET:
661 val = apic->therm_loc_vec_tbl.val;
663 case PERF_CTR_LOC_VEC_TBL_OFFSET:
664 val = apic->perf_ctr_loc_vec_tbl.val;
670 case INT_CMD_LO_OFFSET:
671 val = apic->int_cmd.lo;
673 case INT_CMD_HI_OFFSET:
674 val = apic->int_cmd.hi;
677 // handle current timer count
679 // Unhandled Registers
680 case EXT_INT_LOC_VEC_TBL_OFFSET0:
681 val = apic->ext_intr_vec_tbl[0].val;
683 case EXT_INT_LOC_VEC_TBL_OFFSET1:
684 val = apic->ext_intr_vec_tbl[1].val;
686 case EXT_INT_LOC_VEC_TBL_OFFSET2:
687 val = apic->ext_intr_vec_tbl[2].val;
689 case EXT_INT_LOC_VEC_TBL_OFFSET3:
690 val = apic->ext_intr_vec_tbl[3].val;
694 case EXT_APIC_FEATURE_OFFSET:
695 case EXT_APIC_CMD_OFFSET:
699 PrintError("apic %u: core %u: Read from Unhandled APIC Register: %x (getting zero)\n", apic->lapic_id.val,core->cpu_id, (uint32_t)reg_addr);
706 uint_t byte_addr = reg_addr & 0x3;
707 uint8_t * val_ptr = (uint8_t *)dst;
709 *val_ptr = *(((uint8_t *)&val) + byte_addr);
711 } else if ((length == 2) &&
712 ((reg_addr & 0x3) == 0x3)) {
713 uint_t byte_addr = reg_addr & 0x3;
714 uint16_t * val_ptr = (uint16_t *)dst;
715 *val_ptr = *(((uint16_t *)&val) + byte_addr);
717 } else if (length == 4) {
718 uint32_t * val_ptr = (uint32_t *)dst;
722 PrintError("apic %u: core %u: Invalid apic read length (%d)\n", apic->lapic_id.val,core->cpu_id, length);
726 PrintDebug("apic %u: core %u: Read finished (val=%x)\n", apic->lapic_id.val,core->cpu_id, *(uint32_t *)dst);
735 static int apic_write(struct guest_info * core, addr_t guest_addr, void * src, uint_t length, void * priv_data) {
736 struct apic_state * apic = (struct apic_state *)(priv_data);
737 addr_t reg_addr = guest_addr - apic->base_addr;
738 struct apic_msr * msr = (struct apic_msr *)&(apic->base_addr_msr.value);
739 uint32_t op_val = *(uint32_t *)src;
741 PrintDebug("apic %u: core %u: at %p and priv_data is at %p: Write to address space (%p) (val=%x)\n",
742 apic->lapic_id.val, core->cpu_id, apic,priv_data,
743 (void *)guest_addr, *(uint32_t *)src);
745 if (msr->apic_enable == 0) {
746 PrintError("apic %u: core %u: Write to APIC address space with disabled APIC, apic msr=0x%llx\n",apic->lapic_id.val,core->cpu_id,apic->base_addr_msr.value);
752 PrintError("apic %u: core %u: Invalid apic write length (%d)\n", apic->lapic_id.val, length,core->cpu_id);
757 case REMOTE_READ_OFFSET:
758 case APIC_VERSION_OFFSET:
785 case EXT_APIC_FEATURE_OFFSET:
787 PrintError("apic %u: core %u: Attempting to write to read only register %p (ignored)\n", apic->lapic_id.val,core->cpu_id, (void *)reg_addr);
789 PrintError("apic %u: core %u: Attempting to write to read only register %p (error)\n", apic->lapic_id.val,core->cpu_id, (void *)reg_addr);
796 PrintDebug("apic %u: core %u: my id is being changed to %u\n",apic->lapic_id.val,core->cpu_id,op_val);
797 apic->lapic_id.val = op_val;
800 apic->task_prio.val = op_val;
803 apic->log_dst.val = op_val;
806 apic->dst_fmt.val = op_val;
808 case SPURIOUS_INT_VEC_OFFSET:
809 apic->spurious_int.val = op_val;
812 apic->err_status.val = op_val;
814 case TMR_LOC_VEC_TBL_OFFSET:
815 apic->tmr_vec_tbl.val = op_val;
817 case THERM_LOC_VEC_TBL_OFFSET:
818 apic->therm_loc_vec_tbl.val = op_val;
820 case PERF_CTR_LOC_VEC_TBL_OFFSET:
821 apic->perf_ctr_loc_vec_tbl.val = op_val;
823 case LINT0_VEC_TBL_OFFSET:
824 apic->lint0_vec_tbl.val = op_val;
826 case LINT1_VEC_TBL_OFFSET:
827 apic->lint1_vec_tbl.val = op_val;
829 case ERR_VEC_TBL_OFFSET:
830 apic->err_vec_tbl.val = op_val;
832 case TMR_INIT_CNT_OFFSET:
833 apic->tmr_init_cnt = op_val;
834 apic->tmr_cur_cnt = op_val;
836 case TMR_CUR_CNT_OFFSET:
837 apic->tmr_cur_cnt = op_val;
839 case TMR_DIV_CFG_OFFSET:
840 apic->tmr_div_cfg.val = op_val;
844 // Enable mask (256 bits)
846 *(uint32_t *)(apic->int_en_reg) = op_val;
849 *(uint32_t *)(apic->int_en_reg + 4) = op_val;
852 *(uint32_t *)(apic->int_en_reg + 8) = op_val;
855 *(uint32_t *)(apic->int_en_reg + 12) = op_val;
858 *(uint32_t *)(apic->int_en_reg + 16) = op_val;
861 *(uint32_t *)(apic->int_en_reg + 20) = op_val;
864 *(uint32_t *)(apic->int_en_reg + 24) = op_val;
867 *(uint32_t *)(apic->int_en_reg + 28) = op_val;
870 case EXT_INT_LOC_VEC_TBL_OFFSET0:
871 apic->ext_intr_vec_tbl[0].val = op_val;
873 case EXT_INT_LOC_VEC_TBL_OFFSET1:
874 apic->ext_intr_vec_tbl[1].val = op_val;
876 case EXT_INT_LOC_VEC_TBL_OFFSET2:
877 apic->ext_intr_vec_tbl[2].val = op_val;
879 case EXT_INT_LOC_VEC_TBL_OFFSET3:
880 apic->ext_intr_vec_tbl[3].val = op_val;
890 case INT_CMD_LO_OFFSET:
891 apic->int_cmd.lo = op_val;
893 PrintDebug("apic %u: core %u: sending cmd 0x%llx to apic %u\n",apic->lapic_id.val,core->cpu_id,
894 apic->int_cmd.val, apic->int_cmd.dst);
895 if (v3_icc_send_ipi(apic->icc_bus, apic->lapic_id.val, apic->int_cmd.val,apic->dst_fmt.val,0)==-1) {
899 case INT_CMD_HI_OFFSET:
900 apic->int_cmd.hi = op_val;
902 // Unhandled Registers
904 case EXT_APIC_CMD_OFFSET:
907 PrintError("apic %u: core %u: Write to Unhandled APIC Register: %x (ignored)\n", apic->lapic_id.val,core->cpu_id, (uint32_t)reg_addr);
911 PrintDebug("apic %u: core %u: Write finished\n",apic->lapic_id.val,core->cpu_id);
918 /* Interrupt Controller Functions */
920 // returns 1 if an interrupt is pending, 0 otherwise
921 static int apic_intr_pending(struct guest_info * info, void * private_data) {
922 struct apic_state * apic = (struct apic_state *)private_data;
923 int req_irq = get_highest_irr(apic);
924 int svc_irq = get_highest_isr(apic);
926 // PrintDebug("apic %u: core %u: req_irq=%d, svc_irq=%d\n",apic->lapic_id.val,info->cpu_id,req_irq,svc_irq);
928 if ((req_irq >= 0) &&
929 (req_irq > svc_irq)) {
936 static int apic_get_intr_number(struct guest_info * info, void * private_data) {
937 struct apic_state * apic = (struct apic_state *)private_data;
938 int req_irq = get_highest_irr(apic);
939 int svc_irq = get_highest_isr(apic);
943 } else if (svc_irq < req_irq) {
951 static int apic_raise_intr(struct guest_info * info, int irq, void * private_data) {
952 struct apic_state * apic = (struct apic_state *)private_data;
954 return activate_apic_irq(apic, irq);
959 static int apic_begin_irq(struct guest_info * info, void * private_data, int irq) {
960 struct apic_state * apic = (struct apic_state *)private_data;
961 int major_offset = (irq & ~0x00000007) >> 3;
962 int minor_offset = irq & 0x00000007;
963 uchar_t * req_location = apic->int_req_reg + major_offset;
964 uchar_t * svc_location = apic->int_svc_reg + major_offset;
965 uchar_t flag = 0x01 << minor_offset;
967 if (*req_location & flag) {
968 // we will only pay attention to a begin irq if we
969 // know that we initiated it!
970 *svc_location |= flag;
971 *req_location &= ~flag;
974 PrintDebug("apic %u: core %u: begin irq for %d ignored since I don't own it\n",
975 apic->lapic_id.val,info->cpu_id,irq);
986 /* Timer Functions */
987 static void apic_update_time(struct guest_info * info, ullong_t cpu_cycles, ullong_t cpu_freq, void * priv_data) {
988 struct apic_state * apic = (struct apic_state *)(priv_data);
989 // The 32 bit GCC runtime is a pile of shit
991 uint64_t tmr_ticks = 0;
993 uint32_t tmr_ticks = 0;
996 uchar_t tmr_div = *(uchar_t *)&(apic->tmr_div_cfg.val);
997 uint_t shift_num = 0;
1000 // Check whether this is true:
1001 // -> If the Init count is zero then the timer is disabled
1002 // and doesn't just blitz interrupts to the CPU
1003 if ((apic->tmr_init_cnt == 0) ||
1004 ( (apic->tmr_vec_tbl.tmr_mode == APIC_TMR_ONESHOT) &&
1005 (apic->tmr_cur_cnt == 0))) {
1006 //PrintDebug("apic %u: core %u: APIC timer not yet initialized\n",apic->lapic_id.val,info->cpu_id);
1024 case APIC_TMR_DIV16:
1027 case APIC_TMR_DIV32:
1030 case APIC_TMR_DIV64:
1033 case APIC_TMR_DIV128:
1037 PrintError("apic %u: core %u: Invalid Timer Divider configuration\n",apic->lapic_id.val,info->cpu_id);
1041 tmr_ticks = cpu_cycles >> shift_num;
1042 // PrintDebug("Timer Ticks: %p\n", (void *)tmr_ticks);
1044 if (tmr_ticks < apic->tmr_cur_cnt) {
1045 apic->tmr_cur_cnt -= tmr_ticks;
1047 tmr_ticks -= apic->tmr_cur_cnt;
1048 apic->tmr_cur_cnt = 0;
1051 PrintDebug("apic %u: core %u: Raising APIC Timer interrupt (periodic=%d) (icnt=%d) (div=%d)\n", apic->lapic_id.val,info->cpu_id,
1052 apic->tmr_vec_tbl.tmr_mode, apic->tmr_init_cnt, shift_num);
1054 if (apic_intr_pending(info, priv_data)) {
1055 PrintDebug("apic %u: core %u: Overriding pending IRQ %d\n", apic->lapic_id.val,info->cpu_id, apic_get_intr_number(info, priv_data));
1058 if (activate_internal_irq(apic, APIC_TMR_INT) == -1) {
1059 PrintError("apic %u: core %u: Could not raise Timer interrupt\n",apic->lapic_id.val,info->cpu_id);
1062 if (apic->tmr_vec_tbl.tmr_mode == APIC_TMR_PERIODIC) {
1063 tmr_ticks = tmr_ticks % apic->tmr_init_cnt;
1064 apic->tmr_cur_cnt = apic->tmr_init_cnt - tmr_ticks;
1072 static struct intr_ctrl_ops intr_ops = {
1073 .intr_pending = apic_intr_pending,
1074 .get_intr_number = apic_get_intr_number,
1075 .begin_irq = apic_begin_irq,
1079 static struct vm_timer_ops timer_ops = {
1080 .update_time = apic_update_time,
1086 static int apic_free(struct vm_device * dev) {
1088 /* TODO: This should crosscall to force an unhook on each CPU */
1090 // struct apic_state * apic = (struct apic_state *)dev->private_data;
1092 v3_unhook_msr(dev->vm, BASE_ADDR_MSR);
1098 static struct v3_device_ops dev_ops = {
1107 static int apic_should_deliver_flat(struct guest_info * core, uint8_t mda, void * private_data)
1109 struct apic_state * apic = (struct apic_state *)private_data;
1111 if (mda==0xff || (apic->log_dst.dst_log_id & mda)) {
1118 static struct v3_icc_ops icc_ops = {
1119 .raise_intr = apic_raise_intr,
1120 .should_deliver_flat = apic_should_deliver_flat,
1125 static int apic_init(struct v3_vm_info * vm, v3_cfg_tree_t * cfg) {
1126 PrintDebug("apic: creating an APIC for each core\n");
1127 char * name = v3_cfg_val(cfg, "name");
1128 char * icc_name = v3_cfg_val(cfg,"bus");
1129 struct vm_device * icc = v3_find_dev(vm, icc_name);
1133 PrintError("apic: Cannot find ICC Bus (%s)\n", icc_name);
1137 // We allocate one apic per core
1138 // APICs are accessed via index which correlates with the core's cpu_id
1139 // 0..num_cores-1 at num_cores is the ioapic (one only)
1140 struct apic_state * apic = (struct apic_state *)V3_Malloc(sizeof(struct apic_state) * vm->num_cores);
1142 struct vm_device * dev = v3_allocate_device(name, &dev_ops, apic);
1144 if (v3_attach_device(vm, dev) == -1) {
1145 PrintError("apic: Could not attach device %s\n", name);
1150 for (i = 0; i < vm->num_cores; i++) {
1151 struct guest_info * core = &(vm->cores[i]);
1153 init_apic_state(&(apic[i]),i,icc);
1155 v3_register_intr_controller(core, &intr_ops, &(apic[i]));
1157 v3_add_timer(core, &timer_ops, &(apic[i]));
1159 v3_hook_full_mem(vm, core->cpu_id, apic->base_addr, apic->base_addr + PAGE_SIZE_4KB, apic_read, apic_write, &(apic[i]));
1161 v3_icc_register_apic(core, icc, i, &icc_ops, &(apic[i]));
1163 PrintDebug("apic %u: (setup device): done, my id is %u\n",i,apic[i].lapic_id.val);
1167 for (i=0;i<vm->num_cores;i++) {
1168 PrintDebug("apic: sanity check: apic %u (at %p) has id %u and msr value %llx\n",
1169 i, &(apic[i]), apic[i].lapic_id.val, apic[i].base_addr_msr.value);
1171 PrintDebug("apic: priv_data is at %p\n", apic);
1173 v3_hook_msr(vm, BASE_ADDR_MSR, read_apic_msr, write_apic_msr, dev);
1180 device_register("LAPIC", apic_init)