2 * This file is part of the Palacios Virtual Machine Monitor developed
3 * by the V3VEE Project with funding from the United States National
4 * Science Foundation and the Department of Energy.
6 * The V3VEE Project is a joint project between Northwestern University
7 * and the University of New Mexico. You can find out more at
10 * Copyright (c) 2008, Jack Lange <jarusl@cs.northwestern.edu>
11 * Copyright (c) 2008, The V3VEE Project <http://www.v3vee.org>
12 * All rights reserved.
14 * Author: Jack Lange <jarusl@cs.northwestern.edu>
16 * This is free software. You are permitted to use,
17 * redistribute, and modify it as specified in the file "V3VEE_LICENSE".
21 #include <devices/apic.h>
22 #include <devices/apic_regs.h>
23 #include <palacios/vmm.h>
24 #include <palacios/vmm_msr.h>
25 #include <palacios/vmm_sprintf.h>
26 #include <palacios/vm_guest.h>
27 #include <palacios/vmm_types.h>
30 #ifndef CONFIG_DEBUG_APIC
32 #define PrintDebug(fmt, args...)
35 #ifdef CONFIG_DEBUG_APIC
36 static char *shorthand_str[] = {
43 static char *deliverymode_str[] = {
55 typedef enum { APIC_TMR_INT, APIC_THERM_INT, APIC_PERF_INT,
56 APIC_LINT0_INT, APIC_LINT1_INT, APIC_ERR_INT } apic_irq_type_t;
58 #define APIC_FIXED_DELIVERY 0x0
59 #define APIC_SMI_DELIVERY 0x2
60 #define APIC_NMI_DELIVERY 0x4
61 #define APIC_INIT_DELIVERY 0x5
62 #define APIC_EXTINT_DELIVERY 0x7
65 #define BASE_ADDR_MSR 0x0000001B
66 #define DEFAULT_BASE_ADDR 0xfee00000
68 #define APIC_ID_OFFSET 0x020
69 #define APIC_VERSION_OFFSET 0x030
70 #define TPR_OFFSET 0x080
71 #define APR_OFFSET 0x090
72 #define PPR_OFFSET 0x0a0
73 #define EOI_OFFSET 0x0b0
74 #define REMOTE_READ_OFFSET 0x0c0
75 #define LDR_OFFSET 0x0d0
76 #define DFR_OFFSET 0x0e0
77 #define SPURIOUS_INT_VEC_OFFSET 0x0f0
79 #define ISR_OFFSET0 0x100 // 0x100 - 0x170
80 #define ISR_OFFSET1 0x110 // 0x100 - 0x170
81 #define ISR_OFFSET2 0x120 // 0x100 - 0x170
82 #define ISR_OFFSET3 0x130 // 0x100 - 0x170
83 #define ISR_OFFSET4 0x140 // 0x100 - 0x170
84 #define ISR_OFFSET5 0x150 // 0x100 - 0x170
85 #define ISR_OFFSET6 0x160 // 0x100 - 0x170
86 #define ISR_OFFSET7 0x170 // 0x100 - 0x170
88 #define TRIG_OFFSET0 0x180 // 0x180 - 0x1f0
89 #define TRIG_OFFSET1 0x190 // 0x180 - 0x1f0
90 #define TRIG_OFFSET2 0x1a0 // 0x180 - 0x1f0
91 #define TRIG_OFFSET3 0x1b0 // 0x180 - 0x1f0
92 #define TRIG_OFFSET4 0x1c0 // 0x180 - 0x1f0
93 #define TRIG_OFFSET5 0x1d0 // 0x180 - 0x1f0
94 #define TRIG_OFFSET6 0x1e0 // 0x180 - 0x1f0
95 #define TRIG_OFFSET7 0x1f0 // 0x180 - 0x1f0
98 #define IRR_OFFSET0 0x200 // 0x200 - 0x270
99 #define IRR_OFFSET1 0x210 // 0x200 - 0x270
100 #define IRR_OFFSET2 0x220 // 0x200 - 0x270
101 #define IRR_OFFSET3 0x230 // 0x200 - 0x270
102 #define IRR_OFFSET4 0x240 // 0x200 - 0x270
103 #define IRR_OFFSET5 0x250 // 0x200 - 0x270
104 #define IRR_OFFSET6 0x260 // 0x200 - 0x270
105 #define IRR_OFFSET7 0x270 // 0x200 - 0x270
108 #define ESR_OFFSET 0x280
109 #define INT_CMD_LO_OFFSET 0x300
110 #define INT_CMD_HI_OFFSET 0x310
111 #define TMR_LOC_VEC_TBL_OFFSET 0x320
112 #define THERM_LOC_VEC_TBL_OFFSET 0x330
113 #define PERF_CTR_LOC_VEC_TBL_OFFSET 0x340
114 #define LINT0_VEC_TBL_OFFSET 0x350
115 #define LINT1_VEC_TBL_OFFSET 0x360
116 #define ERR_VEC_TBL_OFFSET 0x370
117 #define TMR_INIT_CNT_OFFSET 0x380
118 #define TMR_CUR_CNT_OFFSET 0x390
119 #define TMR_DIV_CFG_OFFSET 0x3e0
120 #define EXT_APIC_FEATURE_OFFSET 0x400
121 #define EXT_APIC_CMD_OFFSET 0x410
122 #define SEOI_OFFSET 0x420
124 #define IER_OFFSET0 0x480 // 0x480 - 0x4f0
125 #define IER_OFFSET1 0x490 // 0x480 - 0x4f0
126 #define IER_OFFSET2 0x4a0 // 0x480 - 0x4f0
127 #define IER_OFFSET3 0x4b0 // 0x480 - 0x4f0
128 #define IER_OFFSET4 0x4c0 // 0x480 - 0x4f0
129 #define IER_OFFSET5 0x4d0 // 0x480 - 0x4f0
130 #define IER_OFFSET6 0x4e0 // 0x480 - 0x4f0
131 #define IER_OFFSET7 0x4f0 // 0x480 - 0x4f0
133 #define EXT_INT_LOC_VEC_TBL_OFFSET0 0x500 // 0x500 - 0x530
134 #define EXT_INT_LOC_VEC_TBL_OFFSET1 0x510 // 0x500 - 0x530
135 #define EXT_INT_LOC_VEC_TBL_OFFSET2 0x520 // 0x500 - 0x530
136 #define EXT_INT_LOC_VEC_TBL_OFFSET3 0x530 // 0x500 - 0x530
147 uint8_t bootstrap_cpu : 1;
149 uint8_t apic_enable : 1;
150 uint64_t base_addr : 40;
152 } __attribute__((packed));
153 } __attribute__((packed));
154 } __attribute__((packed));
158 typedef enum {INIT_ST,
160 STARTED} ipi_state_t;
162 struct apic_dev_state;
168 struct apic_msr base_addr_msr;
171 /* memory map registers */
173 struct lapic_id_reg lapic_id;
174 struct apic_ver_reg apic_ver;
175 struct ext_apic_ctrl_reg ext_apic_ctrl;
176 struct local_vec_tbl_reg local_vec_tbl;
177 struct tmr_vec_tbl_reg tmr_vec_tbl;
178 struct tmr_div_cfg_reg tmr_div_cfg;
179 struct lint_vec_tbl_reg lint0_vec_tbl;
180 struct lint_vec_tbl_reg lint1_vec_tbl;
181 struct perf_ctr_loc_vec_tbl_reg perf_ctr_loc_vec_tbl;
182 struct therm_loc_vec_tbl_reg therm_loc_vec_tbl;
183 struct err_vec_tbl_reg err_vec_tbl;
184 struct err_status_reg err_status;
185 struct spurious_int_reg spurious_int;
186 struct int_cmd_reg int_cmd;
187 struct log_dst_reg log_dst;
188 struct dst_fmt_reg dst_fmt;
189 struct arb_prio_reg arb_prio;
190 struct task_prio_reg task_prio;
191 struct proc_prio_reg proc_prio;
192 struct ext_apic_feature_reg ext_apic_feature;
193 struct spec_eoi_reg spec_eoi;
196 uint32_t tmr_cur_cnt;
197 uint32_t tmr_init_cnt;
200 struct local_vec_tbl_reg ext_intr_vec_tbl[4];
202 uint32_t rem_rd_data;
205 ipi_state_t ipi_state;
207 uint8_t int_req_reg[32];
208 uint8_t int_svc_reg[32];
209 uint8_t int_en_reg[32];
210 uint8_t trig_mode_reg[32];
212 struct guest_info * core;
222 struct apic_dev_state {
225 struct apic_state apics[0];
226 } __attribute__((packed));
230 static int apic_read(struct guest_info * core, addr_t guest_addr, void * dst, uint_t length, void * priv_data);
231 static int apic_write(struct guest_info * core, addr_t guest_addr, void * src, uint_t length, void * priv_data);
233 static void init_apic_state(struct apic_state * apic, uint32_t id) {
234 apic->base_addr = DEFAULT_BASE_ADDR;
237 // boot processor, enabled
238 apic->base_addr_msr.value = 0x0000000000000900LL;
240 // ap processor, enabled
241 apic->base_addr_msr.value = 0x0000000000000800LL;
244 // same base address regardless of ap or main
245 apic->base_addr_msr.value |= ((uint64_t)DEFAULT_BASE_ADDR);
247 PrintDebug("apic %u: (init_apic_state): msr=0x%llx\n",id, apic->base_addr_msr.value);
249 PrintDebug("apic %u: (init_apic_state): Sizeof Interrupt Request Register %d, should be 32\n",
250 id, (uint_t)sizeof(apic->int_req_reg));
252 memset(apic->int_req_reg, 0, sizeof(apic->int_req_reg));
253 memset(apic->int_svc_reg, 0, sizeof(apic->int_svc_reg));
254 memset(apic->int_en_reg, 0xff, sizeof(apic->int_en_reg));
255 memset(apic->trig_mode_reg, 0, sizeof(apic->trig_mode_reg));
257 apic->eoi = 0x00000000;
258 apic->rem_rd_data = 0x00000000;
259 apic->tmr_init_cnt = 0x00000000;
260 apic->tmr_cur_cnt = 0x00000000;
262 apic->lapic_id.val = id;
264 apic->ipi_state = INIT_ST;
266 // The P6 has 6 LVT entries, so we set the value to (6-1)...
267 apic->apic_ver.val = 0x80050010;
269 apic->task_prio.val = 0x00000000;
270 apic->arb_prio.val = 0x00000000;
271 apic->proc_prio.val = 0x00000000;
272 apic->log_dst.val = 0x00000000;
273 apic->dst_fmt.val = 0xffffffff;
274 apic->spurious_int.val = 0x000000ff;
275 apic->err_status.val = 0x00000000;
276 apic->int_cmd.val = 0x0000000000000000LL;
277 apic->tmr_vec_tbl.val = 0x00010000;
278 apic->therm_loc_vec_tbl.val = 0x00010000;
279 apic->perf_ctr_loc_vec_tbl.val = 0x00010000;
280 apic->lint0_vec_tbl.val = 0x00010000;
281 apic->lint1_vec_tbl.val = 0x00010000;
282 apic->err_vec_tbl.val = 0x00010000;
283 apic->tmr_div_cfg.val = 0x00000000;
284 //apic->ext_apic_feature.val = 0x00000007;
285 apic->ext_apic_feature.val = 0x00040007;
286 apic->ext_apic_ctrl.val = 0x00000000;
287 apic->spec_eoi.val = 0x00000000;
289 v3_lock_init(&(apic->lock));
295 static int read_apic_msr(struct guest_info * core, uint_t msr, v3_msr_t * dst, void * priv_data) {
296 struct apic_dev_state * apic_dev = (struct apic_dev_state *)priv_data;
297 struct apic_state * apic = &(apic_dev->apics[core->cpu_id]);
299 PrintDebug("apic %u: core %u: MSR read\n", apic->lapic_id.val, core->cpu_id);
301 dst->value = apic->base_addr;
302 v3_unlock(apic->lock);
307 static int write_apic_msr(struct guest_info * core, uint_t msr, v3_msr_t src, void * priv_data) {
308 struct apic_dev_state * apic_dev = (struct apic_dev_state *)priv_data;
309 struct apic_state * apic = &(apic_dev->apics[core->cpu_id]);
310 struct v3_mem_region * old_reg = v3_get_mem_region(core->vm_info, core->cpu_id, apic->base_addr);
313 PrintDebug("apic %u: core %u: MSR write\n", apic->lapic_id.val, core->cpu_id);
315 if (old_reg == NULL) {
317 PrintError("apic %u: core %u: APIC Base address region does not exit...\n",
318 apic->lapic_id.val, core->cpu_id);
324 v3_delete_mem_region(core->vm_info, old_reg);
326 apic->base_addr = src.value;
328 if (v3_hook_full_mem(core->vm_info, core->cpu_id, apic->base_addr,
329 apic->base_addr + PAGE_SIZE_4KB,
330 apic_read, apic_write, apic_dev) == -1) {
331 PrintError("apic %u: core %u: Could not hook new APIC Base address\n",
332 apic->lapic_id.val, core->cpu_id);
333 v3_unlock(apic->lock);
337 v3_unlock(apic->lock);
342 // irq_num is the bit offset into a 256 bit buffer...
343 static int activate_apic_irq(struct apic_state * apic, uint32_t irq_num) {
344 int major_offset = (irq_num & ~0x00000007) >> 3;
345 int minor_offset = irq_num & 0x00000007;
346 uint8_t * req_location = apic->int_req_reg + major_offset;
347 uint8_t * en_location = apic->int_en_reg + major_offset;
348 uint8_t flag = 0x1 << minor_offset;
353 PrintError("apic %u: core %d: Attempting to raise an invalid interrupt: %d\n",
354 apic->lapic_id.val, apic->core->cpu_id, irq_num);
359 PrintDebug("apic %u: core %d: Raising APIC IRQ %d\n", apic->lapic_id.val, apic->core->cpu_id, irq_num);
361 if (*req_location & flag) {
362 PrintDebug("Interrupt %d coallescing\n", irq_num);
365 if (*en_location & flag) {
366 *req_location |= flag;
368 PrintDebug("apic %u: core %d: Interrupt not enabled... %.2x\n",
369 apic->lapic_id.val, apic->core->cpu_id,*en_location);
378 static int get_highest_isr(struct apic_state * apic) {
381 // We iterate backwards to find the highest priority
382 for (i = 31; i >= 0; i--) {
383 uint8_t * svc_major = apic->int_svc_reg + i;
385 if ((*svc_major) & 0xff) {
386 for (j = 7; j >= 0; j--) {
387 uint8_t flag = 0x1 << j;
388 if ((*svc_major) & flag) {
389 return ((i * 8) + j);
400 static int get_highest_irr(struct apic_state * apic) {
403 // We iterate backwards to find the highest priority
404 for (i = 31; i >= 0; i--) {
405 uint8_t * req_major = apic->int_req_reg + i;
407 if ((*req_major) & 0xff) {
408 for (j = 7; j >= 0; j--) {
409 uint8_t flag = 0x1 << j;
410 if ((*req_major) & flag) {
411 return ((i * 8) + j);
423 static int apic_do_eoi(struct apic_state * apic) {
424 int isr_irq = get_highest_isr(apic);
427 int major_offset = (isr_irq & ~0x00000007) >> 3;
428 int minor_offset = isr_irq & 0x00000007;
429 uint8_t flag = 0x1 << minor_offset;
430 uint8_t * svc_location = apic->int_svc_reg + major_offset;
432 PrintDebug("apic %u: core ?: Received APIC EOI for IRQ %d\n", apic->lapic_id.val,isr_irq);
434 *svc_location &= ~flag;
436 #ifdef CONFIG_CRAY_XT
438 if ((isr_irq == 238) ||
440 PrintDebug("apic %u: core ?: Acking IRQ %d\n", apic->lapic_id.val,isr_irq);
443 if (isr_irq == 238) {
448 //PrintError("apic %u: core ?: Spurious EOI...\n",apic->lapic_id.val);
455 static int activate_internal_irq(struct apic_state * apic, apic_irq_type_t int_type) {
456 uint32_t vec_num = 0;
457 uint32_t del_mode = 0;
463 vec_num = apic->tmr_vec_tbl.vec;
464 del_mode = APIC_FIXED_DELIVERY;
465 masked = apic->tmr_vec_tbl.mask;
468 vec_num = apic->therm_loc_vec_tbl.vec;
469 del_mode = apic->therm_loc_vec_tbl.msg_type;
470 masked = apic->therm_loc_vec_tbl.mask;
473 vec_num = apic->perf_ctr_loc_vec_tbl.vec;
474 del_mode = apic->perf_ctr_loc_vec_tbl.msg_type;
475 masked = apic->perf_ctr_loc_vec_tbl.mask;
478 vec_num = apic->lint0_vec_tbl.vec;
479 del_mode = apic->lint0_vec_tbl.msg_type;
480 masked = apic->lint0_vec_tbl.mask;
483 vec_num = apic->lint1_vec_tbl.vec;
484 del_mode = apic->lint1_vec_tbl.msg_type;
485 masked = apic->lint1_vec_tbl.mask;
488 vec_num = apic->err_vec_tbl.vec;
489 del_mode = APIC_FIXED_DELIVERY;
490 masked = apic->err_vec_tbl.mask;
493 PrintError("apic %u: core ?: Invalid APIC interrupt type\n", apic->lapic_id.val);
497 // interrupt is masked, don't send
499 PrintDebug("apic %u: core ?: Inerrupt is masked\n", apic->lapic_id.val);
503 if (del_mode == APIC_FIXED_DELIVERY) {
504 //PrintDebug("Activating internal APIC IRQ %d\n", vec_num);
505 return activate_apic_irq(apic, vec_num);
507 PrintError("apic %u: core ?: Unhandled Delivery Mode\n", apic->lapic_id.val);
514 static inline int should_deliver_cluster_ipi(struct guest_info * dst_core,
515 struct apic_state * dst_apic, uint8_t mda) {
517 if ( ((mda & 0xf0) == (dst_apic->log_dst.dst_log_id & 0xf0)) && // (I am in the cluster and
518 ((mda & 0x0f) & (dst_apic->log_dst.dst_log_id & 0x0f)) ) { // I am in the set)
520 PrintDebug("apic %u core %u: accepting clustered IRQ (mda 0x%x == log_dst 0x%x)\n",
521 dst_apic->lapic_id.val, dst_core->cpu_id, mda,
522 dst_apic->log_dst.dst_log_id);
526 PrintDebug("apic %u core %u: rejecting clustered IRQ (mda 0x%x != log_dst 0x%x)\n",
527 dst_apic->lapic_id.val, dst_core->cpu_id, mda,
528 dst_apic->log_dst.dst_log_id);
533 static inline int should_deliver_flat_ipi(struct guest_info * dst_core,
534 struct apic_state * dst_apic, uint8_t mda) {
536 if (dst_apic->log_dst.dst_log_id & mda) { // I am in the set
538 PrintDebug("apic %u core %u: accepting flat IRQ (mda 0x%x == log_dst 0x%x)\n",
539 dst_apic->lapic_id.val, dst_core->cpu_id, mda,
540 dst_apic->log_dst.dst_log_id);
543 PrintDebug("apic %u core %u: rejecting flat IRQ (mda 0x%x != log_dst 0x%x)\n",
544 dst_apic->lapic_id.val, dst_core->cpu_id, mda,
545 dst_apic->log_dst.dst_log_id);
552 static int should_deliver_ipi(struct guest_info * dst_core,
553 struct apic_state * dst_apic, uint8_t mda) {
556 if (dst_apic->dst_fmt.model == 0xf) {
559 // always deliver broadcast
563 return should_deliver_cluster_ipi(dst_core, dst_apic, mda);
564 } else if (dst_apic->dst_fmt.model == 0x0) {
567 // always deliver broadcast
571 return should_deliver_flat_ipi(dst_core, dst_apic, mda);
573 PrintError("apic %u core %u: invalid destination format register value 0x%x for logical mode delivery.\n",
574 dst_apic->lapic_id.val, dst_core->cpu_id, dst_apic->dst_fmt.model);
580 static int deliver_ipi(struct apic_state * src_apic,
581 struct apic_state * dst_apic,
582 uint32_t vector, uint8_t del_mode) {
584 struct guest_info * dst_core = dst_apic->core;
589 case 1: // lowest priority
590 PrintDebug("delivering IRQ %d to core %u\n", vector, dst_core->cpu_id);
592 activate_apic_irq(dst_apic, vector);
594 if (dst_apic != src_apic) {
595 // Assume core # is same as logical processor for now
596 // TODO FIX THIS FIX THIS
597 // THERE SHOULD BE: guestapicid->virtualapicid map,
598 // cpu_id->logical processor map
599 // host maitains logical proc->phsysical proc
600 PrintDebug(" non-local core, forcing it to exit\n");
602 v3_interrupt_cpu(dst_core->vm_info, dst_core->cpu_id, 0);
608 PrintDebug(" INIT delivery to core %u\n", dst_core->cpu_id);
610 // TODO: any APIC reset on dest core (shouldn't be needed, but not sure...)
613 if (dst_apic->ipi_state != INIT_ST) {
614 PrintError(" Warning: core %u is not in INIT state (mode = %d), ignored\n",
615 dst_core->cpu_id, dst_apic->ipi_state);
616 // Only a warning, since INIT INIT SIPI is common
620 // We transition the target core to SIPI state
621 dst_apic->ipi_state = SIPI; // note: locking should not be needed here
623 // That should be it since the target core should be
624 // waiting in host on this transition
625 // either it's on another core or on a different preemptive thread
626 // in both cases, it will quickly notice this transition
627 // in particular, we should not need to force an exit here
629 PrintDebug(" INIT delivery done\n");
636 if (dst_apic->ipi_state != SIPI) {
637 PrintError(" core %u is not in SIPI state (mode = %d), ignored!\n",
638 dst_core->cpu_id, dst_apic->ipi_state);
642 // Write the RIP, CS, and descriptor
643 // assume the rest is already good to go
645 // vector VV -> rip at 0
647 // This means we start executing at linear address VV000
649 // So the selector needs to be VV00
650 // and the base needs to be VV000
653 dst_core->segments.cs.selector = vector << 8;
654 dst_core->segments.cs.limit = 0xffff;
655 dst_core->segments.cs.base = vector << 12;
657 PrintDebug(" SIPI delivery (0x%x -> 0x%x:0x0) to core %u\n",
658 vector, dst_core->segments.cs.selector, dst_core->cpu_id);
659 // Maybe need to adjust the APIC?
661 // We transition the target core to SIPI state
662 dst_core->core_run_state = CORE_RUNNING; // note: locking should not be needed here
663 dst_apic->ipi_state = STARTED;
665 // As with INIT, we should not need to do anything else
667 PrintDebug(" SIPI delivery done\n");
676 PrintError("IPI %d delivery is unsupported\n", del_mode);
685 static int route_ipi(struct apic_dev_state * apic_dev,
686 struct apic_state * src_apic,
687 struct int_cmd_reg * icr) {
688 struct apic_state * dest_apic = NULL;
690 PrintDebug("route_ipi: src_apic=%p, icr_data=%p\n",
691 src_apic, (void *)(addr_t)icr->val);
694 if ((icr->dst_mode == 0) && (icr->dst >= apic_dev->num_apics)) {
695 PrintError("route_ipi: Attempted send to unregistered apic id=%u\n",
700 dest_apic = &(apic_dev->apics[icr->dst]);
703 PrintDebug("route_ipi: IPI %s %u from apic %p to %s %s %u (icr=0x%llx)\n",
704 deliverymode_str[icr->del_mode],
707 (icr->dst_mode == 0) ? "(physical)" : "(logical)",
708 shorthand_str[icr->dst_shorthand],
713 switch (icr->dst_shorthand) {
715 case 0: // no shorthand
716 if (icr->dst_mode == 0) {
719 if (deliver_ipi(src_apic, dest_apic,
720 icr->vec, icr->del_mode) == -1) {
721 PrintError("Error: Could not deliver IPI\n");
728 uint8_t mda = icr->dst;
730 for (i = 0; i < apic_dev->num_apics; i++) {
731 dest_apic = &(apic_dev->apics[i]);
732 int del_flag = should_deliver_ipi(dest_apic->core, dest_apic, mda);
734 if (del_flag == -1) {
735 PrintError("Error checking delivery mode\n");
737 } else if (del_flag == 1) {
738 if (deliver_ipi(src_apic, dest_apic,
739 icr->vec, icr->del_mode) == -1) {
740 PrintError("Error: Could not deliver IPI\n");
751 if (src_apic == NULL) {
752 PrintError("Sending IPI to self from generic IPI sender\n");
756 if (icr->dst_mode == 0) {
757 if (deliver_ipi(src_apic, src_apic, icr->vec, icr->del_mode) == -1) {
758 PrintError("Could not deliver IPI\n");
763 PrintError("use of logical delivery in self is not yet supported.\n");
769 case 3: { // all and all-but-me
770 // assuming that logical verus physical doesn't matter
771 // although it is odd that both are used
774 for (i = 0; i < apic_dev->num_apics; i++) {
775 dest_apic = &(apic_dev->apics[i]);
777 if ((dest_apic != src_apic) || (icr->dst_shorthand == 2)) {
778 if (deliver_ipi(src_apic, dest_apic, icr->vec, icr->del_mode) == -1) {
779 PrintError("Error: Could not deliver IPI\n");
788 PrintError("Error routing IPI, invalid Mode (%d)\n", icr->dst_shorthand);
798 static int apic_read(struct guest_info * core, addr_t guest_addr, void * dst, uint_t length, void * priv_data) {
799 struct apic_dev_state * apic_dev = (struct apic_dev_state *)(priv_data);
800 struct apic_state * apic = &(apic_dev->apics[core->cpu_id]);
801 addr_t reg_addr = guest_addr - apic->base_addr;
802 struct apic_msr * msr = (struct apic_msr *)&(apic->base_addr_msr.value);
806 PrintDebug("apic %u: core %u: at %p: Read apic address space (%p)\n",
807 apic->lapic_id.val, core->cpu_id, apic, (void *)guest_addr);
809 if (msr->apic_enable == 0) {
810 PrintError("apic %u: core %u: Read from APIC address space with disabled APIC, apic msr=0x%llx\n",
811 apic->lapic_id.val, core->cpu_id, apic->base_addr_msr.value);
817 /* Because "May not be supported" doesn't matter to Linux developers... */
818 /* if (length != 4) { */
819 /* PrintError("Invalid apic read length (%d)\n", length); */
823 switch (reg_addr & ~0x3) {
825 // Well, only an idiot would read from a architectural write only register
827 // PrintError("Attempting to read from write only register\n");
833 val = apic->lapic_id.val;
835 case APIC_VERSION_OFFSET:
836 val = apic->apic_ver.val;
839 val = apic->task_prio.val;
842 val = apic->arb_prio.val;
845 val = apic->proc_prio.val;
847 case REMOTE_READ_OFFSET:
848 val = apic->rem_rd_data;
851 val = apic->log_dst.val;
854 val = apic->dst_fmt.val;
856 case SPURIOUS_INT_VEC_OFFSET:
857 val = apic->spurious_int.val;
860 val = apic->err_status.val;
862 case TMR_LOC_VEC_TBL_OFFSET:
863 val = apic->tmr_vec_tbl.val;
865 case LINT0_VEC_TBL_OFFSET:
866 val = apic->lint0_vec_tbl.val;
868 case LINT1_VEC_TBL_OFFSET:
869 val = apic->lint1_vec_tbl.val;
871 case ERR_VEC_TBL_OFFSET:
872 val = apic->err_vec_tbl.val;
874 case TMR_INIT_CNT_OFFSET:
875 val = apic->tmr_init_cnt;
877 case TMR_DIV_CFG_OFFSET:
878 val = apic->tmr_div_cfg.val;
882 val = *(uint32_t *)(apic->int_en_reg);
885 val = *(uint32_t *)(apic->int_en_reg + 4);
888 val = *(uint32_t *)(apic->int_en_reg + 8);
891 val = *(uint32_t *)(apic->int_en_reg + 12);
894 val = *(uint32_t *)(apic->int_en_reg + 16);
897 val = *(uint32_t *)(apic->int_en_reg + 20);
900 val = *(uint32_t *)(apic->int_en_reg + 24);
903 val = *(uint32_t *)(apic->int_en_reg + 28);
907 val = *(uint32_t *)(apic->int_svc_reg);
910 val = *(uint32_t *)(apic->int_svc_reg + 4);
913 val = *(uint32_t *)(apic->int_svc_reg + 8);
916 val = *(uint32_t *)(apic->int_svc_reg + 12);
919 val = *(uint32_t *)(apic->int_svc_reg + 16);
922 val = *(uint32_t *)(apic->int_svc_reg + 20);
925 val = *(uint32_t *)(apic->int_svc_reg + 24);
928 val = *(uint32_t *)(apic->int_svc_reg + 28);
932 val = *(uint32_t *)(apic->trig_mode_reg);
935 val = *(uint32_t *)(apic->trig_mode_reg + 4);
938 val = *(uint32_t *)(apic->trig_mode_reg + 8);
941 val = *(uint32_t *)(apic->trig_mode_reg + 12);
944 val = *(uint32_t *)(apic->trig_mode_reg + 16);
947 val = *(uint32_t *)(apic->trig_mode_reg + 20);
950 val = *(uint32_t *)(apic->trig_mode_reg + 24);
953 val = *(uint32_t *)(apic->trig_mode_reg + 28);
957 val = *(uint32_t *)(apic->int_req_reg);
960 val = *(uint32_t *)(apic->int_req_reg + 4);
963 val = *(uint32_t *)(apic->int_req_reg + 8);
966 val = *(uint32_t *)(apic->int_req_reg + 12);
969 val = *(uint32_t *)(apic->int_req_reg + 16);
972 val = *(uint32_t *)(apic->int_req_reg + 20);
975 val = *(uint32_t *)(apic->int_req_reg + 24);
978 val = *(uint32_t *)(apic->int_req_reg + 28);
980 case TMR_CUR_CNT_OFFSET:
981 val = apic->tmr_cur_cnt;
984 // We are not going to implement these....
985 case THERM_LOC_VEC_TBL_OFFSET:
986 val = apic->therm_loc_vec_tbl.val;
988 case PERF_CTR_LOC_VEC_TBL_OFFSET:
989 val = apic->perf_ctr_loc_vec_tbl.val;
995 case INT_CMD_LO_OFFSET:
996 val = apic->int_cmd.lo;
998 case INT_CMD_HI_OFFSET:
999 val = apic->int_cmd.hi;
1002 // handle current timer count
1004 // Unhandled Registers
1005 case EXT_INT_LOC_VEC_TBL_OFFSET0:
1006 val = apic->ext_intr_vec_tbl[0].val;
1008 case EXT_INT_LOC_VEC_TBL_OFFSET1:
1009 val = apic->ext_intr_vec_tbl[1].val;
1011 case EXT_INT_LOC_VEC_TBL_OFFSET2:
1012 val = apic->ext_intr_vec_tbl[2].val;
1014 case EXT_INT_LOC_VEC_TBL_OFFSET3:
1015 val = apic->ext_intr_vec_tbl[3].val;
1019 case EXT_APIC_FEATURE_OFFSET:
1020 case EXT_APIC_CMD_OFFSET:
1024 PrintError("apic %u: core %u: Read from Unhandled APIC Register: %x (getting zero)\n",
1025 apic->lapic_id.val, core->cpu_id, (uint32_t)reg_addr);
1031 uint_t byte_addr = reg_addr & 0x3;
1032 uint8_t * val_ptr = (uint8_t *)dst;
1034 *val_ptr = *(((uint8_t *)&val) + byte_addr);
1036 } else if ((length == 2) &&
1037 ((reg_addr & 0x3) == 0x3)) {
1038 uint_t byte_addr = reg_addr & 0x3;
1039 uint16_t * val_ptr = (uint16_t *)dst;
1040 *val_ptr = *(((uint16_t *)&val) + byte_addr);
1042 } else if (length == 4) {
1043 uint32_t * val_ptr = (uint32_t *)dst;
1047 PrintError("apic %u: core %u: Invalid apic read length (%d)\n",
1048 apic->lapic_id.val, core->cpu_id, length);
1052 PrintDebug("apic %u: core %u: Read finished (val=%x)\n",
1053 apic->lapic_id.val, core->cpu_id, *(uint32_t *)dst);
1062 static int apic_write(struct guest_info * core, addr_t guest_addr, void * src, uint_t length, void * priv_data) {
1063 struct apic_dev_state * apic_dev = (struct apic_dev_state *)(priv_data);
1064 struct apic_state * apic = &(apic_dev->apics[core->cpu_id]);
1065 addr_t reg_addr = guest_addr - apic->base_addr;
1066 struct apic_msr * msr = (struct apic_msr *)&(apic->base_addr_msr.value);
1067 uint32_t op_val = *(uint32_t *)src;
1069 PrintDebug("apic %u: core %u: at %p and priv_data is at %p\n",
1070 apic->lapic_id.val, core->cpu_id, apic, priv_data);
1072 PrintDebug("Write to address space (%p) (val=%x)\n",
1073 (void *)guest_addr, *(uint32_t *)src);
1075 if (msr->apic_enable == 0) {
1076 PrintError("apic %u: core %u: Write to APIC address space with disabled APIC, apic msr=0x%llx\n",
1077 apic->lapic_id.val, core->cpu_id, apic->base_addr_msr.value);
1083 PrintError("apic %u: core %u: Invalid apic write length (%d)\n",
1084 apic->lapic_id.val, length, core->cpu_id);
1089 case REMOTE_READ_OFFSET:
1090 case APIC_VERSION_OFFSET:
1117 case EXT_APIC_FEATURE_OFFSET:
1119 PrintError("apic %u: core %u: Attempting to write to read only register %p (error)\n",
1120 apic->lapic_id.val, core->cpu_id, (void *)reg_addr);
1126 case APIC_ID_OFFSET:
1127 PrintDebug("apic %u: core %u: my id is being changed to %u\n",
1128 apic->lapic_id.val, core->cpu_id, op_val);
1130 apic->lapic_id.val = op_val;
1133 apic->task_prio.val = op_val;
1136 PrintDebug("apic %u: core %u: setting log_dst.val to 0x%x\n",
1137 apic->lapic_id.val, core->cpu_id, op_val);
1138 apic->log_dst.val = op_val;
1141 apic->dst_fmt.val = op_val;
1143 case SPURIOUS_INT_VEC_OFFSET:
1144 apic->spurious_int.val = op_val;
1147 apic->err_status.val = op_val;
1149 case TMR_LOC_VEC_TBL_OFFSET:
1150 apic->tmr_vec_tbl.val = op_val;
1152 case THERM_LOC_VEC_TBL_OFFSET:
1153 apic->therm_loc_vec_tbl.val = op_val;
1155 case PERF_CTR_LOC_VEC_TBL_OFFSET:
1156 apic->perf_ctr_loc_vec_tbl.val = op_val;
1158 case LINT0_VEC_TBL_OFFSET:
1159 apic->lint0_vec_tbl.val = op_val;
1161 case LINT1_VEC_TBL_OFFSET:
1162 apic->lint1_vec_tbl.val = op_val;
1164 case ERR_VEC_TBL_OFFSET:
1165 apic->err_vec_tbl.val = op_val;
1167 case TMR_INIT_CNT_OFFSET:
1168 apic->tmr_init_cnt = op_val;
1169 apic->tmr_cur_cnt = op_val;
1171 case TMR_CUR_CNT_OFFSET:
1172 apic->tmr_cur_cnt = op_val;
1174 case TMR_DIV_CFG_OFFSET:
1175 apic->tmr_div_cfg.val = op_val;
1179 // Enable mask (256 bits)
1181 *(uint32_t *)(apic->int_en_reg) = op_val;
1184 *(uint32_t *)(apic->int_en_reg + 4) = op_val;
1187 *(uint32_t *)(apic->int_en_reg + 8) = op_val;
1190 *(uint32_t *)(apic->int_en_reg + 12) = op_val;
1193 *(uint32_t *)(apic->int_en_reg + 16) = op_val;
1196 *(uint32_t *)(apic->int_en_reg + 20) = op_val;
1199 *(uint32_t *)(apic->int_en_reg + 24) = op_val;
1202 *(uint32_t *)(apic->int_en_reg + 28) = op_val;
1205 case EXT_INT_LOC_VEC_TBL_OFFSET0:
1206 apic->ext_intr_vec_tbl[0].val = op_val;
1208 case EXT_INT_LOC_VEC_TBL_OFFSET1:
1209 apic->ext_intr_vec_tbl[1].val = op_val;
1211 case EXT_INT_LOC_VEC_TBL_OFFSET2:
1212 apic->ext_intr_vec_tbl[2].val = op_val;
1214 case EXT_INT_LOC_VEC_TBL_OFFSET3:
1215 apic->ext_intr_vec_tbl[3].val = op_val;
1225 case INT_CMD_LO_OFFSET:
1226 apic->int_cmd.lo = op_val;
1228 PrintDebug("apic %u: core %u: sending cmd 0x%llx to apic %u\n",
1229 apic->lapic_id.val, core->cpu_id,
1230 apic->int_cmd.val, apic->int_cmd.dst);
1232 if (route_ipi(apic_dev, apic, &(apic->int_cmd)) == -1) {
1233 PrintError("IPI Routing failure\n");
1239 case INT_CMD_HI_OFFSET:
1240 apic->int_cmd.hi = op_val;
1244 // Unhandled Registers
1245 case EXT_APIC_CMD_OFFSET:
1248 PrintError("apic %u: core %u: Write to Unhandled APIC Register: %x (ignored)\n",
1249 apic->lapic_id.val, core->cpu_id, (uint32_t)reg_addr);
1254 PrintDebug("apic %u: core %u: Write finished\n", apic->lapic_id.val, core->cpu_id);
1261 /* Interrupt Controller Functions */
1263 // returns 1 if an interrupt is pending, 0 otherwise
1264 static int apic_intr_pending(struct guest_info * core, void * private_data) {
1265 struct apic_dev_state * apic_dev = (struct apic_dev_state *)(private_data);
1266 struct apic_state * apic = &(apic_dev->apics[core->cpu_id]);
1267 int req_irq = get_highest_irr(apic);
1268 int svc_irq = get_highest_isr(apic);
1270 // PrintDebug("apic %u: core %u: req_irq=%d, svc_irq=%d\n",apic->lapic_id.val,info->cpu_id,req_irq,svc_irq);
1272 if ((req_irq >= 0) &&
1273 (req_irq > svc_irq)) {
1280 static int apic_get_intr_number(struct guest_info * core, void * private_data) {
1281 struct apic_dev_state * apic_dev = (struct apic_dev_state *)(private_data);
1282 struct apic_state * apic = &(apic_dev->apics[core->cpu_id]);
1283 int req_irq = get_highest_irr(apic);
1284 int svc_irq = get_highest_isr(apic);
1286 if (svc_irq == -1) {
1288 } else if (svc_irq < req_irq) {
1296 int v3_apic_send_ipi(struct v3_vm_info * vm, struct vm_device * dev,
1297 struct v3_gen_ipi * ipi) {
1298 struct apic_dev_state * apic_dev = (struct apic_dev_state *)(dev->private_data);
1299 struct int_cmd_reg tmp_icr;
1301 // zero out all the fields
1305 tmp_icr.vec = ipi->vector;
1306 tmp_icr.del_mode = ipi->mode;
1307 tmp_icr.dst_mode = ipi->logical;
1308 tmp_icr.trig_mode = ipi->trigger_mode;
1309 tmp_icr.dst_shorthand = ipi->dst_shorthand;
1310 tmp_icr.dst = ipi->dst;
1313 return route_ipi(apic_dev, NULL, &tmp_icr);
1317 int v3_apic_raise_intr(struct v3_vm_info * vm, struct vm_device * dev,
1318 uint32_t irq, uint32_t dst) {
1319 struct apic_dev_state * apic_dev = (struct apic_dev_state *)(dev->private_data);
1320 struct apic_state * apic = &(apic_dev->apics[dst]);
1322 PrintDebug("apic %u core ?: raising interrupt IRQ %u (dst = %u).\n", apic->lapic_id.val, irq, dst);
1324 activate_apic_irq(apic, irq);
1326 if (V3_Get_CPU() != dst) {
1327 v3_interrupt_cpu(vm, dst, 0);
1335 static int apic_begin_irq(struct guest_info * core, void * private_data, int irq) {
1336 struct apic_dev_state * apic_dev = (struct apic_dev_state *)(private_data);
1337 struct apic_state * apic = &(apic_dev->apics[core->cpu_id]);
1338 int major_offset = (irq & ~0x00000007) >> 3;
1339 int minor_offset = irq & 0x00000007;
1340 uint8_t * req_location = apic->int_req_reg + major_offset;
1341 uint8_t * svc_location = apic->int_svc_reg + major_offset;
1342 uint8_t flag = 0x01 << minor_offset;
1344 if (*req_location & flag) {
1345 // we will only pay attention to a begin irq if we
1346 // know that we initiated it!
1347 *svc_location |= flag;
1348 *req_location &= ~flag;
1351 //PrintDebug("apic %u: core %u: begin irq for %d ignored since I don't own it\n",
1352 // apic->lapic_id.val, core->cpu_id, irq);
1361 /* Timer Functions */
1362 static void apic_update_time(struct guest_info * core,
1363 uint64_t cpu_cycles, uint64_t cpu_freq,
1365 struct apic_dev_state * apic_dev = (struct apic_dev_state *)(priv_data);
1366 struct apic_state * apic = &(apic_dev->apics[core->cpu_id]);
1368 // The 32 bit GCC runtime is a pile of shit
1370 uint64_t tmr_ticks = 0;
1372 uint32_t tmr_ticks = 0;
1375 uint8_t tmr_div = *(uint8_t *)&(apic->tmr_div_cfg.val);
1376 uint_t shift_num = 0;
1379 // Check whether this is true:
1380 // -> If the Init count is zero then the timer is disabled
1381 // and doesn't just blitz interrupts to the CPU
1382 if ((apic->tmr_init_cnt == 0) ||
1383 ( (apic->tmr_vec_tbl.tmr_mode == APIC_TMR_ONESHOT) &&
1384 (apic->tmr_cur_cnt == 0))) {
1385 //PrintDebug("apic %u: core %u: APIC timer not yet initialized\n",apic->lapic_id.val,info->cpu_id);
1403 case APIC_TMR_DIV16:
1406 case APIC_TMR_DIV32:
1409 case APIC_TMR_DIV64:
1412 case APIC_TMR_DIV128:
1416 PrintError("apic %u: core %u: Invalid Timer Divider configuration\n",
1417 apic->lapic_id.val, core->cpu_id);
1421 tmr_ticks = cpu_cycles >> shift_num;
1422 // PrintDebug("Timer Ticks: %p\n", (void *)tmr_ticks);
1424 if (tmr_ticks < apic->tmr_cur_cnt) {
1425 apic->tmr_cur_cnt -= tmr_ticks;
1427 tmr_ticks -= apic->tmr_cur_cnt;
1428 apic->tmr_cur_cnt = 0;
1431 PrintDebug("apic %u: core %u: Raising APIC Timer interrupt (periodic=%d) (icnt=%d) (div=%d)\n",
1432 apic->lapic_id.val, core->cpu_id,
1433 apic->tmr_vec_tbl.tmr_mode, apic->tmr_init_cnt, shift_num);
1435 if (apic_intr_pending(core, priv_data)) {
1436 PrintDebug("apic %u: core %u: Overriding pending IRQ %d\n",
1437 apic->lapic_id.val, core->cpu_id,
1438 apic_get_intr_number(core, priv_data));
1441 if (activate_internal_irq(apic, APIC_TMR_INT) == -1) {
1442 PrintError("apic %u: core %u: Could not raise Timer interrupt\n",
1443 apic->lapic_id.val, core->cpu_id);
1446 if (apic->tmr_vec_tbl.tmr_mode == APIC_TMR_PERIODIC) {
1447 tmr_ticks = tmr_ticks % apic->tmr_init_cnt;
1448 apic->tmr_cur_cnt = apic->tmr_init_cnt - tmr_ticks;
1456 static struct intr_ctrl_ops intr_ops = {
1457 .intr_pending = apic_intr_pending,
1458 .get_intr_number = apic_get_intr_number,
1459 .begin_irq = apic_begin_irq,
1463 static struct vm_timer_ops timer_ops = {
1464 .update_timer = apic_update_time,
1470 static int apic_free(struct vm_device * dev) {
1472 /* TODO: This should crosscall to force an unhook on each CPU */
1474 // struct apic_state * apic = (struct apic_state *)dev->private_data;
1476 v3_unhook_msr(dev->vm, BASE_ADDR_MSR);
1482 static struct v3_device_ops dev_ops = {
1493 static int apic_init(struct v3_vm_info * vm, v3_cfg_tree_t * cfg) {
1494 char * dev_id = v3_cfg_val(cfg, "ID");
1495 struct apic_dev_state * apic_dev = NULL;
1498 PrintDebug("apic: creating an APIC for each core\n");
1500 apic_dev = (struct apic_dev_state *)V3_Malloc(sizeof(struct apic_dev_state) +
1501 sizeof(struct apic_state) * vm->num_cores);
1503 apic_dev->num_apics = vm->num_cores;
1505 struct vm_device * dev = v3_allocate_device(dev_id, &dev_ops, apic_dev);
1507 if (v3_attach_device(vm, dev) == -1) {
1508 PrintError("apic: Could not attach device %s\n", dev_id);
1513 for (i = 0; i < vm->num_cores; i++) {
1514 struct apic_state * apic = &(apic_dev->apics[i]);
1515 struct guest_info * core = &(vm->cores[i]);
1519 init_apic_state(apic, i);
1521 v3_register_intr_controller(core, &intr_ops, apic_dev);
1523 v3_add_timer(core, &timer_ops, apic_dev);
1525 v3_hook_full_mem(vm, core->cpu_id, apic->base_addr, apic->base_addr + PAGE_SIZE_4KB, apic_read, apic_write, apic_dev);
1527 PrintDebug("apic %u: (setup device): done, my id is %u\n", i, apic->lapic_id.val);
1530 #ifdef CONFIG_DEBUG_APIC
1531 for (i = 0; i < vm->num_cores; i++) {
1532 struct apic_state * apic = &(apic_dev->apics[i]);
1533 PrintDebug("apic: sanity check: apic %u (at %p) has id %u and msr value %llx\n",
1534 i, apic, apic->lapic_id.val, apic->base_addr_msr.value);
1539 PrintDebug("apic: priv_data is at %p\n", apic_dev);
1541 v3_hook_msr(vm, BASE_ADDR_MSR, read_apic_msr, write_apic_msr, apic_dev);
1548 device_register("LAPIC", apic_init)