2 * This file is part of the Palacios Virtual Machine Monitor developed
3 * by the V3VEE Project with funding from the United States National
4 * Science Foundation and the Department of Energy.
6 * The V3VEE Project is a joint project between Northwestern University
7 * and the University of New Mexico. You can find out more at
10 * Copyright (c) 2008, Jack Lange <jarusl@cs.northwestern.edu>
11 * Copyright (c) 2008, The V3VEE Project <http://www.v3vee.org>
12 * All rights reserved.
14 * Author: Jack Lange <jarusl@cs.northwestern.edu>
16 * This is free software. You are permitted to use,
17 * redistribute, and modify it as specified in the file "V3VEE_LICENSE".
21 #include <devices/apic.h>
22 #include <devices/apic_regs.h>
23 #include <palacios/vmm.h>
24 #include <palacios/vmm_msr.h>
25 #include <palacios/vmm_sprintf.h>
26 #include <palacios/vm_guest.h>
27 #include <palacios/vmm_types.h>
30 #ifndef CONFIG_DEBUG_APIC
32 #define PrintDebug(fmt, args...)
35 #ifdef CONFIG_DEBUG_APIC
36 static char * shorthand_str[] = {
43 static char * deliverymode_str[] = {
55 typedef enum { APIC_TMR_INT, APIC_THERM_INT, APIC_PERF_INT,
56 APIC_LINT0_INT, APIC_LINT1_INT, APIC_ERR_INT } apic_irq_type_t;
58 #define APIC_FIXED_DELIVERY 0x0
59 #define APIC_SMI_DELIVERY 0x2
60 #define APIC_NMI_DELIVERY 0x4
61 #define APIC_INIT_DELIVERY 0x5
62 #define APIC_EXTINT_DELIVERY 0x7
65 #define BASE_ADDR_MSR 0x0000001B
66 #define DEFAULT_BASE_ADDR 0xfee00000
68 #define APIC_ID_OFFSET 0x020
69 #define APIC_VERSION_OFFSET 0x030
70 #define TPR_OFFSET 0x080
71 #define APR_OFFSET 0x090
72 #define PPR_OFFSET 0x0a0
73 #define EOI_OFFSET 0x0b0
74 #define REMOTE_READ_OFFSET 0x0c0
75 #define LDR_OFFSET 0x0d0
76 #define DFR_OFFSET 0x0e0
77 #define SPURIOUS_INT_VEC_OFFSET 0x0f0
79 #define ISR_OFFSET0 0x100 // 0x100 - 0x170
80 #define ISR_OFFSET1 0x110 // 0x100 - 0x170
81 #define ISR_OFFSET2 0x120 // 0x100 - 0x170
82 #define ISR_OFFSET3 0x130 // 0x100 - 0x170
83 #define ISR_OFFSET4 0x140 // 0x100 - 0x170
84 #define ISR_OFFSET5 0x150 // 0x100 - 0x170
85 #define ISR_OFFSET6 0x160 // 0x100 - 0x170
86 #define ISR_OFFSET7 0x170 // 0x100 - 0x170
88 #define TRIG_OFFSET0 0x180 // 0x180 - 0x1f0
89 #define TRIG_OFFSET1 0x190 // 0x180 - 0x1f0
90 #define TRIG_OFFSET2 0x1a0 // 0x180 - 0x1f0
91 #define TRIG_OFFSET3 0x1b0 // 0x180 - 0x1f0
92 #define TRIG_OFFSET4 0x1c0 // 0x180 - 0x1f0
93 #define TRIG_OFFSET5 0x1d0 // 0x180 - 0x1f0
94 #define TRIG_OFFSET6 0x1e0 // 0x180 - 0x1f0
95 #define TRIG_OFFSET7 0x1f0 // 0x180 - 0x1f0
98 #define IRR_OFFSET0 0x200 // 0x200 - 0x270
99 #define IRR_OFFSET1 0x210 // 0x200 - 0x270
100 #define IRR_OFFSET2 0x220 // 0x200 - 0x270
101 #define IRR_OFFSET3 0x230 // 0x200 - 0x270
102 #define IRR_OFFSET4 0x240 // 0x200 - 0x270
103 #define IRR_OFFSET5 0x250 // 0x200 - 0x270
104 #define IRR_OFFSET6 0x260 // 0x200 - 0x270
105 #define IRR_OFFSET7 0x270 // 0x200 - 0x270
108 #define ESR_OFFSET 0x280
109 #define INT_CMD_LO_OFFSET 0x300
110 #define INT_CMD_HI_OFFSET 0x310
111 #define TMR_LOC_VEC_TBL_OFFSET 0x320
112 #define THERM_LOC_VEC_TBL_OFFSET 0x330
113 #define PERF_CTR_LOC_VEC_TBL_OFFSET 0x340
114 #define LINT0_VEC_TBL_OFFSET 0x350
115 #define LINT1_VEC_TBL_OFFSET 0x360
116 #define ERR_VEC_TBL_OFFSET 0x370
117 #define TMR_INIT_CNT_OFFSET 0x380
118 #define TMR_CUR_CNT_OFFSET 0x390
119 #define TMR_DIV_CFG_OFFSET 0x3e0
120 #define EXT_APIC_FEATURE_OFFSET 0x400
121 #define EXT_APIC_CMD_OFFSET 0x410
122 #define SEOI_OFFSET 0x420
124 #define IER_OFFSET0 0x480 // 0x480 - 0x4f0
125 #define IER_OFFSET1 0x490 // 0x480 - 0x4f0
126 #define IER_OFFSET2 0x4a0 // 0x480 - 0x4f0
127 #define IER_OFFSET3 0x4b0 // 0x480 - 0x4f0
128 #define IER_OFFSET4 0x4c0 // 0x480 - 0x4f0
129 #define IER_OFFSET5 0x4d0 // 0x480 - 0x4f0
130 #define IER_OFFSET6 0x4e0 // 0x480 - 0x4f0
131 #define IER_OFFSET7 0x4f0 // 0x480 - 0x4f0
133 #define EXT_INT_LOC_VEC_TBL_OFFSET0 0x500 // 0x500 - 0x530
134 #define EXT_INT_LOC_VEC_TBL_OFFSET1 0x510 // 0x500 - 0x530
135 #define EXT_INT_LOC_VEC_TBL_OFFSET2 0x520 // 0x500 - 0x530
136 #define EXT_INT_LOC_VEC_TBL_OFFSET3 0x530 // 0x500 - 0x530
143 uint8_t bootstrap_cpu : 1;
145 uint8_t apic_enable : 1;
146 uint64_t base_addr : 40;
148 } __attribute__((packed));
149 } __attribute__((packed));
150 } __attribute__((packed));
154 typedef enum {INIT_ST,
156 STARTED} ipi_state_t;
158 struct apic_dev_state;
164 struct apic_msr base_addr_msr;
167 /* memory map registers */
169 struct lapic_id_reg lapic_id;
170 struct apic_ver_reg apic_ver;
171 struct ext_apic_ctrl_reg ext_apic_ctrl;
172 struct local_vec_tbl_reg local_vec_tbl;
173 struct tmr_vec_tbl_reg tmr_vec_tbl;
174 struct tmr_div_cfg_reg tmr_div_cfg;
175 struct lint_vec_tbl_reg lint0_vec_tbl;
176 struct lint_vec_tbl_reg lint1_vec_tbl;
177 struct perf_ctr_loc_vec_tbl_reg perf_ctr_loc_vec_tbl;
178 struct therm_loc_vec_tbl_reg therm_loc_vec_tbl;
179 struct err_vec_tbl_reg err_vec_tbl;
180 struct err_status_reg err_status;
181 struct spurious_int_reg spurious_int;
182 struct int_cmd_reg int_cmd;
183 struct log_dst_reg log_dst;
184 struct dst_fmt_reg dst_fmt;
185 struct arb_prio_reg arb_prio;
186 struct task_prio_reg task_prio;
187 struct proc_prio_reg proc_prio;
188 struct ext_apic_feature_reg ext_apic_feature;
189 struct spec_eoi_reg spec_eoi;
192 uint32_t tmr_cur_cnt;
193 uint32_t tmr_init_cnt;
196 struct local_vec_tbl_reg ext_intr_vec_tbl[4];
198 uint32_t rem_rd_data;
201 ipi_state_t ipi_state;
203 uint8_t int_req_reg[32];
204 uint8_t int_svc_reg[32];
205 uint8_t int_en_reg[32];
206 uint8_t trig_mode_reg[32];
208 struct guest_info * core;
210 void * controller_handle;
212 struct v3_timer * timer;
222 struct apic_dev_state {
225 struct apic_state apics[0];
226 } __attribute__((packed));
232 static int apic_read(struct guest_info * core, addr_t guest_addr, void * dst, uint_t length, void * priv_data);
233 static int apic_write(struct guest_info * core, addr_t guest_addr, void * src, uint_t length, void * priv_data);
235 static void init_apic_state(struct apic_state * apic, uint32_t id) {
236 apic->base_addr = DEFAULT_BASE_ADDR;
239 // boot processor, enabled
240 apic->base_addr_msr.value = 0x0000000000000900LL;
242 // ap processor, enabled
243 apic->base_addr_msr.value = 0x0000000000000800LL;
246 // same base address regardless of ap or main
247 apic->base_addr_msr.value |= ((uint64_t)DEFAULT_BASE_ADDR);
249 PrintDebug("apic %u: (init_apic_state): msr=0x%llx\n",id, apic->base_addr_msr.value);
251 PrintDebug("apic %u: (init_apic_state): Sizeof Interrupt Request Register %d, should be 32\n",
252 id, (uint_t)sizeof(apic->int_req_reg));
254 memset(apic->int_req_reg, 0, sizeof(apic->int_req_reg));
255 memset(apic->int_svc_reg, 0, sizeof(apic->int_svc_reg));
256 memset(apic->int_en_reg, 0xff, sizeof(apic->int_en_reg));
257 memset(apic->trig_mode_reg, 0, sizeof(apic->trig_mode_reg));
259 apic->eoi = 0x00000000;
260 apic->rem_rd_data = 0x00000000;
261 apic->tmr_init_cnt = 0x00000000;
262 apic->tmr_cur_cnt = 0x00000000;
264 apic->lapic_id.val = id;
266 apic->ipi_state = INIT_ST;
268 // The P6 has 6 LVT entries, so we set the value to (6-1)...
269 apic->apic_ver.val = 0x80050010;
271 apic->task_prio.val = 0x00000000;
272 apic->arb_prio.val = 0x00000000;
273 apic->proc_prio.val = 0x00000000;
274 apic->log_dst.val = 0x00000000;
275 apic->dst_fmt.val = 0xffffffff;
276 apic->spurious_int.val = 0x000000ff;
277 apic->err_status.val = 0x00000000;
278 apic->int_cmd.val = 0x0000000000000000LL;
279 apic->tmr_vec_tbl.val = 0x00010000;
280 apic->therm_loc_vec_tbl.val = 0x00010000;
281 apic->perf_ctr_loc_vec_tbl.val = 0x00010000;
282 apic->lint0_vec_tbl.val = 0x00010000;
283 apic->lint1_vec_tbl.val = 0x00010000;
284 apic->err_vec_tbl.val = 0x00010000;
285 apic->tmr_div_cfg.val = 0x00000000;
286 //apic->ext_apic_feature.val = 0x00000007;
287 apic->ext_apic_feature.val = 0x00040007;
288 apic->ext_apic_ctrl.val = 0x00000000;
289 apic->spec_eoi.val = 0x00000000;
291 v3_lock_init(&(apic->lock));
297 static int read_apic_msr(struct guest_info * core, uint_t msr, v3_msr_t * dst, void * priv_data) {
298 struct apic_dev_state * apic_dev = (struct apic_dev_state *)priv_data;
299 struct apic_state * apic = &(apic_dev->apics[core->cpu_id]);
301 PrintDebug("apic %u: core %u: MSR read\n", apic->lapic_id.val, core->cpu_id);
303 dst->value = apic->base_addr;
304 v3_unlock(apic->lock);
309 static int write_apic_msr(struct guest_info * core, uint_t msr, v3_msr_t src, void * priv_data) {
310 struct apic_dev_state * apic_dev = (struct apic_dev_state *)priv_data;
311 struct apic_state * apic = &(apic_dev->apics[core->cpu_id]);
312 struct v3_mem_region * old_reg = v3_get_mem_region(core->vm_info, core->cpu_id, apic->base_addr);
315 PrintDebug("apic %u: core %u: MSR write\n", apic->lapic_id.val, core->cpu_id);
317 if (old_reg == NULL) {
319 PrintError("apic %u: core %u: APIC Base address region does not exit...\n",
320 apic->lapic_id.val, core->cpu_id);
326 v3_delete_mem_region(core->vm_info, old_reg);
328 apic->base_addr = src.value;
330 if (v3_hook_full_mem(core->vm_info, core->cpu_id, apic->base_addr,
331 apic->base_addr + PAGE_SIZE_4KB,
332 apic_read, apic_write, apic_dev) == -1) {
333 PrintError("apic %u: core %u: Could not hook new APIC Base address\n",
334 apic->lapic_id.val, core->cpu_id);
335 v3_unlock(apic->lock);
339 v3_unlock(apic->lock);
344 // irq_num is the bit offset into a 256 bit buffer...
345 static int activate_apic_irq(struct apic_state * apic, uint32_t irq_num) {
346 int major_offset = (irq_num & ~0x00000007) >> 3;
347 int minor_offset = irq_num & 0x00000007;
348 uint8_t * req_location = apic->int_req_reg + major_offset;
349 uint8_t * en_location = apic->int_en_reg + major_offset;
350 uint8_t flag = 0x1 << minor_offset;
355 PrintError("apic %u: core %d: Attempting to raise an invalid interrupt: %d\n",
356 apic->lapic_id.val, apic->core->cpu_id, irq_num);
361 PrintDebug("apic %u: core %d: Raising APIC IRQ %d\n", apic->lapic_id.val, apic->core->cpu_id, irq_num);
363 if (*req_location & flag) {
364 PrintDebug("Interrupt %d coallescing\n", irq_num);
367 if (*en_location & flag) {
368 *req_location |= flag;
370 PrintDebug("apic %u: core %d: Interrupt not enabled... %.2x\n",
371 apic->lapic_id.val, apic->core->cpu_id,*en_location);
380 static int get_highest_isr(struct apic_state * apic) {
383 // We iterate backwards to find the highest priority
384 for (i = 31; i >= 0; i--) {
385 uint8_t * svc_major = apic->int_svc_reg + i;
387 if ((*svc_major) & 0xff) {
388 for (j = 7; j >= 0; j--) {
389 uint8_t flag = 0x1 << j;
390 if ((*svc_major) & flag) {
391 return ((i * 8) + j);
402 static int get_highest_irr(struct apic_state * apic) {
405 // We iterate backwards to find the highest priority
406 for (i = 31; i >= 0; i--) {
407 uint8_t * req_major = apic->int_req_reg + i;
409 if ((*req_major) & 0xff) {
410 for (j = 7; j >= 0; j--) {
411 uint8_t flag = 0x1 << j;
412 if ((*req_major) & flag) {
413 return ((i * 8) + j);
425 static int apic_do_eoi(struct apic_state * apic) {
426 int isr_irq = get_highest_isr(apic);
429 int major_offset = (isr_irq & ~0x00000007) >> 3;
430 int minor_offset = isr_irq & 0x00000007;
431 uint8_t flag = 0x1 << minor_offset;
432 uint8_t * svc_location = apic->int_svc_reg + major_offset;
434 PrintDebug("apic %u: core ?: Received APIC EOI for IRQ %d\n", apic->lapic_id.val,isr_irq);
436 *svc_location &= ~flag;
438 #ifdef CONFIG_CRAY_XT
440 if ((isr_irq == 238) ||
442 PrintDebug("apic %u: core ?: Acking IRQ %d\n", apic->lapic_id.val,isr_irq);
445 if (isr_irq == 238) {
450 //PrintError("apic %u: core ?: Spurious EOI...\n",apic->lapic_id.val);
457 static int activate_internal_irq(struct apic_state * apic, apic_irq_type_t int_type) {
458 uint32_t vec_num = 0;
459 uint32_t del_mode = 0;
465 vec_num = apic->tmr_vec_tbl.vec;
466 del_mode = APIC_FIXED_DELIVERY;
467 masked = apic->tmr_vec_tbl.mask;
470 vec_num = apic->therm_loc_vec_tbl.vec;
471 del_mode = apic->therm_loc_vec_tbl.msg_type;
472 masked = apic->therm_loc_vec_tbl.mask;
475 vec_num = apic->perf_ctr_loc_vec_tbl.vec;
476 del_mode = apic->perf_ctr_loc_vec_tbl.msg_type;
477 masked = apic->perf_ctr_loc_vec_tbl.mask;
480 vec_num = apic->lint0_vec_tbl.vec;
481 del_mode = apic->lint0_vec_tbl.msg_type;
482 masked = apic->lint0_vec_tbl.mask;
485 vec_num = apic->lint1_vec_tbl.vec;
486 del_mode = apic->lint1_vec_tbl.msg_type;
487 masked = apic->lint1_vec_tbl.mask;
490 vec_num = apic->err_vec_tbl.vec;
491 del_mode = APIC_FIXED_DELIVERY;
492 masked = apic->err_vec_tbl.mask;
495 PrintError("apic %u: core ?: Invalid APIC interrupt type\n", apic->lapic_id.val);
499 // interrupt is masked, don't send
501 PrintDebug("apic %u: core ?: Inerrupt is masked\n", apic->lapic_id.val);
505 if (del_mode == APIC_FIXED_DELIVERY) {
506 //PrintDebug("Activating internal APIC IRQ %d\n", vec_num);
507 return activate_apic_irq(apic, vec_num);
509 PrintError("apic %u: core ?: Unhandled Delivery Mode\n", apic->lapic_id.val);
516 static inline int should_deliver_cluster_ipi(struct guest_info * dst_core,
517 struct apic_state * dst_apic, uint8_t mda) {
519 if ( ((mda & 0xf0) == (dst_apic->log_dst.dst_log_id & 0xf0)) && // (I am in the cluster and
520 ((mda & 0x0f) & (dst_apic->log_dst.dst_log_id & 0x0f)) ) { // I am in the set)
522 PrintDebug("apic %u core %u: accepting clustered IRQ (mda 0x%x == log_dst 0x%x)\n",
523 dst_apic->lapic_id.val, dst_core->cpu_id, mda,
524 dst_apic->log_dst.dst_log_id);
528 PrintDebug("apic %u core %u: rejecting clustered IRQ (mda 0x%x != log_dst 0x%x)\n",
529 dst_apic->lapic_id.val, dst_core->cpu_id, mda,
530 dst_apic->log_dst.dst_log_id);
535 static inline int should_deliver_flat_ipi(struct guest_info * dst_core,
536 struct apic_state * dst_apic, uint8_t mda) {
538 if (dst_apic->log_dst.dst_log_id & mda) { // I am in the set
540 PrintDebug("apic %u core %u: accepting flat IRQ (mda 0x%x == log_dst 0x%x)\n",
541 dst_apic->lapic_id.val, dst_core->cpu_id, mda,
542 dst_apic->log_dst.dst_log_id);
545 PrintDebug("apic %u core %u: rejecting flat IRQ (mda 0x%x != log_dst 0x%x)\n",
546 dst_apic->lapic_id.val, dst_core->cpu_id, mda,
547 dst_apic->log_dst.dst_log_id);
554 static int should_deliver_ipi(struct guest_info * dst_core,
555 struct apic_state * dst_apic, uint8_t mda) {
558 if (dst_apic->dst_fmt.model == 0xf) {
561 // always deliver broadcast
565 return should_deliver_flat_ipi(dst_core, dst_apic, mda);
566 } else if (dst_apic->dst_fmt.model == 0x0) {
569 // always deliver broadcast
573 return should_deliver_cluster_ipi(dst_core, dst_apic, mda);
575 PrintError("apic %u core %u: invalid destination format register value 0x%x for logical mode delivery.\n",
576 dst_apic->lapic_id.val, dst_core->cpu_id, dst_apic->dst_fmt.model);
582 static int deliver_ipi(struct apic_state * src_apic,
583 struct apic_state * dst_apic,
584 uint32_t vector, uint8_t del_mode) {
586 struct guest_info * dst_core = dst_apic->core;
591 case 1: // lowest priority
592 PrintDebug("delivering IRQ %d to core %u\n", vector, dst_core->cpu_id);
594 activate_apic_irq(dst_apic, vector);
596 if (dst_apic != src_apic) {
597 // Assume core # is same as logical processor for now
598 // TODO FIX THIS FIX THIS
599 // THERE SHOULD BE: guestapicid->virtualapicid map,
600 // cpu_id->logical processor map
601 // host maitains logical proc->phsysical proc
602 PrintDebug(" non-local core, forcing it to exit\n");
604 #ifdef CONFIG_MULTITHREAD_OS
605 v3_interrupt_cpu(dst_core->vm_info, dst_core->cpu_id, 0);
614 PrintDebug(" INIT delivery to core %u\n", dst_core->cpu_id);
616 // TODO: any APIC reset on dest core (shouldn't be needed, but not sure...)
619 if (dst_apic->ipi_state != INIT_ST) {
620 PrintError(" Warning: core %u is not in INIT state (mode = %d), ignored\n",
621 dst_core->cpu_id, dst_apic->ipi_state);
622 // Only a warning, since INIT INIT SIPI is common
626 // We transition the target core to SIPI state
627 dst_apic->ipi_state = SIPI; // note: locking should not be needed here
629 // That should be it since the target core should be
630 // waiting in host on this transition
631 // either it's on another core or on a different preemptive thread
632 // in both cases, it will quickly notice this transition
633 // in particular, we should not need to force an exit here
635 PrintDebug(" INIT delivery done\n");
642 if (dst_apic->ipi_state != SIPI) {
643 PrintError(" core %u is not in SIPI state (mode = %d), ignored!\n",
644 dst_core->cpu_id, dst_apic->ipi_state);
648 // Write the RIP, CS, and descriptor
649 // assume the rest is already good to go
651 // vector VV -> rip at 0
653 // This means we start executing at linear address VV000
655 // So the selector needs to be VV00
656 // and the base needs to be VV000
659 dst_core->segments.cs.selector = vector << 8;
660 dst_core->segments.cs.limit = 0xffff;
661 dst_core->segments.cs.base = vector << 12;
663 PrintDebug(" SIPI delivery (0x%x -> 0x%x:0x0) to core %u\n",
664 vector, dst_core->segments.cs.selector, dst_core->cpu_id);
665 // Maybe need to adjust the APIC?
667 // We transition the target core to SIPI state
668 dst_core->core_run_state = CORE_RUNNING; // note: locking should not be needed here
669 dst_apic->ipi_state = STARTED;
671 // As with INIT, we should not need to do anything else
673 PrintDebug(" SIPI delivery done\n");
682 PrintError("IPI %d delivery is unsupported\n", del_mode);
691 static int route_ipi(struct apic_dev_state * apic_dev,
692 struct apic_state * src_apic,
693 struct int_cmd_reg * icr) {
694 struct apic_state * dest_apic = NULL;
696 PrintDebug("route_ipi: src_apic=%p, icr_data=%p\n",
697 src_apic, (void *)(addr_t)icr->val);
700 if ((icr->dst_mode == 0) && (icr->dst >= apic_dev->num_apics)) {
701 PrintError("route_ipi: Attempted send to unregistered apic id=%u\n",
706 dest_apic = &(apic_dev->apics[icr->dst]);
709 PrintDebug("route_ipi: IPI %s %u from apic %p to %s %s %u (icr=0x%llx) (destapic=%p\n",
710 deliverymode_str[icr->del_mode],
713 (icr->dst_mode == 0) ? "(physical)" : "(logical)",
714 shorthand_str[icr->dst_shorthand],
719 switch (icr->dst_shorthand) {
721 case 0: // no shorthand
722 if (icr->dst_mode == 0) {
725 if (deliver_ipi(src_apic, dest_apic,
726 icr->vec, icr->del_mode) == -1) {
727 PrintError("Error: Could not deliver IPI\n");
734 uint8_t mda = icr->dst;
735 for (i = 0; i < apic_dev->num_apics; i++) {
736 dest_apic = &(apic_dev->apics[i]);
737 int del_flag = should_deliver_ipi(dest_apic->core, dest_apic, mda);
739 if (del_flag == -1) {
740 PrintError("Error checking delivery mode\n");
742 } else if (del_flag == 1) {
743 if (deliver_ipi(src_apic, dest_apic,
744 icr->vec, icr->del_mode) == -1) {
745 PrintError("Error: Could not deliver IPI\n");
756 if (src_apic == NULL) {
757 PrintError("Sending IPI to self from generic IPI sender\n");
761 if (icr->dst_mode == 0) {
762 if (deliver_ipi(src_apic, src_apic, icr->vec, icr->del_mode) == -1) {
763 PrintError("Could not deliver IPI\n");
768 PrintError("use of logical delivery in self is not yet supported.\n");
774 case 3: { // all and all-but-me
775 // assuming that logical verus physical doesn't matter
776 // although it is odd that both are used
779 for (i = 0; i < apic_dev->num_apics; i++) {
780 dest_apic = &(apic_dev->apics[i]);
782 if ((dest_apic != src_apic) || (icr->dst_shorthand == 2)) {
783 if (deliver_ipi(src_apic, dest_apic, icr->vec, icr->del_mode) == -1) {
784 PrintError("Error: Could not deliver IPI\n");
793 PrintError("Error routing IPI, invalid Mode (%d)\n", icr->dst_shorthand);
803 static int apic_read(struct guest_info * core, addr_t guest_addr, void * dst, uint_t length, void * priv_data) {
804 struct apic_dev_state * apic_dev = (struct apic_dev_state *)(priv_data);
805 struct apic_state * apic = &(apic_dev->apics[core->cpu_id]);
806 addr_t reg_addr = guest_addr - apic->base_addr;
807 struct apic_msr * msr = (struct apic_msr *)&(apic->base_addr_msr.value);
811 PrintDebug("apic %u: core %u: at %p: Read apic address space (%p)\n",
812 apic->lapic_id.val, core->cpu_id, apic, (void *)guest_addr);
814 if (msr->apic_enable == 0) {
815 PrintError("apic %u: core %u: Read from APIC address space with disabled APIC, apic msr=0x%llx\n",
816 apic->lapic_id.val, core->cpu_id, apic->base_addr_msr.value);
822 /* Because "May not be supported" doesn't matter to Linux developers... */
823 /* if (length != 4) { */
824 /* PrintError("Invalid apic read length (%d)\n", length); */
828 switch (reg_addr & ~0x3) {
830 // Well, only an idiot would read from a architectural write only register
832 // PrintError("Attempting to read from write only register\n");
838 val = apic->lapic_id.val;
840 case APIC_VERSION_OFFSET:
841 val = apic->apic_ver.val;
844 val = apic->task_prio.val;
847 val = apic->arb_prio.val;
850 val = apic->proc_prio.val;
852 case REMOTE_READ_OFFSET:
853 val = apic->rem_rd_data;
856 val = apic->log_dst.val;
859 val = apic->dst_fmt.val;
861 case SPURIOUS_INT_VEC_OFFSET:
862 val = apic->spurious_int.val;
865 val = apic->err_status.val;
867 case TMR_LOC_VEC_TBL_OFFSET:
868 val = apic->tmr_vec_tbl.val;
870 case LINT0_VEC_TBL_OFFSET:
871 val = apic->lint0_vec_tbl.val;
873 case LINT1_VEC_TBL_OFFSET:
874 val = apic->lint1_vec_tbl.val;
876 case ERR_VEC_TBL_OFFSET:
877 val = apic->err_vec_tbl.val;
879 case TMR_INIT_CNT_OFFSET:
880 val = apic->tmr_init_cnt;
882 case TMR_DIV_CFG_OFFSET:
883 val = apic->tmr_div_cfg.val;
887 val = *(uint32_t *)(apic->int_en_reg);
890 val = *(uint32_t *)(apic->int_en_reg + 4);
893 val = *(uint32_t *)(apic->int_en_reg + 8);
896 val = *(uint32_t *)(apic->int_en_reg + 12);
899 val = *(uint32_t *)(apic->int_en_reg + 16);
902 val = *(uint32_t *)(apic->int_en_reg + 20);
905 val = *(uint32_t *)(apic->int_en_reg + 24);
908 val = *(uint32_t *)(apic->int_en_reg + 28);
912 val = *(uint32_t *)(apic->int_svc_reg);
915 val = *(uint32_t *)(apic->int_svc_reg + 4);
918 val = *(uint32_t *)(apic->int_svc_reg + 8);
921 val = *(uint32_t *)(apic->int_svc_reg + 12);
924 val = *(uint32_t *)(apic->int_svc_reg + 16);
927 val = *(uint32_t *)(apic->int_svc_reg + 20);
930 val = *(uint32_t *)(apic->int_svc_reg + 24);
933 val = *(uint32_t *)(apic->int_svc_reg + 28);
937 val = *(uint32_t *)(apic->trig_mode_reg);
940 val = *(uint32_t *)(apic->trig_mode_reg + 4);
943 val = *(uint32_t *)(apic->trig_mode_reg + 8);
946 val = *(uint32_t *)(apic->trig_mode_reg + 12);
949 val = *(uint32_t *)(apic->trig_mode_reg + 16);
952 val = *(uint32_t *)(apic->trig_mode_reg + 20);
955 val = *(uint32_t *)(apic->trig_mode_reg + 24);
958 val = *(uint32_t *)(apic->trig_mode_reg + 28);
962 val = *(uint32_t *)(apic->int_req_reg);
965 val = *(uint32_t *)(apic->int_req_reg + 4);
968 val = *(uint32_t *)(apic->int_req_reg + 8);
971 val = *(uint32_t *)(apic->int_req_reg + 12);
974 val = *(uint32_t *)(apic->int_req_reg + 16);
977 val = *(uint32_t *)(apic->int_req_reg + 20);
980 val = *(uint32_t *)(apic->int_req_reg + 24);
983 val = *(uint32_t *)(apic->int_req_reg + 28);
985 case TMR_CUR_CNT_OFFSET:
986 val = apic->tmr_cur_cnt;
989 // We are not going to implement these....
990 case THERM_LOC_VEC_TBL_OFFSET:
991 val = apic->therm_loc_vec_tbl.val;
993 case PERF_CTR_LOC_VEC_TBL_OFFSET:
994 val = apic->perf_ctr_loc_vec_tbl.val;
1000 case INT_CMD_LO_OFFSET:
1001 val = apic->int_cmd.lo;
1003 case INT_CMD_HI_OFFSET:
1004 val = apic->int_cmd.hi;
1007 // handle current timer count
1009 // Unhandled Registers
1010 case EXT_INT_LOC_VEC_TBL_OFFSET0:
1011 val = apic->ext_intr_vec_tbl[0].val;
1013 case EXT_INT_LOC_VEC_TBL_OFFSET1:
1014 val = apic->ext_intr_vec_tbl[1].val;
1016 case EXT_INT_LOC_VEC_TBL_OFFSET2:
1017 val = apic->ext_intr_vec_tbl[2].val;
1019 case EXT_INT_LOC_VEC_TBL_OFFSET3:
1020 val = apic->ext_intr_vec_tbl[3].val;
1024 case EXT_APIC_FEATURE_OFFSET:
1025 case EXT_APIC_CMD_OFFSET:
1029 PrintError("apic %u: core %u: Read from Unhandled APIC Register: %x (getting zero)\n",
1030 apic->lapic_id.val, core->cpu_id, (uint32_t)reg_addr);
1036 uint_t byte_addr = reg_addr & 0x3;
1037 uint8_t * val_ptr = (uint8_t *)dst;
1039 *val_ptr = *(((uint8_t *)&val) + byte_addr);
1041 } else if ((length == 2) &&
1042 ((reg_addr & 0x3) == 0x3)) {
1043 uint_t byte_addr = reg_addr & 0x3;
1044 uint16_t * val_ptr = (uint16_t *)dst;
1045 *val_ptr = *(((uint16_t *)&val) + byte_addr);
1047 } else if (length == 4) {
1048 uint32_t * val_ptr = (uint32_t *)dst;
1052 PrintError("apic %u: core %u: Invalid apic read length (%d)\n",
1053 apic->lapic_id.val, core->cpu_id, length);
1057 PrintDebug("apic %u: core %u: Read finished (val=%x)\n",
1058 apic->lapic_id.val, core->cpu_id, *(uint32_t *)dst);
1067 static int apic_write(struct guest_info * core, addr_t guest_addr, void * src, uint_t length, void * priv_data) {
1068 struct apic_dev_state * apic_dev = (struct apic_dev_state *)(priv_data);
1069 struct apic_state * apic = &(apic_dev->apics[core->cpu_id]);
1070 addr_t reg_addr = guest_addr - apic->base_addr;
1071 struct apic_msr * msr = (struct apic_msr *)&(apic->base_addr_msr.value);
1072 uint32_t op_val = *(uint32_t *)src;
1074 PrintDebug("apic %u: core %u: at %p and priv_data is at %p\n",
1075 apic->lapic_id.val, core->cpu_id, apic, priv_data);
1077 PrintDebug("apic %u: core %u: write to address space (%p) (val=%x)\n",
1078 apic->lapic_id.val, core->cpu_id, (void *)guest_addr, *(uint32_t *)src);
1080 if (msr->apic_enable == 0) {
1081 PrintError("apic %u: core %u: Write to APIC address space with disabled APIC, apic msr=0x%llx\n",
1082 apic->lapic_id.val, core->cpu_id, apic->base_addr_msr.value);
1088 PrintError("apic %u: core %u: Invalid apic write length (%d)\n",
1089 apic->lapic_id.val, length, core->cpu_id);
1094 case REMOTE_READ_OFFSET:
1095 case APIC_VERSION_OFFSET:
1122 case EXT_APIC_FEATURE_OFFSET:
1124 PrintError("apic %u: core %u: Attempting to write to read only register %p (error)\n",
1125 apic->lapic_id.val, core->cpu_id, (void *)reg_addr);
1131 case APIC_ID_OFFSET:
1132 PrintDebug("apic %u: core %u: my id is being changed to %u\n",
1133 apic->lapic_id.val, core->cpu_id, op_val);
1135 apic->lapic_id.val = op_val;
1138 apic->task_prio.val = op_val;
1141 PrintDebug("apic %u: core %u: setting log_dst.val to 0x%x\n",
1142 apic->lapic_id.val, core->cpu_id, op_val);
1143 apic->log_dst.val = op_val;
1146 apic->dst_fmt.val = op_val;
1148 case SPURIOUS_INT_VEC_OFFSET:
1149 apic->spurious_int.val = op_val;
1152 apic->err_status.val = op_val;
1154 case TMR_LOC_VEC_TBL_OFFSET:
1155 apic->tmr_vec_tbl.val = op_val;
1157 case THERM_LOC_VEC_TBL_OFFSET:
1158 apic->therm_loc_vec_tbl.val = op_val;
1160 case PERF_CTR_LOC_VEC_TBL_OFFSET:
1161 apic->perf_ctr_loc_vec_tbl.val = op_val;
1163 case LINT0_VEC_TBL_OFFSET:
1164 apic->lint0_vec_tbl.val = op_val;
1166 case LINT1_VEC_TBL_OFFSET:
1167 apic->lint1_vec_tbl.val = op_val;
1169 case ERR_VEC_TBL_OFFSET:
1170 apic->err_vec_tbl.val = op_val;
1172 case TMR_INIT_CNT_OFFSET:
1173 apic->tmr_init_cnt = op_val;
1174 apic->tmr_cur_cnt = op_val;
1176 case TMR_CUR_CNT_OFFSET:
1177 apic->tmr_cur_cnt = op_val;
1179 case TMR_DIV_CFG_OFFSET:
1180 apic->tmr_div_cfg.val = op_val;
1184 // Enable mask (256 bits)
1186 *(uint32_t *)(apic->int_en_reg) = op_val;
1189 *(uint32_t *)(apic->int_en_reg + 4) = op_val;
1192 *(uint32_t *)(apic->int_en_reg + 8) = op_val;
1195 *(uint32_t *)(apic->int_en_reg + 12) = op_val;
1198 *(uint32_t *)(apic->int_en_reg + 16) = op_val;
1201 *(uint32_t *)(apic->int_en_reg + 20) = op_val;
1204 *(uint32_t *)(apic->int_en_reg + 24) = op_val;
1207 *(uint32_t *)(apic->int_en_reg + 28) = op_val;
1210 case EXT_INT_LOC_VEC_TBL_OFFSET0:
1211 apic->ext_intr_vec_tbl[0].val = op_val;
1213 case EXT_INT_LOC_VEC_TBL_OFFSET1:
1214 apic->ext_intr_vec_tbl[1].val = op_val;
1216 case EXT_INT_LOC_VEC_TBL_OFFSET2:
1217 apic->ext_intr_vec_tbl[2].val = op_val;
1219 case EXT_INT_LOC_VEC_TBL_OFFSET3:
1220 apic->ext_intr_vec_tbl[3].val = op_val;
1230 case INT_CMD_LO_OFFSET:
1231 apic->int_cmd.lo = op_val;
1233 PrintDebug("apic %u: core %u: sending cmd 0x%llx to apic %u\n",
1234 apic->lapic_id.val, core->cpu_id,
1235 apic->int_cmd.val, apic->int_cmd.dst);
1237 if (route_ipi(apic_dev, apic, &(apic->int_cmd)) == -1) {
1238 PrintError("IPI Routing failure\n");
1244 case INT_CMD_HI_OFFSET:
1245 apic->int_cmd.hi = op_val;
1249 // Unhandled Registers
1250 case EXT_APIC_CMD_OFFSET:
1253 PrintError("apic %u: core %u: Write to Unhandled APIC Register: %x (ignored)\n",
1254 apic->lapic_id.val, core->cpu_id, (uint32_t)reg_addr);
1259 PrintDebug("apic %u: core %u: Write finished\n", apic->lapic_id.val, core->cpu_id);
1266 /* Interrupt Controller Functions */
1268 // returns 1 if an interrupt is pending, 0 otherwise
1269 static int apic_intr_pending(struct guest_info * core, void * private_data) {
1270 struct apic_dev_state * apic_dev = (struct apic_dev_state *)(private_data);
1271 struct apic_state * apic = &(apic_dev->apics[core->cpu_id]);
1272 int req_irq = get_highest_irr(apic);
1273 int svc_irq = get_highest_isr(apic);
1275 // PrintDebug("apic %u: core %u: req_irq=%d, svc_irq=%d\n",apic->lapic_id.val,info->cpu_id,req_irq,svc_irq);
1277 if ((req_irq >= 0) &&
1278 (req_irq > svc_irq)) {
1285 static int apic_get_intr_number(struct guest_info * core, void * private_data) {
1286 struct apic_dev_state * apic_dev = (struct apic_dev_state *)(private_data);
1287 struct apic_state * apic = &(apic_dev->apics[core->cpu_id]);
1288 int req_irq = get_highest_irr(apic);
1289 int svc_irq = get_highest_isr(apic);
1291 if (svc_irq == -1) {
1293 } else if (svc_irq < req_irq) {
1301 int v3_apic_send_ipi(struct v3_vm_info * vm, struct v3_gen_ipi * ipi, void * dev_data) {
1302 struct apic_dev_state * apic_dev = (struct apic_dev_state *)
1303 (((struct vm_device *)dev_data)->private_data);
1304 struct int_cmd_reg tmp_icr;
1306 // zero out all the fields
1309 tmp_icr.vec = ipi->vector;
1310 tmp_icr.del_mode = ipi->mode;
1311 tmp_icr.dst_mode = ipi->logical;
1312 tmp_icr.trig_mode = ipi->trigger_mode;
1313 tmp_icr.dst_shorthand = ipi->dst_shorthand;
1314 tmp_icr.dst = ipi->dst;
1317 return route_ipi(apic_dev, NULL, &tmp_icr);
1321 int v3_apic_raise_intr(struct v3_vm_info * vm, uint32_t irq, uint32_t dst, void * dev_data) {
1322 struct apic_dev_state * apic_dev = (struct apic_dev_state *)
1323 (((struct vm_device*)dev_data)->private_data);
1324 struct apic_state * apic = &(apic_dev->apics[dst]);
1326 PrintDebug("apic %u core ?: raising interrupt IRQ %u (dst = %u).\n", apic->lapic_id.val, irq, dst);
1328 activate_apic_irq(apic, irq);
1330 if (V3_Get_CPU() != dst) {
1331 #ifdef CONFIG_MULTITHREAD_OS
1332 v3_interrupt_cpu(vm, dst, 0);
1343 static int apic_begin_irq(struct guest_info * core, void * private_data, int irq) {
1344 struct apic_dev_state * apic_dev = (struct apic_dev_state *)(private_data);
1345 struct apic_state * apic = &(apic_dev->apics[core->cpu_id]);
1346 int major_offset = (irq & ~0x00000007) >> 3;
1347 int minor_offset = irq & 0x00000007;
1348 uint8_t * req_location = apic->int_req_reg + major_offset;
1349 uint8_t * svc_location = apic->int_svc_reg + major_offset;
1350 uint8_t flag = 0x01 << minor_offset;
1352 if (*req_location & flag) {
1353 // we will only pay attention to a begin irq if we
1354 // know that we initiated it!
1355 *svc_location |= flag;
1356 *req_location &= ~flag;
1359 //PrintDebug("apic %u: core %u: begin irq for %d ignored since I don't own it\n",
1360 // apic->lapic_id.val, core->cpu_id, irq);
1369 /* Timer Functions */
1370 static void apic_update_time(struct guest_info * core,
1371 uint64_t cpu_cycles, uint64_t cpu_freq,
1373 struct apic_dev_state * apic_dev = (struct apic_dev_state *)(priv_data);
1374 struct apic_state * apic = &(apic_dev->apics[core->cpu_id]);
1376 // The 32 bit GCC runtime is a pile of shit
1378 uint64_t tmr_ticks = 0;
1380 uint32_t tmr_ticks = 0;
1383 uint8_t tmr_div = *(uint8_t *)&(apic->tmr_div_cfg.val);
1384 uint_t shift_num = 0;
1387 // Check whether this is true:
1388 // -> If the Init count is zero then the timer is disabled
1389 // and doesn't just blitz interrupts to the CPU
1390 if ((apic->tmr_init_cnt == 0) ||
1391 ( (apic->tmr_vec_tbl.tmr_mode == APIC_TMR_ONESHOT) &&
1392 (apic->tmr_cur_cnt == 0))) {
1393 //PrintDebug("apic %u: core %u: APIC timer not yet initialized\n",apic->lapic_id.val,info->cpu_id);
1411 case APIC_TMR_DIV16:
1414 case APIC_TMR_DIV32:
1417 case APIC_TMR_DIV64:
1420 case APIC_TMR_DIV128:
1424 PrintError("apic %u: core %u: Invalid Timer Divider configuration\n",
1425 apic->lapic_id.val, core->cpu_id);
1429 tmr_ticks = cpu_cycles >> shift_num;
1430 // PrintDebug("Timer Ticks: %p\n", (void *)tmr_ticks);
1432 if (tmr_ticks < apic->tmr_cur_cnt) {
1433 apic->tmr_cur_cnt -= tmr_ticks;
1435 tmr_ticks -= apic->tmr_cur_cnt;
1436 apic->tmr_cur_cnt = 0;
1439 PrintDebug("apic %u: core %u: Raising APIC Timer interrupt (periodic=%d) (icnt=%d) (div=%d)\n",
1440 apic->lapic_id.val, core->cpu_id,
1441 apic->tmr_vec_tbl.tmr_mode, apic->tmr_init_cnt, shift_num);
1443 if (apic_intr_pending(core, priv_data)) {
1444 PrintDebug("apic %u: core %u: Overriding pending IRQ %d\n",
1445 apic->lapic_id.val, core->cpu_id,
1446 apic_get_intr_number(core, priv_data));
1449 if (activate_internal_irq(apic, APIC_TMR_INT) == -1) {
1450 PrintError("apic %u: core %u: Could not raise Timer interrupt\n",
1451 apic->lapic_id.val, core->cpu_id);
1454 if (apic->tmr_vec_tbl.tmr_mode == APIC_TMR_PERIODIC) {
1455 tmr_ticks = tmr_ticks % apic->tmr_init_cnt;
1456 apic->tmr_cur_cnt = apic->tmr_init_cnt - tmr_ticks;
1464 static struct intr_ctrl_ops intr_ops = {
1465 .intr_pending = apic_intr_pending,
1466 .get_intr_number = apic_get_intr_number,
1467 .begin_irq = apic_begin_irq,
1471 static struct v3_timer_ops timer_ops = {
1472 .update_timer = apic_update_time,
1478 static int apic_free(struct apic_dev_state * apic_dev) {
1480 struct v3_vm_info * vm = NULL;
1482 for (i = 0; i < apic_dev->num_apics; i++) {
1483 struct apic_state * apic = &(apic_dev->apics[i]);
1484 struct guest_info * core = apic->core;
1488 v3_remove_intr_controller(core, apic->controller_handle);
1491 v3_remove_timer(core, apic->timer);
1498 v3_unhook_msr(vm, BASE_ADDR_MSR);
1505 static struct v3_device_ops dev_ops = {
1506 .free = (int (*)(void *))apic_free,
1513 static int apic_init(struct v3_vm_info * vm, v3_cfg_tree_t * cfg) {
1514 char * dev_id = v3_cfg_val(cfg, "ID");
1515 struct apic_dev_state * apic_dev = NULL;
1518 PrintDebug("apic: creating an APIC for each core\n");
1520 apic_dev = (struct apic_dev_state *)V3_Malloc(sizeof(struct apic_dev_state) +
1521 sizeof(struct apic_state) * vm->num_cores);
1523 apic_dev->num_apics = vm->num_cores;
1525 struct vm_device * dev = v3_add_device(vm, dev_id, &dev_ops, apic_dev);
1528 PrintError("apic: Could not attach device %s\n", dev_id);
1534 for (i = 0; i < vm->num_cores; i++) {
1535 struct apic_state * apic = &(apic_dev->apics[i]);
1536 struct guest_info * core = &(vm->cores[i]);
1540 init_apic_state(apic, i);
1542 apic->controller_handle = v3_register_intr_controller(core, &intr_ops, apic_dev);
1544 apic->timer = v3_add_timer(core, &timer_ops, apic_dev);
1546 if (apic->timer == NULL) {
1547 PrintError("APIC: Failed to attach timer to core %d\n", i);
1548 v3_remove_device(dev);
1552 v3_hook_full_mem(vm, core->cpu_id, apic->base_addr, apic->base_addr + PAGE_SIZE_4KB, apic_read, apic_write, apic_dev);
1554 PrintDebug("apic %u: (setup device): done, my id is %u\n", i, apic->lapic_id.val);
1557 #ifdef CONFIG_DEBUG_APIC
1558 for (i = 0; i < vm->num_cores; i++) {
1559 struct apic_state * apic = &(apic_dev->apics[i]);
1560 PrintDebug("apic: sanity check: apic %u (at %p) has id %u and msr value %llx and core at %p\n",
1561 i, apic, apic->lapic_id.val, apic->base_addr_msr.value,apic->core);
1566 PrintDebug("apic: priv_data is at %p\n", apic_dev);
1568 v3_hook_msr(vm, BASE_ADDR_MSR, read_apic_msr, write_apic_msr, apic_dev);
1575 device_register("LAPIC", apic_init)