1 #include <devices/8259a.h>
2 #include <palacios/vmm_intr.h>
3 #include <palacios/vmm_types.h>
4 #include <palacios/vmm.h>
7 typedef enum {RESET, ICW1, ICW2, ICW3, ICW4, READY} pic_state_t;
9 static const uint_t MASTER_PORT1 = 0x20;
10 static const uint_t MASTER_PORT2 = 0x21;
11 static const uint_t SLAVE_PORT1 = 0xA0;
12 static const uint_t SLAVE_PORT2 = 0xA1;
14 #define IS_OCW2(x) (((x & 0x18) >> 3) == 0x0)
15 #define IS_OCW3(x) (((x & 0x18) >> 3) == 0x1)
18 uint_t ic4 : 1; // ICW4 has to be read
19 uint_t sngl : 1; // single (only one PIC)
20 uint_t adi : 1; // call address interval
21 uint_t ltim : 1; // level interrupt mode
33 // Each bit that is set indicates that the IR input has a slave
45 // The ID is the Slave device ID
52 uint_t uPM : 1; // 1=x86
53 uint_t AEOI : 1; // Automatic End of Interrupt
54 uint_t M_S : 1; // only if buffered 1=master,0=slave
55 uint_t BUF : 1; // buffered mode
56 uint_t SFNM : 1; // special fully nexted mode
74 uint_t cw_code : 2; // should be 00
84 uint_t cw_code : 2; // should be 01
119 pic_state_t master_state;
120 pic_state_t slave_state;
125 static int pic_raise_intr(void * private_data, int irq, int error_code) {
126 struct pic_internal * state = (struct pic_internal*)private_data;
133 state->master_irr |= 0x01 << irq;
134 } else if ((irq > 7) && (irq < 16)) {
135 state->slave_irr |= 0x01 << (irq - 7);
143 static int pic_intr_pending(void * private_data) {
144 struct pic_internal * state = (struct pic_internal*)private_data;
146 if ((state->master_irr & ~(state->master_imr)) ||
147 (state->slave_irr & ~(state->slave_imr))) {
154 static int pic_get_intr_number(void * private_data) {
155 struct pic_internal * state = (struct pic_internal*)private_data;
158 for (i = 0; i < 16; i++) {
160 if (((state->master_irr & ~(state->master_imr)) >> i) == 0x01) {
164 if (((state->slave_irr & ~(state->slave_imr)) >> i) == 0x01) {
174 static int begin_irq(void * private_data, int irq) {
179 static int end_irq(void * private_data, int irq) {
185 static struct intr_ctrl_ops intr_ops = {
186 .intr_pending = pic_intr_pending,
187 .get_intr_number = pic_get_intr_number,
188 .raise_intr = pic_raise_intr,
189 .begin_irq = begin_irq,
198 int read_master_port1(ushort_t port, void * dst, uint_t length, struct vm_device * dev) {
199 struct pic_internal * state = (struct pic_internal*)dev->private_data;
204 if ((state->master_ocw3 & 0x03) == 0x02) {
205 *(char *)dst = state->master_irr;
206 } else if ((state->master_ocw3 & 0x03) == 0x03) {
207 *(char *)dst = state->master_isr;
215 int read_master_port2(ushort_t port, void * dst, uint_t length, struct vm_device * dev) {
216 struct pic_internal * state = (struct pic_internal*)dev->private_data;
221 *(char *)dst = state->master_imr;
227 int read_slave_port1(ushort_t port, void * dst, uint_t length, struct vm_device * dev) {
228 struct pic_internal * state = (struct pic_internal*)dev->private_data;
233 if ((state->slave_ocw3 & 0x03) == 0x02) {
234 *(char*)dst = state->slave_irr;
235 } else if ((state->slave_ocw3 & 0x03) == 0x03) {
236 *(char *)dst = state->slave_isr;
244 int read_slave_port2(ushort_t port, void * dst, uint_t length, struct vm_device * dev) {
245 struct pic_internal * state = (struct pic_internal*)dev->private_data;
250 *(char *)dst = state->slave_imr;
256 int write_master_port1(ushort_t port, void * src, uint_t length, struct vm_device * dev) {
257 struct pic_internal * state = (struct pic_internal*)dev->private_data;
258 char cw = *(char *)src;
264 if (state->master_state == ICW1) {
265 state->master_icw1 = cw;
266 state->master_state = ICW2;
267 } else if (state->master_state == READY) {
269 // handle the EOI here
270 struct ocw2 * cw2 = (struct ocw2 *)cw;
272 if ((cw2->EOI) && (!cw2->R) && (cw2->SL)) {
274 state->master_isr &= ~(0x01 << cw2->level);
279 state->master_ocw2 = cw;
280 } else if (IS_OCW3(cw)) {
281 state->master_ocw3 = cw;
292 int write_master_port2(ushort_t port, void * src, uint_t length, struct vm_device * dev) {
293 struct pic_internal * state = (struct pic_internal*)dev->private_data;
294 char cw = *(char *)src;
300 if (state->master_state == ICW2) {
301 struct icw1 * cw1 = (struct icw1 *)&(state->master_icw1);
303 state->master_icw2 = cw;
305 if (cw1->sngl == 0) {
306 state->master_state = ICW3;
307 } else if (cw1->ic4 == 1) {
308 state->master_state = ICW4;
310 state->master_state = READY;
313 } else if (state->master_state == ICW3) {
314 struct icw1 * cw1 = (struct icw1 *)&(state->master_icw1);
316 state->master_icw3 = cw;
319 state->master_state = ICW4;
321 state->master_state = READY;
324 } else if (state->master_state == ICW4) {
325 state->master_icw4 = cw;
326 state->master_state = READY;
327 } else if (state->master_state == READY) {
328 state->master_imr = cw;
336 int write_slave_port1(ushort_t port, void * src, uint_t length, struct vm_device * dev) {
337 struct pic_internal * state = (struct pic_internal*)dev->private_data;
338 char cw = *(char *)src;
344 if (state->slave_state == ICW1) {
345 state->slave_icw1 = cw;
346 state->slave_state = ICW2;
347 } else if (state->slave_state == READY) {
349 // handle the EOI here
350 struct ocw2 * cw2 = (struct ocw2 *)cw;
352 if ((cw2->EOI) && (!cw2->R) && (cw2->SL)) {
354 state->slave_isr &= ~(0x01 << cw2->level);
359 state->slave_ocw2 = cw;
360 } else if (IS_OCW3(cw)) {
361 // Basically sets the IRR/ISR read flag
362 state->slave_ocw3 = cw;
373 int write_slave_port2(ushort_t port, void * src, uint_t length, struct vm_device * dev) {
374 struct pic_internal * state = (struct pic_internal*)dev->private_data;
375 char cw = *(char *)src;
381 if (state->slave_state == ICW2) {
382 struct icw1 * cw1 = (struct icw1 *)&(state->master_icw1);
384 state->slave_icw2 = cw;
386 if (cw1->sngl == 0) {
387 state->slave_state = ICW3;
388 } else if (cw1->ic4 == 1) {
389 state->slave_state = ICW4;
391 state->slave_state = READY;
394 } else if (state->slave_state == ICW3) {
395 struct icw1 * cw1 = (struct icw1 *)&(state->master_icw1);
397 state->slave_icw3 = cw;
400 state->slave_state = ICW4;
402 state->slave_state = READY;
405 } else if (state->slave_state == ICW4) {
406 state->slave_icw4 = cw;
407 state->slave_state = READY;
408 } else if (state->slave_state == READY) {
409 state->slave_imr = cw;
424 int pic_init(struct vm_device * dev) {
425 struct pic_internal * state = (struct pic_internal*)dev->private_data;
427 set_intr_controller(dev->vm, &intr_ops, state);
429 state->master_irr = 0;
430 state->master_isr = 0;
431 state->master_icw1 = 0;
432 state->master_icw2 = 0;
433 state->master_icw3 = 0;
434 state->master_icw4 = 0;
435 state->master_imr = 0;
436 state->master_ocw2 = 0;
437 state->master_ocw3 = 0x02;
438 state->master_state = ICW1;
441 state->slave_irr = 0;
442 state->slave_isr = 0;
443 state->slave_icw1 = 0;
444 state->slave_icw2 = 0;
445 state->slave_icw3 = 0;
446 state->slave_icw4 = 0;
447 state->slave_imr = 0;
448 state->slave_ocw2 = 0;
449 state->slave_ocw3 = 0x02;
450 state->slave_state = ICW1;
453 dev_hook_io(dev, MASTER_PORT1, &read_master_port1, &write_master_port1);
454 dev_hook_io(dev, MASTER_PORT2, &read_master_port2, &write_master_port2);
455 dev_hook_io(dev, SLAVE_PORT1, &read_slave_port1, &write_slave_port1);
456 dev_hook_io(dev, SLAVE_PORT2, &read_slave_port2, &write_slave_port2);
462 int pic_deinit(struct vm_device * dev) {
463 dev_unhook_io(dev, MASTER_PORT1);
464 dev_unhook_io(dev, MASTER_PORT2);
465 dev_unhook_io(dev, SLAVE_PORT1);
466 dev_unhook_io(dev, SLAVE_PORT2);
477 static struct vm_device_ops dev_ops = {
479 .deinit = pic_deinit,
486 struct vm_device * create_pic() {
487 struct pic_internal * state = NULL;
488 VMMMalloc(struct pic_internal *, state, sizeof(struct pic_internal));
490 struct vm_device *device = create_device("8259A", &dev_ops, state);