2 * This file is part of the Palacios Virtual Machine Monitor developed
3 * by the V3VEE Project with funding from the United States National
4 * Science Foundation and the Department of Energy.
6 * The V3VEE Project is a joint project between Northwestern University
7 * and the University of New Mexico. You can find out more at
10 * Copyright (c) 2008, Jack Lange <jarusl@cs.northwestern.edu>
11 * Copyright (c) 2008, The V3VEE Project <http://www.v3vee.org>
12 * All rights reserved.
14 * Author: Jack Lange <jarusl@cs.northwestern.edu>
16 * This is free software. You are permitted to use,
17 * redistribute, and modify it as specified in the file "V3VEE_LICENSE".
21 #include <devices/8259a.h>
22 #include <palacios/vmm_intr.h>
23 #include <palacios/vmm_types.h>
24 #include <palacios/vmm.h>
28 #define PrintDebug(fmt, args...)
32 typedef enum {RESET, ICW1, ICW2, ICW3, ICW4, READY} pic_state_t;
34 static const uint_t MASTER_PORT1 = 0x20;
35 static const uint_t MASTER_PORT2 = 0x21;
36 static const uint_t SLAVE_PORT1 = 0xA0;
37 static const uint_t SLAVE_PORT2 = 0xA1;
39 #define IS_ICW1(x) (((x & 0x10) >> 4) == 0x1)
40 #define IS_OCW2(x) (((x & 0x18) >> 3) == 0x0)
41 #define IS_OCW3(x) (((x & 0x18) >> 3) == 0x1)
45 uint_t ic4 : 1; // ICW4 has to be read
46 uint_t sngl : 1; // single (only one PIC)
47 uint_t adi : 1; // call address interval
48 uint_t ltim : 1; // level interrupt mode
60 // Each bit that is set indicates that the IR input has a slave
72 // The ID is the Slave device ID
79 uint_t uPM : 1; // 1=x86
80 uint_t AEOI : 1; // Automatic End of Interrupt
81 uint_t M_S : 1; // only if buffered 1=master,0=slave
82 uint_t BUF : 1; // buffered mode
83 uint_t SFNM : 1; // special fully nexted mode
101 uint_t cw_code : 2; // should be 00
111 uint_t cw_code : 2; // should be 01
118 struct pic_internal {
146 pic_state_t master_state;
147 pic_state_t slave_state;
151 static void DumpPICState(struct pic_internal *p)
154 PrintDebug("8259 PIC: master_state=0x%x\n",p->master_state);
155 PrintDebug("8259 PIC: master_irr=0x%x\n",p->master_irr);
156 PrintDebug("8259 PIC: master_isr=0x%x\n",p->master_isr);
157 PrintDebug("8259 PIC: master_imr=0x%x\n",p->master_imr);
159 PrintDebug("8259 PIC: master_ocw2=0x%x\n",p->master_ocw2);
160 PrintDebug("8259 PIC: master_ocw3=0x%x\n",p->master_ocw3);
162 PrintDebug("8259 PIC: master_icw1=0x%x\n",p->master_icw1);
163 PrintDebug("8259 PIC: master_icw2=0x%x\n",p->master_icw2);
164 PrintDebug("8259 PIC: master_icw3=0x%x\n",p->master_icw3);
165 PrintDebug("8259 PIC: master_icw4=0x%x\n",p->master_icw4);
167 PrintDebug("8259 PIC: slave_state=0x%x\n",p->slave_state);
168 PrintDebug("8259 PIC: slave_irr=0x%x\n",p->slave_irr);
169 PrintDebug("8259 PIC: slave_isr=0x%x\n",p->slave_isr);
170 PrintDebug("8259 PIC: slave_imr=0x%x\n",p->slave_imr);
172 PrintDebug("8259 PIC: slave_ocw2=0x%x\n",p->slave_ocw2);
173 PrintDebug("8259 PIC: slave_ocw3=0x%x\n",p->slave_ocw3);
175 PrintDebug("8259 PIC: slave_icw1=0x%x\n",p->slave_icw1);
176 PrintDebug("8259 PIC: slave_icw2=0x%x\n",p->slave_icw2);
177 PrintDebug("8259 PIC: slave_icw3=0x%x\n",p->slave_icw3);
178 PrintDebug("8259 PIC: slave_icw4=0x%x\n",p->slave_icw4);
183 static int pic_raise_intr(void * private_data, int irq) {
184 struct pic_internal * state = (struct pic_internal*)private_data;
188 state->master_irr |= 0x04; // PAD
191 PrintDebug("8259 PIC: Raising irq %d in the PIC\n", irq);
194 state->master_irr |= 0x01 << irq;
195 } else if ((irq > 7) && (irq < 16)) {
196 state->slave_irr |= 0x01 << (irq - 8); // PAD if -7 then irq 15=no irq
198 PrintError("8259 PIC: Invalid IRQ raised (%d)\n", irq);
208 static int pic_lower_intr(void *private_data, int irq_no) {
210 struct pic_internal *state = (struct pic_internal*)private_data;
212 PrintDebug("[pic_lower_intr] IRQ line %d now low\n", (unsigned) irq_no);
215 state->master_irr &= ~(1 << irq_no);
216 if ((state->master_irr & ~(state->master_imr)) == 0) {
217 PrintDebug("\t\tFIXME: Master maybe should do sth\n");
219 } else if ((irq_no > 7) && (irq_no <= 15)) {
221 state->slave_irr &= ~(1 << (irq_no - 8));
222 if ((state->slave_irr & (~(state->slave_imr))) == 0) {
223 PrintDebug("\t\tFIXME: Slave maybe should do sth\n");
231 static int pic_intr_pending(void * private_data) {
232 struct pic_internal * state = (struct pic_internal*)private_data;
234 if ((state->master_irr & ~(state->master_imr)) ||
235 (state->slave_irr & ~(state->slave_imr))) {
242 static int pic_get_intr_number(void * private_data) {
243 struct pic_internal * state = (struct pic_internal *)private_data;
247 PrintDebug("8259 PIC: getnum: master_irr: 0x%x master_imr: 0x%x\n", i, state->master_irr, state->master_imr);
248 PrintDebug("8259 PIC: getnum: slave_irr: 0x%x slave_imr: 0x%x\n", i, state->slave_irr, state->slave_imr);
250 for (i = 0; i < 16; i++) {
252 if (((state->master_irr & ~(state->master_imr)) >> i) == 0x01) {
253 //state->master_isr |= (0x1 << i);
255 //state->master_irr &= ~(0x1 << i);
256 PrintDebug("8259 PIC: IRQ: %d, master_icw2: %x\n", i, state->master_icw2);
257 irq= i + state->master_icw2;
261 if (((state->slave_irr & ~(state->slave_imr)) >> (i - 8)) == 0x01) {
262 //state->slave_isr |= (0x1 << (i - 8));
263 //state->slave_irr &= ~(0x1 << (i - 8));
264 PrintDebug("8259 PIC: IRQ: %d, slave_icw2: %x\n", i, state->slave_icw2);
265 irq= (i - 8) + state->slave_icw2;
271 if ((i == 15) || (i == 6)) {
284 /* The IRQ number is the number returned by pic_get_intr_number(), not the pin number */
285 static int pic_begin_irq(void * private_data, int irq) {
286 struct pic_internal * state = (struct pic_internal*)private_data;
288 if ((irq >= state->master_icw2) && (irq <= state->master_icw2 + 7)) {
290 } else if ((irq >= state->slave_icw2) && (irq <= state->slave_icw2 + 7)) {
294 PrintError("8259 PIC: Could not find IRQ (0x%x) to Begin\n",irq);
299 if (((state->master_irr & ~(state->master_imr)) >> irq) == 0x01) {
300 state->master_isr |= (0x1 << irq);
301 state->master_irr &= ~(0x1 << irq);
304 state->slave_isr |= (0x1 << (irq - 8));
305 state->slave_irr &= ~(0x1 << (irq - 8));
313 static int pic_end_irq(void * private_data, int irq) {
320 static struct intr_ctrl_ops intr_ops = {
321 .intr_pending = pic_intr_pending,
322 .get_intr_number = pic_get_intr_number,
323 .raise_intr = pic_raise_intr,
324 .begin_irq = pic_begin_irq,
325 .lower_intr = pic_lower_intr, //Zheng added
332 int read_master_port1(ushort_t port, void * dst, uint_t length, struct vm_device * dev) {
333 struct pic_internal * state = (struct pic_internal*)dev->private_data;
336 PrintError("8259 PIC: Invalid Read length (rd_Master1)\n");
340 if ((state->master_ocw3 & 0x03) == 0x02) {
341 *(uchar_t *)dst = state->master_irr;
342 } else if ((state->master_ocw3 & 0x03) == 0x03) {
343 *(uchar_t *)dst = state->master_isr;
351 int read_master_port2(ushort_t port, void * dst, uint_t length, struct vm_device * dev) {
352 struct pic_internal * state = (struct pic_internal*)dev->private_data;
355 PrintError("8259 PIC: Invalid Read length (rd_Master2)\n");
359 *(uchar_t *)dst = state->master_imr;
365 int read_slave_port1(ushort_t port, void * dst, uint_t length, struct vm_device * dev) {
366 struct pic_internal * state = (struct pic_internal*)dev->private_data;
369 PrintError("8259 PIC: Invalid Read length (rd_Slave1)\n");
373 if ((state->slave_ocw3 & 0x03) == 0x02) {
374 *(uchar_t*)dst = state->slave_irr;
375 } else if ((state->slave_ocw3 & 0x03) == 0x03) {
376 *(uchar_t *)dst = state->slave_isr;
384 int read_slave_port2(ushort_t port, void * dst, uint_t length, struct vm_device * dev) {
385 struct pic_internal * state = (struct pic_internal*)dev->private_data;
388 PrintError("8259 PIC: Invalid Read length (rd_Slave2)\n");
392 *(uchar_t *)dst = state->slave_imr;
398 int write_master_port1(ushort_t port, void * src, uint_t length, struct vm_device * dev) {
399 struct pic_internal * state = (struct pic_internal*)dev->private_data;
400 uchar_t cw = *(uchar_t *)src;
402 PrintDebug("8259 PIC: Write master port 1 with 0x%x\n",cw);
405 PrintError("8259 PIC: Invalid Write length (wr_Master1)\n");
411 PrintDebug("8259 PIC: Setting ICW1 = %x (wr_Master1)\n", cw);
413 state->master_icw1 = cw;
414 state->master_state = ICW2;
416 } else if (state->master_state == READY) {
418 // handle the EOI here
419 struct ocw2 * cw2 = (struct ocw2*)&cw;
421 PrintDebug("8259 PIC: Handling OCW2 = %x (wr_Master1)\n", cw);
423 if ((cw2->EOI) && (!cw2->R) && (cw2->SL)) {
425 state->master_isr &= ~(0x01 << cw2->level);
426 } else if ((cw2->EOI) & (!cw2->R) && (!cw2->SL)) {
429 PrintDebug("8259 PIC: Pre ISR = %x (wr_Master1)\n", state->master_isr);
430 for (i = 0; i < 8; i++) {
431 if (state->master_isr & (0x01 << i)) {
432 state->master_isr &= ~(0x01 << i);
436 PrintDebug("8259 PIC: Post ISR = %x (wr_Master1)\n", state->master_isr);
438 PrintError("8259 PIC: Command not handled, or in error (wr_Master1)\n");
442 state->master_ocw2 = cw;
443 } else if (IS_OCW3(cw)) {
444 PrintDebug("8259 PIC: Handling OCW3 = %x (wr_Master1)\n", cw);
445 state->master_ocw3 = cw;
447 PrintError("8259 PIC: Invalid OCW to PIC (wr_Master1)\n");
448 PrintError("8259 PIC: CW=%x\n", cw);
452 PrintError("8259 PIC: Invalid PIC State (wr_Master1)\n");
453 PrintError("8259 PIC: CW=%x\n", cw);
460 int write_master_port2(ushort_t port, void * src, uint_t length, struct vm_device * dev) {
461 struct pic_internal * state = (struct pic_internal*)dev->private_data;
462 uchar_t cw = *(uchar_t *)src;
464 PrintDebug("8259 PIC: Write master port 2 with 0x%x\n",cw);
467 PrintError("8259 PIC: Invalid Write length (wr_Master2)\n");
471 if (state->master_state == ICW2) {
472 struct icw1 * cw1 = (struct icw1 *)&(state->master_icw1);
474 PrintDebug("8259 PIC: Setting ICW2 = %x (wr_Master2)\n", cw);
475 state->master_icw2 = cw;
477 if (cw1->sngl == 0) {
478 state->master_state = ICW3;
479 } else if (cw1->ic4 == 1) {
480 state->master_state = ICW4;
482 state->master_state = READY;
485 } else if (state->master_state == ICW3) {
486 struct icw1 * cw1 = (struct icw1 *)&(state->master_icw1);
488 PrintDebug("8259 PIC: Setting ICW3 = %x (wr_Master2)\n", cw);
490 state->master_icw3 = cw;
493 state->master_state = ICW4;
495 state->master_state = READY;
498 } else if (state->master_state == ICW4) {
499 PrintDebug("8259 PIC: Setting ICW4 = %x (wr_Master2)\n", cw);
500 state->master_icw4 = cw;
501 state->master_state = READY;
502 } else if (state->master_state == READY) {
503 PrintDebug("8259 PIC: Setting IMR = %x (wr_Master2)\n", cw);
504 state->master_imr = cw;
507 PrintError("8259 PIC: Invalid master PIC State (wr_Master2)\n");
514 int write_slave_port1(ushort_t port, void * src, uint_t length, struct vm_device * dev) {
515 struct pic_internal * state = (struct pic_internal*)dev->private_data;
516 uchar_t cw = *(uchar_t *)src;
518 PrintDebug("8259 PIC: Write slave port 1 with 0x%x\n",cw);
522 PrintError("8259 PIC: Invalid Write length (wr_Slave1)\n");
527 PrintDebug("8259 PIC: Setting ICW1 = %x (wr_Slave1)\n", cw);
528 state->slave_icw1 = cw;
529 state->slave_state = ICW2;
530 } else if (state->slave_state == READY) {
532 // handle the EOI here
533 struct ocw2 * cw2 = (struct ocw2 *)&cw;
535 PrintDebug("8259 PIC: Setting OCW2 = %x (wr_Slave1)\n", cw);
537 if ((cw2->EOI) && (!cw2->R) && (cw2->SL)) {
539 state->slave_isr &= ~(0x01 << cw2->level);
540 } else if ((cw2->EOI) & (!cw2->R) && (!cw2->SL)) {
543 PrintDebug("8259 PIC: Pre ISR = %x (wr_Slave1)\n", state->slave_isr);
544 for (i = 0; i < 8; i++) {
545 if (state->slave_isr & (0x01 << i)) {
546 state->slave_isr &= ~(0x01 << i);
550 PrintDebug("8259 PIC: Post ISR = %x (wr_Slave1)\n", state->slave_isr);
552 PrintError("8259 PIC: Command not handled or invalid (wr_Slave1)\n");
556 state->slave_ocw2 = cw;
557 } else if (IS_OCW3(cw)) {
558 // Basically sets the IRR/ISR read flag
559 PrintDebug("8259 PIC: Setting OCW3 = %x (wr_Slave1)\n", cw);
560 state->slave_ocw3 = cw;
562 PrintError("8259 PIC: Invalid command work (wr_Slave1)\n");
566 PrintError("8259 PIC: Invalid State writing (wr_Slave1)\n");
573 int write_slave_port2(ushort_t port, void * src, uint_t length, struct vm_device * dev) {
574 struct pic_internal * state = (struct pic_internal*)dev->private_data;
575 uchar_t cw = *(uchar_t *)src;
577 PrintDebug("8259 PIC: Write slave port 2 with 0x%x\n",cw);
580 PrintError("8259 PIC: Invalid write length (wr_Slave2)\n");
584 if (state->slave_state == ICW2) {
585 struct icw1 * cw1 = (struct icw1 *)&(state->master_icw1);
587 PrintDebug("8259 PIC: Setting ICW2 = %x (wr_Slave2)\n", cw);
589 state->slave_icw2 = cw;
591 if (cw1->sngl == 0) {
592 state->slave_state = ICW3;
593 } else if (cw1->ic4 == 1) {
594 state->slave_state = ICW4;
596 state->slave_state = READY;
599 } else if (state->slave_state == ICW3) {
600 struct icw1 * cw1 = (struct icw1 *)&(state->master_icw1);
602 PrintDebug("8259 PIC: Setting ICW3 = %x (wr_Slave2)\n", cw);
604 state->slave_icw3 = cw;
607 state->slave_state = ICW4;
609 state->slave_state = READY;
612 } else if (state->slave_state == ICW4) {
613 PrintDebug("8259 PIC: Setting ICW4 = %x (wr_Slave2)\n", cw);
614 state->slave_icw4 = cw;
615 state->slave_state = READY;
616 } else if (state->slave_state == READY) {
617 PrintDebug("8259 PIC: Setting IMR = %x (wr_Slave2)\n", cw);
618 state->slave_imr = cw;
620 PrintError("8259 PIC: Invalid State at write (wr_Slave2)\n");
634 int pic_init(struct vm_device * dev) {
635 struct pic_internal * state = (struct pic_internal*)dev->private_data;
637 set_intr_controller(dev->vm, &intr_ops, state);
639 state->master_irr = 0;
640 state->master_isr = 0;
641 state->master_icw1 = 0;
642 state->master_icw2 = 0;
643 state->master_icw3 = 0;
644 state->master_icw4 = 0;
645 state->master_imr = 0;
646 state->master_ocw2 = 0;
647 state->master_ocw3 = 0x02;
648 state->master_state = ICW1;
651 state->slave_irr = 0;
652 state->slave_isr = 0;
653 state->slave_icw1 = 0;
654 state->slave_icw2 = 0;
655 state->slave_icw3 = 0;
656 state->slave_icw4 = 0;
657 state->slave_imr = 0;
658 state->slave_ocw2 = 0;
659 state->slave_ocw3 = 0x02;
660 state->slave_state = ICW1;
663 dev_hook_io(dev, MASTER_PORT1, &read_master_port1, &write_master_port1);
664 dev_hook_io(dev, MASTER_PORT2, &read_master_port2, &write_master_port2);
665 dev_hook_io(dev, SLAVE_PORT1, &read_slave_port1, &write_slave_port1);
666 dev_hook_io(dev, SLAVE_PORT2, &read_slave_port2, &write_slave_port2);
672 int pic_deinit(struct vm_device * dev) {
673 dev_unhook_io(dev, MASTER_PORT1);
674 dev_unhook_io(dev, MASTER_PORT2);
675 dev_unhook_io(dev, SLAVE_PORT1);
676 dev_unhook_io(dev, SLAVE_PORT2);
687 static struct vm_device_ops dev_ops = {
689 .deinit = pic_deinit,
696 struct vm_device * create_pic() {
697 struct pic_internal * state = NULL;
698 state = (struct pic_internal *)V3_Malloc(sizeof(struct pic_internal));
699 V3_ASSERT(state != NULL);
701 struct vm_device *device = create_device("8259A", &dev_ops, state);