1 #include <devices/8259a.h>
2 #include <palacios/vmm_intr.h>
3 #include <palacios/vmm_types.h>
4 #include <palacios/vmm.h>
7 typedef enum {RESET, ICW1, ICW2, ICW3, ICW4, READY} pic_state_t;
9 static const uint_t MASTER_PORT1 = 0x20;
10 static const uint_t MASTER_PORT2 = 0x21;
11 static const uint_t SLAVE_PORT1 = 0xA0;
12 static const uint_t SLAVE_PORT2 = 0xA1;
14 #define IS_OCW2(x) (((x & 0x18) >> 3) == 0x0)
15 #define IS_OCW3(x) (((x & 0x18) >> 3) == 0x1)
18 uint_t ic4 : 1; // ICW4 has to be read
19 uint_t sngl : 1; // single (only one PIC)
20 uint_t adi : 1; // call address interval
21 uint_t ltim : 1; // level interrupt mode
33 // Each bit that is set indicates that the IR input has a slave
45 // The ID is the Slave device ID
52 uint_t uPM : 1; // 1=x86
53 uint_t AEOI : 1; // Automatic End of Interrupt
54 uint_t M_S : 1; // only if buffered 1=master,0=slave
55 uint_t BUF : 1; // buffered mode
56 uint_t SFNM : 1; // special fully nexted mode
74 uint_t cw_code : 2; // should be 00
84 uint_t cw_code : 2; // should be 01
119 pic_state_t master_state;
120 pic_state_t slave_state;
125 static int pic_raise_intr(void * private_data, int irq, int error_code) {
126 struct pic_internal * state = (struct pic_internal*)private_data;
132 PrintDebug("Raising irq %d in the PIC\n", irq);
135 state->master_irr |= 0x01 << irq;
136 } else if ((irq > 7) && (irq < 16)) {
137 state->slave_irr |= 0x01 << (irq - 7);
139 PrintDebug("Invalid IRQ raised (%d)\n", irq);
146 static int pic_intr_pending(void * private_data) {
147 struct pic_internal * state = (struct pic_internal*)private_data;
149 if ((state->master_irr & ~(state->master_imr)) ||
150 (state->slave_irr & ~(state->slave_imr))) {
157 static int pic_get_intr_number(void * private_data) {
158 struct pic_internal * state = (struct pic_internal*)private_data;
161 for (i = 0; i < 16; i++) {
163 if (((state->master_irr & ~(state->master_imr)) >> i) == 0x01) {
164 state->master_isr |= (0x1 << i);
165 return i + state->master_icw2;
168 if (((state->slave_irr & ~(state->slave_imr)) >> i) == 0x01) {
169 state->slave_isr |= (0x1 << i);
170 return i + state->slave_icw2;
179 static int pic_begin_irq(void * private_data, int irq) {
185 static int pic_end_irq(void * private_data, int irq) {
191 static struct intr_ctrl_ops intr_ops = {
192 .intr_pending = pic_intr_pending,
193 .get_intr_number = pic_get_intr_number,
194 .raise_intr = pic_raise_intr,
195 .begin_irq = pic_begin_irq,
204 int read_master_port1(ushort_t port, void * dst, uint_t length, struct vm_device * dev) {
205 struct pic_internal * state = (struct pic_internal*)dev->private_data;
210 if ((state->master_ocw3 & 0x03) == 0x02) {
211 *(char *)dst = state->master_irr;
212 } else if ((state->master_ocw3 & 0x03) == 0x03) {
213 *(char *)dst = state->master_isr;
221 int read_master_port2(ushort_t port, void * dst, uint_t length, struct vm_device * dev) {
222 struct pic_internal * state = (struct pic_internal*)dev->private_data;
227 *(char *)dst = state->master_imr;
233 int read_slave_port1(ushort_t port, void * dst, uint_t length, struct vm_device * dev) {
234 struct pic_internal * state = (struct pic_internal*)dev->private_data;
239 if ((state->slave_ocw3 & 0x03) == 0x02) {
240 *(char*)dst = state->slave_irr;
241 } else if ((state->slave_ocw3 & 0x03) == 0x03) {
242 *(char *)dst = state->slave_isr;
250 int read_slave_port2(ushort_t port, void * dst, uint_t length, struct vm_device * dev) {
251 struct pic_internal * state = (struct pic_internal*)dev->private_data;
256 *(char *)dst = state->slave_imr;
262 int write_master_port1(ushort_t port, void * src, uint_t length, struct vm_device * dev) {
263 struct pic_internal * state = (struct pic_internal*)dev->private_data;
264 char cw = *(char *)src;
270 if (state->master_state == ICW1) {
271 state->master_icw1 = cw;
272 state->master_state = ICW2;
273 } else if (state->master_state == READY) {
275 // handle the EOI here
276 struct ocw2 * cw2 = (struct ocw2*)&cw;
278 if ((cw2->EOI) && (!cw2->R) && (cw2->SL)) {
280 state->master_isr &= ~(0x01 << cw2->level);
281 } else if ((cw2->EOI) & (!cw2->R) && (!cw2->SL)) {
288 state->master_ocw2 = cw;
289 } else if (IS_OCW3(cw)) {
290 state->master_ocw3 = cw;
301 int write_master_port2(ushort_t port, void * src, uint_t length, struct vm_device * dev) {
302 struct pic_internal * state = (struct pic_internal*)dev->private_data;
303 char cw = *(char *)src;
309 if (state->master_state == ICW2) {
310 struct icw1 * cw1 = (struct icw1 *)&(state->master_icw1);
312 state->master_icw2 = cw;
314 if (cw1->sngl == 0) {
315 state->master_state = ICW3;
316 } else if (cw1->ic4 == 1) {
317 state->master_state = ICW4;
319 state->master_state = READY;
322 } else if (state->master_state == ICW3) {
323 struct icw1 * cw1 = (struct icw1 *)&(state->master_icw1);
325 state->master_icw3 = cw;
328 state->master_state = ICW4;
330 state->master_state = READY;
333 } else if (state->master_state == ICW4) {
334 state->master_icw4 = cw;
335 state->master_state = READY;
336 } else if (state->master_state == READY) {
337 state->master_imr = cw;
345 int write_slave_port1(ushort_t port, void * src, uint_t length, struct vm_device * dev) {
346 struct pic_internal * state = (struct pic_internal*)dev->private_data;
347 char cw = *(char *)src;
353 if (state->slave_state == ICW1) {
354 state->slave_icw1 = cw;
355 state->slave_state = ICW2;
356 } else if (state->slave_state == READY) {
358 // handle the EOI here
359 struct ocw2 * cw2 = (struct ocw2 *)&cw;
361 if ((cw2->EOI) && (!cw2->R) && (cw2->SL)) {
363 state->slave_isr &= ~(0x01 << cw2->level);
364 } else if ((cw2->EOI) & (!cw2->R) && (!cw2->SL)) {
370 state->slave_ocw2 = cw;
371 } else if (IS_OCW3(cw)) {
372 // Basically sets the IRR/ISR read flag
373 state->slave_ocw3 = cw;
384 int write_slave_port2(ushort_t port, void * src, uint_t length, struct vm_device * dev) {
385 struct pic_internal * state = (struct pic_internal*)dev->private_data;
386 char cw = *(char *)src;
392 if (state->slave_state == ICW2) {
393 struct icw1 * cw1 = (struct icw1 *)&(state->master_icw1);
395 state->slave_icw2 = cw;
397 if (cw1->sngl == 0) {
398 state->slave_state = ICW3;
399 } else if (cw1->ic4 == 1) {
400 state->slave_state = ICW4;
402 state->slave_state = READY;
405 } else if (state->slave_state == ICW3) {
406 struct icw1 * cw1 = (struct icw1 *)&(state->master_icw1);
408 state->slave_icw3 = cw;
411 state->slave_state = ICW4;
413 state->slave_state = READY;
416 } else if (state->slave_state == ICW4) {
417 state->slave_icw4 = cw;
418 state->slave_state = READY;
419 } else if (state->slave_state == READY) {
420 state->slave_imr = cw;
435 int pic_init(struct vm_device * dev) {
436 struct pic_internal * state = (struct pic_internal*)dev->private_data;
438 set_intr_controller(dev->vm, &intr_ops, state);
440 state->master_irr = 0;
441 state->master_isr = 0;
442 state->master_icw1 = 0;
443 state->master_icw2 = 0;
444 state->master_icw3 = 0;
445 state->master_icw4 = 0;
446 state->master_imr = 0;
447 state->master_ocw2 = 0;
448 state->master_ocw3 = 0x02;
449 state->master_state = ICW1;
452 state->slave_irr = 0;
453 state->slave_isr = 0;
454 state->slave_icw1 = 0;
455 state->slave_icw2 = 0;
456 state->slave_icw3 = 0;
457 state->slave_icw4 = 0;
458 state->slave_imr = 0;
459 state->slave_ocw2 = 0;
460 state->slave_ocw3 = 0x02;
461 state->slave_state = ICW1;
464 dev_hook_io(dev, MASTER_PORT1, &read_master_port1, &write_master_port1);
465 dev_hook_io(dev, MASTER_PORT2, &read_master_port2, &write_master_port2);
466 dev_hook_io(dev, SLAVE_PORT1, &read_slave_port1, &write_slave_port1);
467 dev_hook_io(dev, SLAVE_PORT2, &read_slave_port2, &write_slave_port2);
473 int pic_deinit(struct vm_device * dev) {
474 dev_unhook_io(dev, MASTER_PORT1);
475 dev_unhook_io(dev, MASTER_PORT2);
476 dev_unhook_io(dev, SLAVE_PORT1);
477 dev_unhook_io(dev, SLAVE_PORT2);
488 static struct vm_device_ops dev_ops = {
490 .deinit = pic_deinit,
497 struct vm_device * create_pic() {
498 struct pic_internal * state = NULL;
499 VMMMalloc(struct pic_internal *, state, sizeof(struct pic_internal));
501 struct vm_device *device = create_device("8259A", &dev_ops, state);