2 * This file is part of the Palacios Virtual Machine Monitor developed
3 * by the V3VEE Project with funding from the United States National
4 * Science Foundation and the Department of Energy.
6 * The V3VEE Project is a joint project between Northwestern University
7 * and the University of New Mexico. You can find out more at
10 * Copyright (c) 2008, Jack Lange <jarusl@cs.northwestern.edu>
11 * Copyright (c) 2008, The V3VEE Project <http://www.v3vee.org>
12 * All rights reserved.
14 * Author: Jack Lange <jarusl@cs.northwestern.edu>
16 * This is free software. You are permitted to use,
17 * redistribute, and modify it as specified in the file "V3VEE_LICENSE".
22 #include <palacios/vmm_intr.h>
23 #include <palacios/vmm_types.h>
24 #include <palacios/vmm.h>
25 #include <palacios/vmm_dev_mgr.h>
26 #include <palacios/vm_guest.h>
28 #ifndef V3_CONFIG_DEBUG_PIC
30 #define PrintDebug(fmt, args...)
34 typedef enum {RESET, ICW1, ICW2, ICW3, ICW4, READY} pic_state_t;
36 static const uint_t MASTER_PORT1 = 0x20;
37 static const uint_t MASTER_PORT2 = 0x21;
38 static const uint_t SLAVE_PORT1 = 0xA0;
39 static const uint_t SLAVE_PORT2 = 0xA1;
41 static const uint_t ELCR1_PORT = 0x4d0;
42 static const uint_t ELCR2_PORT = 0x4d1;
45 #define IS_ICW1(x) (((x & 0x10) >> 4) == 0x1)
46 #define IS_OCW2(x) (((x & 0x18) >> 3) == 0x0)
47 #define IS_OCW3(x) (((x & 0x18) >> 3) == 0x1)
51 uint_t ic4 : 1; // ICW4 has to be read
52 uint_t sngl : 1; // single (only one PIC)
53 uint_t adi : 1; // call address interval
54 uint_t ltim : 1; // level interrupt mode
66 // Each bit that is set indicates that the IR input has a slave
78 // The ID is the Slave device ID
85 uint_t uPM : 1; // 1=x86
86 uint_t AEOI : 1; // Automatic End of Interrupt
87 uint_t M_S : 1; // only if buffered 1=master,0=slave
88 uint_t BUF : 1; // buffered mode
89 uint_t SFNM : 1; // special fully nexted mode
107 uint_t cw_code : 2; // should be 00
117 uint_t cw_code : 2; // should be 01
124 struct pic_internal {
135 uint8_t master_elcr_mask;
136 uint8_t slave_elcr_mask;
157 pic_state_t master_state;
158 pic_state_t slave_state;
160 struct guest_info * core;
163 int (*ack)(struct guest_info * core, uint32_t irq, void * private_data);
168 void * router_handle;
169 void * controller_handle;
173 static void DumpPICState(struct pic_internal *p)
176 V3_Print(VM_NONE, VCORE_NONE, "8259 PIC: master_state=0x%x\n",p->master_state);
177 V3_Print(VM_NONE, VCORE_NONE, "8259 PIC: master_irr=0x%x\n",p->master_irr);
178 V3_Print(VM_NONE, VCORE_NONE, "8259 PIC: master_isr=0x%x\n",p->master_isr);
179 V3_Print(VM_NONE, VCORE_NONE, "8259 PIC: master_imr=0x%x\n",p->master_imr);
181 V3_Print(VM_NONE, VCORE_NONE, "8259 PIC: master_ocw2=0x%x\n",p->master_ocw2);
182 V3_Print(VM_NONE, VCORE_NONE, "8259 PIC: master_ocw3=0x%x\n",p->master_ocw3);
184 V3_Print(VM_NONE, VCORE_NONE, "8259 PIC: master_icw1=0x%x\n",p->master_icw1);
185 V3_Print(VM_NONE, VCORE_NONE, "8259 PIC: master_icw2=0x%x\n",p->master_icw2);
186 V3_Print(VM_NONE, VCORE_NONE, "8259 PIC: master_icw3=0x%x\n",p->master_icw3);
187 V3_Print(VM_NONE, VCORE_NONE, "8259 PIC: master_icw4=0x%x\n",p->master_icw4);
189 V3_Print(VM_NONE, VCORE_NONE, "8259 PIC: slave_state=0x%x\n",p->slave_state);
190 V3_Print(VM_NONE, VCORE_NONE, "8259 PIC: slave_irr=0x%x\n",p->slave_irr);
191 V3_Print(VM_NONE, VCORE_NONE, "8259 PIC: slave_isr=0x%x\n",p->slave_isr);
192 V3_Print(VM_NONE, VCORE_NONE, "8259 PIC: slave_imr=0x%x\n",p->slave_imr);
194 V3_Print(VM_NONE, VCORE_NONE, "8259 PIC: slave_ocw2=0x%x\n",p->slave_ocw2);
195 V3_Print(VM_NONE, VCORE_NONE, "8259 PIC: slave_ocw3=0x%x\n",p->slave_ocw3);
197 V3_Print(VM_NONE, VCORE_NONE, "8259 PIC: slave_icw1=0x%x\n",p->slave_icw1);
198 V3_Print(VM_NONE, VCORE_NONE, "8259 PIC: slave_icw2=0x%x\n",p->slave_icw2);
199 V3_Print(VM_NONE, VCORE_NONE, "8259 PIC: slave_icw3=0x%x\n",p->slave_icw3);
200 V3_Print(VM_NONE, VCORE_NONE, "8259 PIC: slave_icw4=0x%x\n",p->slave_icw4);
205 static int pic_vec_to_irq(struct guest_info *info, struct pic_internal *state, int vec)
207 if ((vec >= state->master_icw2) && (vec <= state->master_icw2 + 7)) {
209 } else if ((vec >= state->slave_icw2) && (vec <= state->slave_icw2 + 7)) {
210 return (vec & 0x7) + 8;
212 // Note that this is not an error since there may also be IOAPICs
213 PrintDebug(info->vm_info, info, "8259 PIC: Cannot translate vector %d back to an IRQ I support\n",vec);
218 static int pic_irq_to_vec(struct guest_info *info, struct pic_internal *state, int irq)
224 // This will treat IRQ2 as occuring on the master,
225 // not on slave IRQ9 as expected for legacy behavior
226 // We shouldn't see anything attempting to raise IRQ2...
228 PrintError(info->vm_info, info, "8259 PIC: Warning - IRQ 2 is being translated...\n");
232 return irq + state->master_icw2;
233 } else if (irq<=15) {
234 return (irq-8) + state->slave_icw2;
236 PrintDebug(info->vm_info, info, "8259 PIC: Warning: IRQ %d is being translated, but only IRQs 0..15 are supported\n",irq);
243 static int pic_raise_intr(struct v3_vm_info * vm, void * private_data, struct v3_irq * irq) {
244 struct pic_internal * state = (struct pic_internal*)private_data;
245 uint8_t irq_num = irq->irq;
248 PrintError(vm, VCORE_NONE, "8259 PIC: Warning - IRQ 2 is being raised...\n");
249 // This is the legacy reroute of IRQ2 to IRQ9
253 PrintDebug(vm, VCORE_NONE, "8259 PIC: Raising irq %d in the PIC\n", irq_num);
256 state->master_irr |= 0x01 << irq_num;
257 PrintDebug(vm, VCORE_NONE, "8259 PIC: Master: Raising IRQ %d\n",irq_num);
258 } else if ((irq_num > 7) && (irq_num < 16)) {
259 state->slave_irr |= 0x01 << (irq_num - 8);
260 state->master_irr |= 0x04; // immediately signal to the master pin we're attached to
261 PrintDebug(vm, VCORE_NONE, "8259 PIC: Master + Slave: Raising IRQ %d\n",irq_num);
263 // This is not an error as the system could have other interrupt controllers
264 PrintDebug(vm, VCORE_NONE, "8259 PIC: Ignoring raise of IRQ %d as it is not supported by the PIC\n", irq_num);
268 state->irq_ack_cbs[irq_num].ack = irq->ack;
269 state->irq_ack_cbs[irq_num].private_data = irq->private_data;
271 if (V3_Get_CPU() != vm->cores[0].pcpu_id) {
272 // guest is running on another core, interrupt it to deliver irq
273 v3_interrupt_cpu(vm, 0, 0);
280 static int pic_lower_intr(struct v3_vm_info * vm, void * private_data, struct v3_irq * irq) {
281 struct pic_internal * state = (struct pic_internal*)private_data;
282 uint8_t irq_num = irq->irq;
285 PrintError(vm, VCORE_NONE, "8259 PIC: Warning - IRQ 2 is being lowered...\n");
286 // Legacy reroute of IRQ2 to IRQ9
290 PrintDebug(vm, VCORE_NONE, "8259 PIC: [pic_lower_intr] IRQ line %d now low\n", irq_num);
294 PrintDebug(vm, VCORE_NONE, "8259 PIC: Master: IRQ line %d lowered\n", irq_num);
295 state->master_irr &= ~(1 << irq_num);
296 // Note that another interrupt may still be in the IRR, but that's OK
297 // We'll recognize it on the next entry
298 } else if ((irq_num > 7) && (irq_num < 16)) {
300 PrintDebug(vm, VCORE_NONE, "8259 PIC: Slave: IRQ line %d lowered\n", irq_num);
301 state->slave_irr &= ~(1 << (irq_num - 8));
302 if ((state->slave_irr & (~(state->slave_imr))) == 0) {
303 // If there is no other slave interrupt available, we can
304 // turn off IRQ2 on the master
305 PrintDebug(vm, VCORE_NONE, "8259 PIC: Master: IRQ line 2 also lowered due to no other interrupts pending in slave\n");
306 state->master_irr &= ~(0x04);
309 // This is not an error as the system could have other interrupt controllers
310 PrintDebug(vm, VCORE_NONE, "8259 PIC: Ignoring lower of IRQ %d as it is not supported by the PIC\n",irq_num);
318 static int pic_intr_pending_from_master(struct guest_info * info, void * private_data) {
319 struct pic_internal * state = (struct pic_internal*)private_data;
321 return state->master_irr // interrupt pending in the master's irr
322 & (~(state->master_imr)) // and is not masked in the master
323 & (~(state->master_icw3)); // and the pin is not hooked to slave
326 static int pic_intr_pending_from_slave(struct guest_info * info, void * private_data) {
327 struct pic_internal * state = (struct pic_internal*)private_data;
329 return (!(state->master_imr & 0x4)) && // master has slave unmasked and
330 (state->slave_irr & (~(state->slave_imr))); // slave is pending
333 static int pic_intr_pending(struct guest_info * info, void * private_data) {
335 return pic_intr_pending_from_master(info,private_data) ||
336 pic_intr_pending_from_slave(info,private_data);
340 8259 prioritization is oddball since there are two chips. The
341 slave chip signals an interrupt through pin 2 of the master chip.
342 This means that all the slave chip's pins are actually at a higher priority
343 than pins 3..7 of the master. The scheme is as follows, from highest
344 to lowest priority, including legacy mappings:
346 Master Slave Typical Legacy Use
347 --------------------------------------------------------------
350 IRQ2 ****NOT USED - Slave chip inputs here
352 IRQ9 VGA / previous IRQ2 (or PCI via PIRQ LINK B)
353 IRQ10 unused (or PCI via PIRQ LINK C)
354 IRQ11 unused (or PCI via PIRQ LINK D)
355 IRQ12 PS/2 Mouse (8042)
356 IRQ13 Coprocessor error
357 IRQ14 First IDE controller
358 IRQ15 Second IDE controller
359 IRQ3 Second and Fourth Serial Port (COM2/4)
360 IRQ4 First and Third serial port (COM1/3)
361 IRQ5 Second Parallel Port (or PCI via PIRQ LINK A)
362 IRQ6 Floppy controller
363 IRQ7 First Parallel Port
367 static int pic_get_intr_number(struct guest_info * info, void * private_data) {
368 struct pic_internal * state = (struct pic_internal *)private_data;
372 PrintDebug(info->vm_info, info, "8259 PIC: getnum: master_irr: 0x%x master_imr: 0x%x\n", state->master_irr, state->master_imr);
373 PrintDebug(info->vm_info, info, "8259 PIC: getnum: slave_irr: 0x%x slave_imr: 0x%x\n", state->slave_irr, state->slave_imr);
375 // First, see if we have something upstream of the slave
377 // Interrupt requested and not masked
378 if (((state->master_irr & ~(state->master_imr)) >> i) & 0x01) {
379 PrintDebug(info->vm_info, info, "8259 PIC: IRQ: %d, master_icw2: %x\n", i, state->master_icw2);
380 vec = pic_irq_to_vec(info, state, i);
382 PrintError(info->vm_info, info, "8259 PIC: Master Interrupt Ready, but vector=%d\n",vec);
389 if (vec<0 && // Nothing upstream and
390 !(state->master_imr & 0x4)) { // Master is not masking the slave
391 for (i = 8; i < 16; i++) {
392 if (((state->slave_irr & ~(state->slave_imr)) >> (i - 8)) & 0x01) {
393 PrintDebug(info->vm_info, info, "8259 PIC: IRQ: %d, slave_icw2: %x\n", i, state->slave_icw2);
394 vec = pic_irq_to_vec(info, state, i);
396 PrintError(info->vm_info, info, "8259 PIC: Slave Interrupt Readby, but vector=%d\n",vec);
403 // And finally the master downstream of the slave
405 for (i = 3; i < 8; i++) {
406 if (((state->master_irr & ~(state->master_imr)) >> i) & 0x01) {
407 PrintDebug(info->vm_info, info, "8259 PIC: IRQ: %d, master_icw2: %x\n", i, state->master_icw2);
408 vec = pic_irq_to_vec(info, state, i);
410 PrintError(info->vm_info, info, "8259 PIC: Master Interrupt Ready in 2nd pass, but vector=%d\n",vec);
418 PrintDebug(info->vm_info, info, "8259 PIC: get num is returning vector %d\n",vec);
420 PrintDebug(info->vm_info, info, "8259 PIC: no vector available\n");
429 /* The vec number is the number returned by pic_get_irq_number(), not the pin number. */
430 /* In other words, it's the INT vector the PIC is feeding the processor */
431 static int pic_begin_irq(struct guest_info * info, void * private_data, int vec) {
432 struct pic_internal * state = (struct pic_internal*)private_data;
435 irq = pic_vec_to_irq(info,state,vec);
438 // Not an error - could be for other interrupt controller
439 PrintDebug(info->vm_info,info,"8259 PIC: Ignoring begin_irq on vector %d since it's not ours\n", vec);
445 PrintDebug(info->vm_info, info, "8259 PIC: Master: Beginning IRQ %d\n",irq);
446 // This should always be true: See pic_get_irq_number
447 if (((state->master_irr & (~(state->master_imr))) >> irq) & 0x01) {
448 // unmasked - let's start it
449 state->master_isr |= (0x1 << irq);
450 // auto reset the request if the elcr has this as edge-triggered
451 if (!(state->master_elcr & (0x1 << irq))) {
452 state->master_irr &= ~(0x1 << irq);
455 PrintDebug(info->vm_info, info, "8259 PIC: Master: Ignoring begin_irq vector %d since I either do not see it set or have it masked (mnaster_irr=0x%x, master_imr=0x%x\n", irq, state->master_irr, state->master_imr);
457 } else if (irq>=8 && irq<=15) {
459 PrintDebug(info->vm_info, info, "8259 PIC: Master + Slave: Beginning IRQ %d\n",irq);
460 // This should always be true: See pic_get_irq_number
461 if (((state->slave_irr & (~(state->slave_imr))) >> (irq - 8)) & 0x01) {
462 // unmasked - so let's start it in the slave
463 state->slave_isr |= (0x1 << (irq - 8));
464 // We must have previously pushed it to the master's irr,
465 // so all we need to do here is put it in service there too
466 state->master_isr |= 0x4; // pin 2 is where the slave attaches
468 // auto-reset the request in the slave if it's marked as edge-triggered
469 if (!(state->slave_elcr & (0x1 << (irq - 8)))) {
470 state->slave_irr &= ~(0x1 << (irq - 8));
473 // auto-reset the request in pin 2 of the master if it's marked as edge-trigged
474 if (!(state->master_elcr & 0x04)) {
475 state->master_irr &= ~0x04;
478 PrintDebug(info->vm_info, info, "8259 PIC: Maser + Slave: Ignoring begin_irq for %d since I either don't see it set or I don't own it (master_irr=0x%x, master_imr=0x%x, slave_irr=0x%x, slave_imr=0x%x\n", irq,state->master_irr, state->master_imr, state->slave_irr, state->slave_imr);
481 PrintDebug(info->vm_info, info, "8259 PIC: Ignoring begin_irq for %d since I don't own it\n", irq);
489 static int pic_end_irq(void * private_data, int irq) {
496 static struct intr_ctrl_ops intr_ops = {
497 .intr_pending = pic_intr_pending,
498 .get_intr_number = pic_get_intr_number,
499 .begin_irq = pic_begin_irq
502 static struct intr_router_ops router_ops = {
503 .raise_intr = pic_raise_intr,
504 .lower_intr = pic_lower_intr
508 static int read_master_port1(struct guest_info * core, ushort_t port, void * dst, uint_t length, void * priv_data) {
509 struct pic_internal * state = (struct pic_internal *)priv_data;
512 PrintError(core->vm_info, core, "8259 PIC: Master: Invalid Read length (rd_Master1)\n");
516 if ((state->master_ocw3 & 0x03) == 0x02) {
517 *(uint8_t *)dst = state->master_irr;
518 } else if ((state->master_ocw3 & 0x03) == 0x03) {
519 *(uint8_t *)dst = state->master_isr;
527 static int read_master_port2(struct guest_info * core, ushort_t port, void * dst, uint_t length, void * priv_data) {
528 struct pic_internal * state = (struct pic_internal *)priv_data;
531 PrintError(core->vm_info, core, "8259 PIC: Master: Invalid Read length (rd_Master2)\n");
535 *(uint8_t *)dst = state->master_imr;
541 static int read_slave_port1(struct guest_info * core, ushort_t port, void * dst, uint_t length, void * priv_data) {
542 struct pic_internal * state = (struct pic_internal *)priv_data;
545 PrintError(core->vm_info, core, "8259 PIC: Slave: Invalid Read length (rd_Slave1)\n");
549 if ((state->slave_ocw3 & 0x03) == 0x02) {
550 *(uint8_t*)dst = state->slave_irr;
551 } else if ((state->slave_ocw3 & 0x03) == 0x03) {
552 *(uint8_t *)dst = state->slave_isr;
560 static int read_slave_port2(struct guest_info * core, ushort_t port, void * dst, uint_t length, void * priv_data) {
561 struct pic_internal * state = (struct pic_internal *)priv_data;
564 PrintError(core->vm_info, core, "8259 PIC: Slave: Invalid Read length (rd_Slave2)\n");
568 *(uint8_t *)dst = state->slave_imr;
574 static int write_master_port1(struct guest_info * core, ushort_t port, void * src, uint_t length, void * priv_data) {
575 struct pic_internal * state = (struct pic_internal *)priv_data;
576 uint8_t cw = *(uint8_t *)src;
578 PrintDebug(core->vm_info, core, "8259 PIC: Master: Write port 1 with 0x%x\n",cw);
581 PrintError(core->vm_info, core, "8259 PIC: Master: Invalid Write length (wr_Master1)\n");
585 v3_clear_pending_intr(core);
589 PrintDebug(core->vm_info, core, "8259 PIC: Master: Setting ICW1 = %x (wr_Master1)\n", cw);
591 state->master_icw1 = cw;
592 state->master_state = ICW2;
594 } else if (state->master_state == READY) {
596 // handle the EOI here
597 struct ocw2 * cw2 = (struct ocw2*)&cw;
600 PrintDebug(core->vm_info, core, "8259 PIC: Master: Handling OCW2 = %x (wr_Master1)\n", cw);
602 if ((cw2->EOI) && (!cw2->R) && (cw2->SL)) {
604 state->master_isr &= ~(0x01 << cw2->level);
605 eoi_irq = cw2->level;
608 // ack the irq if requested
609 if (state->irq_ack_cbs[irq].ack) {
610 state->irq_ack_cbs[irq].ack(info, irq, state->irq_ack_cbs[irq].private_data);
614 } else if ((cw2->EOI) & (!cw2->R) && (!cw2->SL)) {
617 PrintDebug(core->vm_info, core, "8259 PIC: Master: Pre ISR = %x (wr_Master1)\n", state->master_isr);
618 for (i = 0; i < 8; i++) {
619 if (state->master_isr & (0x01 << i)) {
620 state->master_isr &= ~(0x01 << i);
626 PrintDebug(core->vm_info, core, "8259 PIC: Master: Strange... non-specific EOI but no in-service interrupts\n");
629 PrintDebug(core->vm_info, core, "8259 PIC: Master: Post ISR = %x (wr_Master1)\n", state->master_isr);
630 } else if (!(cw2->EOI) && (cw2->R) && (cw2->SL)) {
631 PrintDebug(core->vm_info, core, "8259 PIC: Master: Ignoring set-priority, priorities not implemented (level=%d, wr_Master1)\n", cw2->level);
632 } else if (!(cw2->EOI) && !(cw2->R) && (cw2->SL)) {
633 PrintDebug(core->vm_info, core, "8259 PIC: Master: Ignoring no-op (level=%d, wr_Master1)\n", cw2->level);
635 PrintError(core->vm_info, core, "8259 PIC: Master: Command not handled, or in error (wr_Master1)\n");
640 if (pic_intr_pending_from_master(core,state)) {
641 // this is perfectly fine as there may be other latched interrupts
642 // but it would be strange if the one we just cleared is suddenly
643 // alive again - well, depending on concurrent behavior external to
644 int irq = pic_vec_to_irq(core,state,pic_get_intr_number(core,state));
646 if (irq == eoi_irq) {
647 // Not necessarily an error, since it could have been raised again in another thread...
648 PrintError(core->vm_info, core, "8259 PIC: Master: IRQ %d pending after EOI of IRQ %d\n", irq,eoi_irq);
654 state->master_ocw2 = cw;
655 } else if (IS_OCW3(cw)) {
656 PrintDebug(core->vm_info, core, "8259 PIC: Master: Handling OCW3 = %x (wr_Master1)\n", cw);
657 state->master_ocw3 = cw;
659 PrintError(core->vm_info, core, "8259 PIC: Master: Invalid OCW to PIC (wr_Master1)\n");
660 PrintError(core->vm_info, core, "8259 PIC: Master: CW=%x\n", cw);
664 PrintError(core->vm_info, core, "8259 PIC: Master: Invalid PIC State (wr_Master1)\n");
665 PrintError(core->vm_info, core, "8259 PIC: Master: CW=%x\n", cw);
672 static int write_master_port2(struct guest_info * core, ushort_t port, void * src, uint_t length, void * priv_data) {
673 struct pic_internal * state = (struct pic_internal *)priv_data;
674 uint8_t cw = *(uint8_t *)src;
676 PrintDebug(core->vm_info, core, "8259 PIC: Master: Write master port 2 with 0x%x\n",cw);
679 PrintError(core->vm_info, core, "8259 PIC: Master: Invalid Write length (wr_Master2)\n");
683 v3_clear_pending_intr(core);
685 if (state->master_state == ICW2) {
686 struct icw1 * cw1 = (struct icw1 *)&(state->master_icw1);
688 PrintDebug(core->vm_info, core, "8259 PIC: Master: Setting ICW2 = %x (wr_Master2)\n", cw);
689 state->master_icw2 = cw;
693 if (cw1->sngl == 0) {
694 state->master_state = ICW3;
695 } else if (cw1->ic4 == 1) {
696 state->master_state = ICW4;
698 state->master_state = READY;
703 } else if (state->master_state == ICW3) {
704 struct icw1 * cw1 = (struct icw1 *)&(state->master_icw1);
706 PrintDebug(core->vm_info, core, "8259 PIC: Master: Setting ICW3 = %x (wr_Master2)\n", cw);
708 state->master_icw3 = cw;
711 state->master_state = ICW4;
713 state->master_state = READY;
716 } else if (state->master_state == ICW4) {
717 PrintDebug(core->vm_info, core, "8259 PIC: Master: Setting ICW4 = %x (wr_Master2)\n", cw);
718 state->master_icw4 = cw;
719 state->master_state = READY;
720 } else if ((state->master_state == ICW1) || (state->master_state == READY)) {
721 PrintDebug(core->vm_info, core, "8259 PIC: Master: Setting IMR = %x (wr_Master2)\n", cw);
722 state->master_imr = cw;
725 PrintError(core->vm_info, core, "8259 PIC: Master: Invalid master PIC State (wr_Master2) (state=%d)\n",
726 state->master_state);
733 static int write_slave_port1(struct guest_info * core, ushort_t port, void * src, uint_t length, void * priv_data) {
734 struct pic_internal * state = (struct pic_internal *)priv_data;
735 uint8_t cw = *(uint8_t *)src;
737 PrintDebug(core->vm_info, core, "8259 PIC: Slave: Write slave port 1 with 0x%x\n",cw);
741 PrintError(core->vm_info, core, "8259 PIC: Slave: Invalid Write length (wr_Slave1)\n");
745 v3_clear_pending_intr(core);
748 PrintDebug(core->vm_info, core, "8259 PIC: Slave: Setting ICW1 = %x (wr_Slave1)\n", cw);
749 state->slave_icw1 = cw;
750 state->slave_state = ICW2;
751 } else if (state->slave_state == READY) {
754 // handle the EOI here
755 struct ocw2 * cw2 = (struct ocw2 *)&cw;
757 PrintDebug(core->vm_info, core, "8259 PIC: Slave: Setting OCW2 = %x (wr_Slave1)\n", cw);
759 if ((cw2->EOI) && (!cw2->R) && (cw2->SL)) {
761 state->slave_isr &= ~(0x01 << cw2->level);
762 eoi_irq = 8+cw2->level;
763 } else if ((cw2->EOI) & (!cw2->R) && (!cw2->SL)) {
766 PrintDebug(core->vm_info, core, "8259 PIC: Slave: Pre ISR = %x (wr_Slave1)\n", state->slave_isr);
767 for (i = 0; i < 8; i++) {
768 if (state->slave_isr & (0x01 << i)) {
769 state->slave_isr &= ~(0x01 << i);
775 PrintDebug(core->vm_info, core, "8259 PIC: Slave: Strange... non-specific EOI but no in-service interrupts\n");
777 PrintDebug(core->vm_info, core, "8259 PIC: Slave: Post ISR = %x (wr_Slave1)\n", state->slave_isr);
779 PrintError(core->vm_info, core, "8259 PIC: Slave: Command not handled or invalid (wr_Slave1)\n");
783 // If we now have no further requested interrupts,
784 // we are not requesting from the master either
785 if (!(state->slave_irr)) {
786 state->master_irr &= ~0x04;
790 if (pic_intr_pending_from_slave(core,state)) {
791 // this is perfectly fine as there may be other latched interrupts
792 // but it would be strange if the one we just cleared is suddenly
793 // alive again - well, depending on concurrent behavior external to
794 int irq = pic_vec_to_irq(core,state,pic_get_intr_number(core,state));
796 if (irq == eoi_irq) {
797 // Not necessarily an error, since it could have been raised again in another thread.
798 PrintError(core->vm_info, core, "8259 PIC: Slave: IRQ %d pending after EOI of IRQ %d\n", irq,eoi_irq);
804 state->slave_ocw2 = cw;
805 } else if (IS_OCW3(cw)) {
806 // Basically sets the IRR/ISR read flag
807 PrintDebug(core->vm_info, core, "8259 PIC: Slave: Setting OCW3 = %x (wr_Slave1)\n", cw);
808 state->slave_ocw3 = cw;
810 PrintError(core->vm_info, core, "8259 PIC: Slave: Invalid command work (wr_Slave1)\n");
814 PrintError(core->vm_info, core, "8259 PIC: Slave: Invalid State writing (wr_Slave1)\n");
821 static int write_slave_port2(struct guest_info * core, ushort_t port, void * src, uint_t length, void * priv_data) {
822 struct pic_internal * state = (struct pic_internal *)priv_data;
823 uint8_t cw = *(uint8_t *)src;
825 PrintDebug(core->vm_info, core, "8259 PIC: Slave: Write slave port 2 with 0x%x\n",cw);
828 PrintError(core->vm_info, core, "8259 PIC: Slave: Invalid write length (wr_Slave2)\n");
832 v3_clear_pending_intr(core);
835 if (state->slave_state == ICW2) {
836 struct icw1 * cw1 = (struct icw1 *)&(state->master_icw1);
838 PrintDebug(core->vm_info, core, "8259 PIC: Slave: Setting ICW2 = %x (wr_Slave2)\n", cw);
840 state->slave_icw2 = cw;
842 if (cw1->sngl == 0) {
843 state->slave_state = ICW3;
844 } else if (cw1->ic4 == 1) {
845 state->slave_state = ICW4;
847 state->slave_state = READY;
850 } else if (state->slave_state == ICW3) {
851 struct icw1 * cw1 = (struct icw1 *)&(state->master_icw1);
853 PrintDebug(core->vm_info, core, "8259 PIC: Slave: Setting ICW3 = %x (wr_Slave2)\n", cw);
855 state->slave_icw3 = cw;
858 state->slave_state = ICW4;
860 state->slave_state = READY;
863 } else if (state->slave_state == ICW4) {
864 PrintDebug(core->vm_info, core, "8259 PIC: Slave: Setting ICW4 = %x (wr_Slave2)\n", cw);
865 state->slave_icw4 = cw;
866 state->slave_state = READY;
867 } else if ((state->slave_state == ICW1) || (state->slave_state == READY)) {
868 PrintDebug(core->vm_info, core, "8259 PIC: Slave: Setting IMR = %x (wr_Slave2)\n", cw);
869 state->slave_imr = cw;
871 PrintError(core->vm_info, core, "8259 PIC: Slave: Invalid State at write (wr_Slave2)\n");
881 static int read_elcr_port(struct guest_info * core, ushort_t port, void * dst, uint_t length, void * priv_data) {
882 struct pic_internal * state = (struct pic_internal *)priv_data;
885 PrintError(core->vm_info, core, "8259 PIC: ELCR read of invalid length %d\n", length);
889 if (port == ELCR1_PORT) {
891 *(uint8_t *)dst = state->master_elcr;
892 } else if (port == ELCR2_PORT) {
893 *(uint8_t *)dst = state->slave_elcr;
895 PrintError(core->vm_info, core, "8259 PIC: Invalid port %x\n", port);
903 static int write_elcr_port(struct guest_info * core, ushort_t port, void * src, uint_t length, void * priv_data) {
904 struct pic_internal * state = (struct pic_internal *)priv_data;
907 PrintError(core->vm_info, core, "8259 PIC: ELCR read of invalid length %d\n", length);
911 if (port == ELCR1_PORT) {
913 state->master_elcr = (*(uint8_t *)src) & state->master_elcr_mask;
914 } else if (port == ELCR2_PORT) {
915 state->slave_elcr = (*(uint8_t *)src) & state->slave_elcr_mask;
917 PrintError(core->vm_info, core, "8259 PIC: Invalid port %x\n", port);
926 static int pic_free(struct pic_internal * state) {
927 struct guest_info * core = state->core;
929 v3_remove_intr_controller(core, state->controller_handle);
930 v3_remove_intr_router(core->vm_info, state->router_handle);
936 #ifdef V3_CONFIG_CHECKPOINT
937 static int pic_save(struct v3_chkpt_ctx * ctx, void * private_data) {
938 struct pic_internal * pic = (struct pic_internal *)private_data;
940 V3_CHKPT_SAVE(ctx, "MASTER_IRR", pic->master_irr, savefailout);
941 V3_CHKPT_SAVE(ctx, "SLAVE_IRR", pic->slave_irr, savefailout);
943 V3_CHKPT_SAVE(ctx, "MASTER_ISR", pic->master_isr, savefailout);
944 V3_CHKPT_SAVE(ctx, "SLAVE_ISR", pic->slave_isr, savefailout);
946 V3_CHKPT_SAVE(ctx, "MASTER_ELCR", pic->master_elcr, savefailout);
947 V3_CHKPT_SAVE(ctx, "SLAVE_ELCR", pic->slave_elcr, savefailout);
948 V3_CHKPT_SAVE(ctx, "MASTER_ELCR_MASK", pic->master_elcr_mask, savefailout);
949 V3_CHKPT_SAVE(ctx, "SLAVE_ELCR_MASK", pic->slave_elcr_mask, savefailout);
951 V3_CHKPT_SAVE(ctx, "MASTER_ICW1", pic->master_icw1, savefailout);
952 V3_CHKPT_SAVE(ctx, "MASTER_ICW2", pic->master_icw2, savefailout);
953 V3_CHKPT_SAVE(ctx, "MASTER_ICW3", pic->master_icw3, savefailout);
954 V3_CHKPT_SAVE(ctx, "MASTER_ICW4", pic->master_icw4, savefailout);
957 V3_CHKPT_SAVE(ctx, "SLAVE_ICW1", pic->slave_icw1, savefailout);
958 V3_CHKPT_SAVE(ctx, "SLAVE_ICW2", pic->slave_icw2, savefailout);
959 V3_CHKPT_SAVE(ctx, "SLAVE_ICW3", pic->slave_icw3, savefailout);
960 V3_CHKPT_SAVE(ctx, "SLAVE_ICW4", pic->slave_icw4, savefailout);
963 V3_CHKPT_SAVE(ctx, "MASTER_IMR", pic->master_imr, savefailout);
964 V3_CHKPT_SAVE(ctx, "SLAVE_IMR", pic->slave_imr, savefailout);
965 V3_CHKPT_SAVE(ctx, "MASTER_OCW2", pic->master_ocw2, savefailout);
966 V3_CHKPT_SAVE(ctx, "MASTER_OCW3", pic->master_ocw3, savefailout);
967 V3_CHKPT_SAVE(ctx, "SLAVE_OCW2", pic->slave_ocw2, savefailout);
968 V3_CHKPT_SAVE(ctx, "SLAVE_OCW3", pic->slave_ocw3, savefailout);
970 V3_CHKPT_SAVE(ctx, "MASTER_STATE", pic->master_state, savefailout);
971 V3_CHKPT_SAVE(ctx, "SLAVE_STATE", pic->slave_state, savefailout);
977 PrintError(VM_NONE, VCORE_NONE, "Failed to save PIC\n");
982 static int pic_load(struct v3_chkpt_ctx * ctx, void * private_data) {
983 struct pic_internal * pic = (struct pic_internal *)private_data;
986 V3_CHKPT_LOAD(ctx, "MASTER_IRR", pic->master_irr, loadfailout);
987 V3_CHKPT_LOAD(ctx, "SLAVE_IRR", pic->slave_irr, loadfailout);
989 V3_CHKPT_LOAD(ctx, "MASTER_ISR", pic->master_isr, loadfailout);
990 V3_CHKPT_LOAD(ctx, "SLAVE_ISR", pic->slave_isr, loadfailout);
992 V3_CHKPT_LOAD(ctx, "MASTER_ELCR", pic->master_elcr, loadfailout);
993 V3_CHKPT_LOAD(ctx, "SLAVE_ELCR", pic->slave_elcr, loadfailout);
994 V3_CHKPT_LOAD(ctx, "MASTER_ELCR_MASK", pic->master_elcr_mask, loadfailout);
995 V3_CHKPT_LOAD(ctx, "SLAVE_ELCR_MASK", pic->slave_elcr_mask, loadfailout);
997 V3_CHKPT_LOAD(ctx, "MASTER_ICW1", pic->master_icw1, loadfailout);
998 V3_CHKPT_LOAD(ctx, "MASTER_ICW2", pic->master_icw2, loadfailout);
999 V3_CHKPT_LOAD(ctx, "MASTER_ICW3", pic->master_icw3, loadfailout);
1000 V3_CHKPT_LOAD(ctx, "MASTER_ICW4", pic->master_icw4, loadfailout);
1003 V3_CHKPT_LOAD(ctx, "SLAVE_ICW1", pic->slave_icw1, loadfailout);
1004 V3_CHKPT_LOAD(ctx, "SLAVE_ICW2", pic->slave_icw2, loadfailout);
1005 V3_CHKPT_LOAD(ctx, "SLAVE_ICW3", pic->slave_icw3, loadfailout);
1006 V3_CHKPT_LOAD(ctx, "SLAVE_ICW4", pic->slave_icw4, loadfailout);
1009 V3_CHKPT_LOAD(ctx, "MASTER_IMR", pic->master_imr, loadfailout);
1010 V3_CHKPT_LOAD(ctx, "SLAVE_IMR", pic->slave_imr, loadfailout);
1011 V3_CHKPT_LOAD(ctx, "MASTER_OCW2", pic->master_ocw2, loadfailout);
1012 V3_CHKPT_LOAD(ctx, "MASTER_OCW3", pic->master_ocw3, loadfailout);
1013 V3_CHKPT_LOAD(ctx, "SLAVE_OCW2", pic->slave_ocw2, loadfailout);
1014 V3_CHKPT_LOAD(ctx, "SLAVE_OCW3", pic->slave_ocw3, loadfailout);
1016 V3_CHKPT_LOAD(ctx, "MASTER_STATE", pic->master_state, loadfailout);
1017 V3_CHKPT_LOAD(ctx, "SLAVE_STATE", pic->slave_state, loadfailout);
1022 PrintError(VM_NONE, VCORE_NONE, "Failed to load PIC\n");
1029 static struct v3_device_ops dev_ops = {
1030 .free = (int (*)(void *))pic_free,
1031 #ifdef V3_CONFIG_CHECKPOINT
1041 static int pic_init(struct v3_vm_info * vm, v3_cfg_tree_t * cfg) {
1042 struct pic_internal * state = NULL;
1043 char * dev_id = v3_cfg_val(cfg, "ID");
1046 // PIC is only usable in non-multicore environments
1047 // just hardcode the core context
1048 struct guest_info * core = &(vm->cores[0]);
1050 state = (struct pic_internal *)V3_Malloc(sizeof(struct pic_internal));
1053 PrintError(vm, VCORE_NONE, "8259 PIC: Cannot allocate in init\n");
1057 struct vm_device * dev = v3_add_device(vm, dev_id, &dev_ops, state);
1060 PrintError(vm, VCORE_NONE, "8259 PIC: Could not add device %s\n", dev_id);
1067 state->controller_handle = v3_register_intr_controller(core, &intr_ops, state);
1068 state->router_handle = v3_register_intr_router(vm, &router_ops, state);
1070 state->master_irr = 0;
1071 state->master_isr = 0;
1072 state->master_elcr = 0;
1073 state->master_elcr_mask = 0xf8;
1074 state->master_icw1 = 0;
1075 state->master_icw2 = 0;
1076 state->master_icw3 = 0;
1077 state->master_icw4 = 0;
1078 state->master_imr = 0;
1079 state->master_ocw2 = 0;
1080 state->master_ocw3 = 0x02;
1081 state->master_state = ICW1;
1084 state->slave_irr = 0;
1085 state->slave_isr = 0;
1086 state->slave_elcr = 0;
1087 state->slave_elcr_mask = 0xde;
1088 state->slave_icw1 = 0;
1089 state->slave_icw2 = 0;
1090 state->slave_icw3 = 0;
1091 state->slave_icw4 = 0;
1092 state->slave_imr = 0;
1093 state->slave_ocw2 = 0;
1094 state->slave_ocw3 = 0x02;
1095 state->slave_state = ICW1;
1098 ret |= v3_dev_hook_io(dev, MASTER_PORT1, &read_master_port1, &write_master_port1);
1099 ret |= v3_dev_hook_io(dev, MASTER_PORT2, &read_master_port2, &write_master_port2);
1100 ret |= v3_dev_hook_io(dev, SLAVE_PORT1, &read_slave_port1, &write_slave_port1);
1101 ret |= v3_dev_hook_io(dev, SLAVE_PORT2, &read_slave_port2, &write_slave_port2);
1104 ret |= v3_dev_hook_io(dev, ELCR1_PORT, &read_elcr_port, &write_elcr_port);
1105 ret |= v3_dev_hook_io(dev, ELCR2_PORT, &read_elcr_port, &write_elcr_port);
1108 PrintError(vm, VCORE_NONE, "8259 PIC: Error hooking io ports\n");
1109 v3_remove_device(dev);
1118 device_register("8259A", pic_init);