2 * This file is part of the Palacios Virtual Machine Monitor developed
3 * by the V3VEE Project with funding from the United States National
4 * Science Foundation and the Department of Energy.
6 * The V3VEE Project is a joint project between Northwestern University
7 * and the University of New Mexico. You can find out more at
10 * Copyright (c) 2008, Jack Lange <jarusl@cs.northwestern.edu>
11 * Copyright (c) 2008, The V3VEE Project <http://www.v3vee.org>
12 * All rights reserved.
14 * Author: Jack Lange <jarusl@cs.northwestern.edu>
16 * This is free software. You are permitted to use,
17 * redistribute, and modify it as specified in the file "V3VEE_LICENSE".
21 #include <palacios/vmm.h>
22 #include <palacios/vmm_dev_mgr.h>
23 #include <palacios/vmm_time.h>
24 #include <palacios/vmm_util.h>
25 #include <palacios/vmm_intr.h>
26 #include <palacios/vmm_config.h>
27 #include <palacios/vmm_io.h>
30 #ifndef CONFIG_DEBUG_PIT
32 #define PrintDebug(fmt, args...)
38 #define OSC_HZ 1193182
41 /* The 8254 has three counters and one control port */
42 #define CHANNEL0_PORT 0x40
43 #define CHANNEL1_PORT 0x41
44 #define CHANNEL2_PORT 0x42
45 #define COMMAND_PORT 0x43
46 #define SPEAKER_PORT 0x61
49 #define PIT_INTR_NUM 0
50 #define PIT_SPEAKER_GATE 0x01
52 /* The order of these typedefs is important because the numerical values correspond to the
53 * values coming from the io ports
55 typedef enum {NOT_RUNNING, PENDING, RUNNING} channel_run_state_t;
56 typedef enum {NOT_WAITING, WAITING_LOBYTE, WAITING_HIBYTE} channel_access_state_t;
57 typedef enum {LATCH_COUNT, LOBYTE_ONLY, HIBYTE_ONLY, LOBYTE_HIBYTE} channel_access_mode_t;
58 typedef enum {IRQ_ON_TERM_CNT, ONE_SHOT, RATE_GEN, SQR_WAVE, SW_STROBE, HW_STROBE} channel_op_mode_t;
62 channel_access_mode_t access_mode;
63 channel_access_state_t access_state;
64 channel_run_state_t run_state;
66 channel_op_mode_t op_mode;
69 // Time til interrupt trigger
72 ushort_t reload_value;
74 ushort_t latched_value;
76 enum {NOTLATCHED, LATCHED} latch_state;
78 enum {LSB, MSB} read_state;
80 uint_t output_pin : 1;
81 uint_t gate_input_pin : 1;
90 struct v3_timer * timer;
102 uint_t access_mode : 2;
106 struct pit_rdb_cmd_word {
107 uint_t rsvd : 1; // SBZ
111 uint_t latch_status : 1;
112 uint_t latch_count : 1;
113 uint_t readback_cmd : 2; // Must Be 0x3
116 struct pit_rdb_status_word {
119 uint_t access_mode : 2;
120 uint_t null_count : 1;
121 uint_t pin_state : 1;
127 * This should call out to handle_SQR_WAVE_tics, etc...
129 // Returns true if the the output signal changed state
130 static int handle_crystal_tics(struct vm_device * dev, struct channel * ch, uint_t oscillations) {
131 uint_t channel_cycles = 0;
132 uint_t output_changed = 0;
134 // PrintDebug("8254 PIT: %d crystal tics\n", oscillations);
135 if (ch->run_state == PENDING) {
137 ch->counter = ch->reload_value;
139 if (ch->op_mode == SQR_WAVE) {
140 ch->counter -= ch->counter % 2;
143 ch->run_state = RUNNING;
144 } else if (ch->run_state != RUNNING) {
145 return output_changed;
149 PrintDebug("8254 PIT: Channel Run State = %d, counter=", ch->run_state);
150 PrintTraceLL(ch->counter);
153 if (ch->op_mode == SQR_WAVE) {
157 if (ch->counter > oscillations) {
158 ch->counter -= oscillations;
159 return output_changed;
161 ushort_t reload_val = ch->reload_value;
163 if (ch->op_mode == SW_STROBE) {
167 oscillations -= ch->counter;
171 if (ch->op_mode == SQR_WAVE) {
172 reload_val -= reload_val % 2;
175 // TODO: Check this....
176 // Is this correct???
177 if (reload_val == 0) {
181 channel_cycles += oscillations / reload_val;
182 oscillations = oscillations % reload_val;
184 ch->counter = reload_val - oscillations;
187 // PrintDebug("8254 PIT: Channel Cycles: %d\n", channel_cycles);
191 switch (ch->op_mode) {
192 case IRQ_ON_TERM_CNT:
193 if ((channel_cycles > 0) && (ch->output_pin == 0)) {
199 if ((channel_cycles > 0) && (ch->output_pin == 0)) {
205 // See the data sheet: we ignore the output pin cycle...
206 if (channel_cycles > 0) {
211 ch->output_pin = (ch->output_pin + 1) % 2;
213 if (ch->output_pin == 1) {
220 if (channel_cycles > 0) {
221 if (ch->output_pin == 1) {
228 PrintError("Hardware strobe not implemented\n");
235 return output_changed;
239 #include <palacios/vm_guest.h>
241 static void pit_update_timer(struct guest_info * info, ullong_t cpu_cycles, ullong_t cpu_freq, void * private_data) {
242 struct vm_device * dev = (struct vm_device *)private_data;
243 struct pit * state = (struct pit *)dev->private_data;
244 // ullong_t tmp_ctr = state->pit_counter;
246 uint_t oscillations = 0;
250 PrintDebug("updating cpu_cycles=");
251 PrintTraceLL(cpu_cycles);
254 PrintDebug("pit_counter=");
255 PrintTraceLL(state->pit_counter);
258 PrintDebug("pit_reload=");
259 PrintTraceLL(state->pit_reload);
263 if (state->pit_counter > cpu_cycles) {
265 state->pit_counter -= cpu_cycles;
267 ushort_t reload_val = state->pit_reload;
268 // Take off the first part
269 cpu_cycles -= state->pit_counter;
270 state->pit_counter = 0;
273 if (cpu_cycles > state->pit_reload) {
274 // how many full oscillations
276 //PrintError("cpu_cycles = %p, reload = %p...\n",
277 // (void *)(addr_t)cpu_cycles,
278 // (void *)(addr_t)state->pit_reload);
280 // How do we check for a one shot....
281 if (state->pit_reload == 0) {
285 tmp_cycles = cpu_cycles;
289 cpu_cycles = tmp_cycles % state->pit_reload;
290 tmp_cycles = tmp_cycles / state->pit_reload;
292 cpu_cycles = do_divll(tmp_cycles, state->pit_reload);
295 oscillations += tmp_cycles;
298 // update counter with remainder (mod reload)
299 state->pit_counter = state->pit_reload - cpu_cycles;
301 //PrintDebug("8254 PIT: Handling %d crystal tics\n", oscillations);
302 if (handle_crystal_tics(dev, &(state->ch_0), oscillations) == 1) {
304 PrintDebug("8254 PIT: Injecting Timer interrupt to guest\n");
305 v3_raise_irq(info->vm_info, 0);
308 //handle_crystal_tics(dev, &(state->ch_1), oscillations);
309 handle_crystal_tics(dev, &(state->ch_2), oscillations);
318 /* This should call out to handle_SQR_WAVE_write, etc...
320 static int handle_channel_write(struct channel * ch, char val) {
322 switch (ch->access_state) {
325 ushort_t tmp_val = ((ushort_t)val) << 8;
326 ch->reload_value &= 0x00ff;
327 ch->reload_value |= tmp_val;
330 if ((ch->op_mode != RATE_GEN) || (ch->run_state != RUNNING)){
331 ch->run_state = PENDING;
334 if (ch->access_mode == LOBYTE_HIBYTE) {
335 ch->access_state = WAITING_LOBYTE;
338 PrintDebug("8254 PIT: updated channel counter: %d\n", ch->reload_value);
339 PrintDebug("8254 PIT: Channel Run State=%d\n", ch->run_state);
343 ch->reload_value &= 0xff00;
344 ch->reload_value |= val;
346 if (ch->access_mode == LOBYTE_HIBYTE) {
347 ch->access_state = WAITING_HIBYTE;
348 } else if ((ch->op_mode != RATE_GEN) || (ch->run_state != RUNNING)) {
349 ch->run_state = PENDING;
352 PrintDebug("8254 PIT: updated channel counter: %d\n", ch->reload_value);
353 PrintDebug("8254 PIT: Channel Run State=%d\n", ch->run_state);
356 PrintError("Invalid Access state\n");
361 switch (ch->op_mode) {
362 case IRQ_ON_TERM_CNT:
378 PrintError("Invalid OP_MODE: %d\n", ch->op_mode);
388 static int handle_channel_read(struct channel * ch, char * val) {
392 if (ch->latch_state == NOTLATCHED) {
393 myval = &(ch->counter);
395 myval = &(ch->latched_value);
398 if (ch->read_state == LSB) {
399 *val = ((char*)myval)[0]; // little endian
400 ch->read_state = MSB;
402 *val = ((char*)myval)[1];
403 ch->read_state = LSB;
404 if (ch->latch_state == LATCHED) {
405 ch->latch_state = NOTLATCHED;
413 static int handle_speaker_read(uint8_t *speaker, struct channel * ch, char * val) {
416 if ((*speaker & PIT_SPEAKER_GATE)) {
417 *val |= (ch->output_pin << 5);
423 static int handle_speaker_write(uint8_t *speaker, struct channel * ch, char val) {
424 *speaker = (val & ~0x20);
428 static int handle_channel_cmd(struct channel * ch, struct pit_cmd_word cmd) {
429 ch->op_mode = cmd.op_mode;
430 ch->access_mode = cmd.access_mode;
435 switch (cmd.access_mode) {
437 if (ch->latch_state == NOTLATCHED) {
438 ch->latched_value = ch->counter;
439 ch->latch_state = LATCHED;
443 ch->access_state = WAITING_HIBYTE;
447 ch->access_state = WAITING_LOBYTE;
452 switch (cmd.op_mode) {
453 case IRQ_ON_TERM_CNT:
469 PrintError("Invalid OP_MODE: %d\n", cmd.op_mode);
480 static int pit_read_channel(struct guest_info * core, ushort_t port, void * dst, uint_t length, void * priv_data) {
481 struct vm_device * dev = (struct vm_device *)priv_data;
482 struct pit * state = (struct pit *)dev->private_data;
483 char * val = (char *)dst;
486 PrintError("8254 PIT: Invalid Read Write length \n");
490 PrintDebug("8254 PIT: Read of PIT Channel %d\n", port - CHANNEL0_PORT);
494 if (handle_channel_read(&(state->ch_0), val) == -1) {
495 PrintError("CHANNEL0 read error\n");
500 if (handle_channel_read(&(state->ch_1), val) == -1) {
501 PrintError("CHANNEL1 read error\n");
506 if (handle_channel_read(&(state->ch_2), val) == -1) {
507 PrintError("CHANNEL2 read error\n");
512 if (handle_speaker_read(&state->speaker, &(state->ch_2), val) == -1) {
513 PrintError("SPEAKER read error\n");
518 PrintError("8254 PIT: Read from invalid port (%d)\n", port);
527 static int pit_write_channel(struct guest_info * core, ushort_t port, void * src, uint_t length, void * priv_data) {
528 struct vm_device * dev = (struct vm_device *)priv_data;
529 struct pit * state = (struct pit *)dev->private_data;
530 char val = *(char *)src;
533 PrintError("8254 PIT: Invalid Write Length\n");
537 PrintDebug("8254 PIT: Write to PIT Channel %d (%x)\n", port - CHANNEL0_PORT, *(char*)src);
542 if (handle_channel_write(&(state->ch_0), val) == -1) {
543 PrintError("CHANNEL0 write error\n");
548 if (handle_channel_write(&(state->ch_1), val) == -1) {
549 PrintError("CHANNEL1 write error\n");
554 if (handle_channel_write(&(state->ch_2), val) == -1) {
555 PrintError("CHANNEL2 write error\n");
560 if (handle_speaker_write(&state->speaker, &(state->ch_2), val) == -1) {
561 PrintError("SPEAKER write error\n");
566 PrintError("8254 PIT: Write to invalid port (%d)\n", port);
576 static int pit_write_command(struct guest_info * core, ushort_t port, void * src, uint_t length, void * priv_data) {
577 struct vm_device * dev = (struct vm_device *)priv_data;
578 struct pit * state = (struct pit *)dev->private_data;
579 struct pit_cmd_word * cmd = (struct pit_cmd_word *)src;
581 PrintDebug("8254 PIT: Write to PIT Command port\n");
582 PrintDebug("8254 PIT: Writing to channel %d (access_mode = %d, op_mode = %d)\n", cmd->channel, cmd->access_mode, cmd->op_mode);
584 PrintError("8254 PIT: Write of Invalid length to command port\n");
588 switch (cmd->channel) {
590 if (handle_channel_cmd(&(state->ch_0), *cmd) == -1) {
591 PrintError("CHANNEL0 command error\n");
596 if (handle_channel_cmd(&(state->ch_1), *cmd) == -1) {
597 PrintError("CHANNEL1 command error\n");
602 if (handle_channel_cmd(&(state->ch_2), *cmd) == -1) {
603 PrintError("CHANNEL2 command error\n");
609 PrintError("Read back command not implemented\n");
623 static struct v3_timer_ops timer_ops = {
624 .update_timer = pit_update_timer,
628 static void init_channel(struct channel * ch) {
629 ch->run_state = NOT_RUNNING;
630 ch->access_state = NOT_WAITING;
635 ch->reload_value = 0;
637 ch->gate_input_pin = 0;
639 ch->latched_value = 0;
640 ch->latch_state = NOTLATCHED;
641 ch->read_state = LSB;
649 static int pit_free(struct vm_device * dev) {
650 struct pit * state = (struct pit *)dev->private_data;
651 struct guest_info * info = &(dev->vm->cores[0]);
655 v3_remove_timer(info, state->timer);
658 v3_unhook_io_port(dev->vm, CHANNEL0_PORT);
659 v3_unhook_io_port(dev->vm, CHANNEL1_PORT);
660 v3_unhook_io_port(dev->vm, CHANNEL2_PORT);
661 v3_unhook_io_port(dev->vm, COMMAND_PORT);
662 v3_unhook_io_port(dev->vm, SPEAKER_PORT);
669 static struct v3_device_ops dev_ops = {
677 #include <palacios/vm_guest.h>
679 static int pit_init(struct v3_vm_info * vm, v3_cfg_tree_t * cfg) {
680 struct pit * pit_state = NULL;
681 struct vm_device * dev = NULL;
682 char * dev_id = v3_cfg_val(cfg, "ID");
684 // PIT is only usable in non-multicore environments
685 // just hardcode the core context
686 struct guest_info * info = &(vm->cores[0]);
688 uint_t cpu_khz = V3_CPU_KHZ();
689 ullong_t reload_val = (ullong_t)cpu_khz * 1000;
691 pit_state = (struct pit *)V3_Malloc(sizeof(struct pit));
692 V3_ASSERT(pit_state != NULL);
693 pit_state->speaker = 0;
695 dev = v3_allocate_device(dev_id, &dev_ops, pit_state);
697 if (v3_attach_device(vm, dev) == -1) {
698 PrintError("Could not attach device %s\n", dev_id);
702 v3_hook_io_port(vm, CHANNEL0_PORT, &pit_read_channel, &pit_write_channel, dev);
703 v3_hook_io_port(vm, CHANNEL1_PORT, &pit_read_channel, &pit_write_channel, dev);
704 v3_hook_io_port(vm, CHANNEL2_PORT, &pit_read_channel, &pit_write_channel, dev);
705 v3_hook_io_port(vm, COMMAND_PORT, NULL, &pit_write_command, dev);
706 v3_hook_io_port(vm, SPEAKER_PORT, &pit_read_channel, &pit_write_channel, dev);
708 #ifdef CONFIG_DEBUG_PIT
709 PrintDebug("8254 PIT: OSC_HZ=%d, reload_val=", OSC_HZ);
710 //PrintTrace(reload_val);
716 pit_state->timer = v3_add_timer(info, &timer_ops, dev);
718 if (pit_state->timer == NULL) {
719 v3_detach_device(dev);
723 // Get cpu frequency and calculate the global pit oscilattor counter/cycle
725 do_divll(reload_val, OSC_HZ);
726 pit_state->pit_counter = reload_val;
727 pit_state->pit_reload = reload_val;
731 init_channel(&(pit_state->ch_0));
732 init_channel(&(pit_state->ch_1));
733 init_channel(&(pit_state->ch_2));
735 #ifdef CONFIG_DEBUG_PIT
736 PrintDebug("8254 PIT: CPU MHZ=%d -- pit count=", cpu_khz / 1000);
737 //PrintTraceLL(pit_state->pit_counter);
745 device_register("8254_PIT", pit_init);