1 #include <devices/8254.h>
2 #include <palacios/vmm.h>
3 #include <palacios/vmm_time.h>
4 #include <palacios/vmm_util.h>
5 #include <palacios/vmm_intr.h>
11 #define PrintDebug(fmt, args...)
17 #define OSC_HZ 1193182
20 /* The 8254 has three counters and one control port */
21 #define CHANNEL0_PORT 0x40
22 #define CHANNEL1_PORT 0x41
23 #define CHANNEL2_PORT 0x42
24 #define COMMAND_PORT 0x43
27 #define PIT_INTR_NUM 0
29 /* The order of these typedefs is important because the numerical values correspond to the
30 * values coming from the io ports
32 typedef enum {NOT_RUNNING, PENDING, RUNNING} channel_run_state_t;
33 typedef enum {NOT_WAITING, WAITING_LOBYTE, WAITING_HIBYTE} channel_access_state_t;
34 typedef enum {LATCH_COUNT, LOBYTE_ONLY, HIBYTE_ONLY, LOBYTE_HIBYTE} channel_access_mode_t;
35 typedef enum {IRQ_ON_TERM_CNT, ONE_SHOT, RATE_GEN, SQR_WAVE, SW_STROBE, HW_STROBE} channel_op_mode_t;
39 channel_access_mode_t access_mode;
40 channel_access_state_t access_state;
41 channel_run_state_t run_state;
43 channel_op_mode_t op_mode;
46 // Time til interrupt trigger
49 ushort_t reload_value;
51 ushort_t latched_value;
53 enum {NOTLATCHED, LATCHED} latch_state;
55 enum {LSB, MSB} read_state;
57 uint_t output_pin : 1;
58 uint_t gate_input_pin : 1;
77 uint_t access_mode : 2;
81 struct pit_rdb_cmd_word {
82 uint_t rsvd : 1; // SBZ
86 uint_t latch_status : 1;
87 uint_t latch_count : 1;
88 uint_t readback_cmd : 2; // Must Be 0x3
91 struct pit_rdb_status_word {
94 uint_t access_mode : 2;
95 uint_t null_count : 1;
102 * This should call out to handle_SQR_WAVE_tics, etc...
104 // Returns true if the the output signal changed state
105 static int handle_crystal_tics(struct vm_device * dev, struct channel * ch, uint_t oscillations) {
106 uint_t channel_cycles = 0;
107 uint_t output_changed = 0;
109 // PrintDebug("8254 PIT: %d crystal tics\n", oscillations);
110 if (ch->run_state == PENDING) {
112 ch->counter = ch->reload_value;
114 if (ch->op_mode == SQR_WAVE) {
115 ch->counter -= ch->counter % 2;
118 ch->run_state = RUNNING;
119 } else if (ch->run_state != RUNNING) {
120 return output_changed;
124 PrintDebug("8254 PIT: Channel Run State = %d, counter=", ch->run_state);
125 PrintTraceLL(ch->counter);
128 if (ch->op_mode == SQR_WAVE) {
132 if (ch->counter > oscillations) {
133 ch->counter -= oscillations;
134 return output_changed;
136 ushort_t reload_val = ch->reload_value;
137 oscillations -= ch->counter;
142 if (ch->op_mode == SQR_WAVE) {
143 reload_val -= reload_val % 2;
146 channel_cycles += oscillations / reload_val;
147 oscillations = oscillations % reload_val;
149 ch->counter = reload_val - oscillations;
152 // PrintDebug("8254 PIT: Channel Cycles: %d\n", channel_cycles);
156 switch (ch->op_mode) {
157 case IRQ_ON_TERM_CNT:
158 if ((channel_cycles > 0) && (ch->output_pin == 0)) {
164 if ((channel_cycles > 0) && (ch->output_pin == 0)) {
170 // See the data sheet: we ignore the output pin cycle...
171 if (channel_cycles > 0) {
176 ch->output_pin = (ch->output_pin + 1) % 2;
178 if (ch->output_pin == 1) {
193 return output_changed;
198 static void pit_update_time(ullong_t cpu_cycles, ullong_t cpu_freq, void * private_data) {
199 struct vm_device * dev = (struct vm_device *)private_data;
200 struct pit * state = (struct pit *)dev->private_data;
201 // ullong_t tmp_ctr = state->pit_counter;
203 uint_t oscillations = 0;
207 PrintDebug("updating cpu_cycles=");
208 PrintTraceLL(cpu_cycles);
211 PrintDebug("pit_counter=");
212 PrintTraceLL(state->pit_counter);
215 PrintDebug("pit_reload=");
216 PrintTraceLL(state->pit_reload);
220 if (state->pit_counter > cpu_cycles) {
222 state->pit_counter -= cpu_cycles;
225 // Take off the first part
226 cpu_cycles -= state->pit_counter;
227 state->pit_counter = 0;
230 if (cpu_cycles > state->pit_reload) {
231 // how many full oscillations
232 tmp_cycles = cpu_cycles;
234 cpu_cycles = do_divll(tmp_cycles, state->pit_reload);
236 oscillations += tmp_cycles;
239 // update counter with remainder (mod reload)
240 state->pit_counter = state->pit_reload - cpu_cycles;
242 //PrintDebug("8254 PIT: Handling %d crystal tics\n", oscillations);
243 if (handle_crystal_tics(dev, &(state->ch_0), oscillations) == 1) {
245 PrintDebug("8254 PIT: Injecting Timer interrupt to guest\n");
246 v3_raise_irq(dev->vm, 0);
249 //handle_crystal_tics(dev, &(state->ch_1), oscillations);
250 //handle_crystal_tics(dev, &(state->ch_2), oscillations);
261 /* This should call out to handle_SQR_WAVE_write, etc...
263 static int handle_channel_write(struct channel * ch, char val) {
265 switch (ch->access_state) {
268 ushort_t tmp_val = ((ushort_t)val) << 8;
269 ch->reload_value &= 0x00ff;
270 ch->reload_value |= tmp_val;
273 if ((ch->op_mode != RATE_GEN) || (ch->run_state != RUNNING)){
274 ch->run_state = PENDING;
277 if (ch->access_mode == LOBYTE_HIBYTE) {
278 ch->access_state = WAITING_LOBYTE;
281 PrintDebug("8254 PIT: updated channel counter: %d\n", ch->reload_value);
282 PrintDebug("8254 PIT: Channel Run State=%d\n", ch->run_state);
286 ch->reload_value &= 0xff00;
287 ch->reload_value |= val;
289 if (ch->access_mode == LOBYTE_HIBYTE) {
290 ch->access_state = WAITING_HIBYTE;
291 } else if ((ch->op_mode != RATE_GEN) || (ch->run_state != RUNNING)) {
292 ch->run_state = PENDING;
295 PrintDebug("8254 PIT: updated channel counter: %d\n", ch->reload_value);
296 PrintDebug("8254 PIT: Channel Run State=%d\n", ch->run_state);
303 switch (ch->op_mode) {
304 case IRQ_ON_TERM_CNT:
326 static int handle_channel_read(struct channel * ch, char * val) {
330 if (ch->latch_state == NOTLATCHED) {
331 myval = &(ch->counter);
333 myval = &(ch->latched_value);
336 if (ch->read_state == LSB) {
337 *val = ((char*)myval)[0]; // little endian
338 ch->read_state = MSB;
340 *val = ((char*)myval)[1];
341 ch->read_state = LSB;
342 if (ch->latch_state == LATCHED) {
343 ch->latch_state = NOTLATCHED;
355 static int handle_channel_cmd(struct channel * ch, struct pit_cmd_word cmd) {
356 ch->op_mode = cmd.op_mode;
357 ch->access_mode = cmd.access_mode;
362 switch (cmd.access_mode) {
364 if (ch->latch_state == NOTLATCHED) {
365 ch->latched_value = ch->counter;
366 ch->latch_state = LATCHED;
370 ch->access_state = WAITING_HIBYTE;
374 ch->access_state = WAITING_LOBYTE;
379 switch (cmd.op_mode) {
380 case IRQ_ON_TERM_CNT:
403 static int pit_read_channel(ushort_t port, void * dst, uint_t length, struct vm_device * dev) {
404 struct pit * state = (struct pit *)dev->private_data;
405 char * val = (char *)dst;
408 PrintError("8254 PIT: Invalid Read Write length \n");
412 PrintDebug("8254 PIT: Read of PIT Channel %d\n", port - CHANNEL0_PORT);
416 if (handle_channel_read(&(state->ch_0), val) == -1) {
421 if (handle_channel_read(&(state->ch_1), val) == -1) {
426 if (handle_channel_read(&(state->ch_2), val) == -1) {
431 PrintError("8254 PIT: Read from invalid port (%d)\n", port);
440 static int pit_write_channel(ushort_t port, void * src, uint_t length, struct vm_device * dev) {
441 struct pit * state = (struct pit *)dev->private_data;
442 char val = *(char *)src;
445 PrintError("8254 PIT: Invalid Write Length\n");
449 PrintDebug("8254 PIT: Write to PIT Channel %d (%x)\n", port - CHANNEL0_PORT, *(char*)src);
454 if (handle_channel_write(&(state->ch_0), val) == -1) {
459 if (handle_channel_write(&(state->ch_1), val) == -1) {
464 if (handle_channel_write(&(state->ch_2), val) == -1) {
469 PrintError("8254 PIT: Write to invalid port (%d)\n", port);
479 static int pit_write_command(ushort_t port, void * src, uint_t length, struct vm_device * dev) {
480 struct pit * state = (struct pit *)dev->private_data;
481 struct pit_cmd_word * cmd = (struct pit_cmd_word *)src;
483 PrintDebug("8254 PIT: Write to PIT Command port\n");
484 PrintDebug("8254 PIT: Writing to channel %d (access_mode = %d, op_mode = %d)\n", cmd->channel, cmd->access_mode, cmd->op_mode);
486 PrintError("8254 PIT: Write of Invalid length to command port\n");
490 switch (cmd->channel) {
492 if (handle_channel_cmd(&(state->ch_0), *cmd) == -1) {
497 if (handle_channel_cmd(&(state->ch_1), *cmd) == -1) {
502 if (handle_channel_cmd(&(state->ch_2), *cmd) == -1) {
521 static struct vm_timer_ops timer_ops = {
522 .update_time = pit_update_time,
526 static void init_channel(struct channel * ch) {
527 ch->run_state = NOT_RUNNING;
528 ch->access_state = NOT_WAITING;
533 ch->reload_value = 0;
535 ch->gate_input_pin = 0;
537 ch->latched_value = 0;
538 ch->latch_state = NOTLATCHED;
539 ch->read_state = LSB;
545 static int pit_init(struct vm_device * dev) {
546 struct pit * state = (struct pit *)dev->private_data;
547 uint_t cpu_khz = V3_CPU_KHZ();
548 ullong_t reload_val = (ullong_t)cpu_khz * 1000;
550 dev_hook_io(dev, CHANNEL0_PORT, &pit_read_channel, &pit_write_channel);
551 dev_hook_io(dev, CHANNEL1_PORT, &pit_read_channel, &pit_write_channel);
552 dev_hook_io(dev, CHANNEL2_PORT, &pit_read_channel, &pit_write_channel);
553 dev_hook_io(dev, COMMAND_PORT, NULL, &pit_write_command);
556 PrintDebug("8254 PIT: OSC_HZ=%d, reload_val=", OSC_HZ);
557 PrintTraceLL(reload_val);
561 v3_add_timer(dev->vm, &timer_ops, dev);
563 // Get cpu frequency and calculate the global pit oscilattor counter/cycle
565 do_divll(reload_val, OSC_HZ);
566 state->pit_counter = reload_val;
567 state->pit_reload = reload_val;
571 init_channel(&(state->ch_0));
572 init_channel(&(state->ch_1));
573 init_channel(&(state->ch_2));
576 PrintDebug("8254 PIT: CPU MHZ=%d -- pit count=", cpu_khz / 1000);
577 PrintTraceLL(state->pit_counter);
584 static int pit_deinit(struct vm_device * dev) {
590 static struct vm_device_ops dev_ops = {
592 .deinit = pit_deinit,
600 struct vm_device * create_pit() {
601 struct pit * pit_state = NULL;
602 pit_state = (struct pit *)V3_Malloc(sizeof(struct pit));
603 V3_ASSERT(pit_state != NULL);
605 struct vm_device * dev = create_device("PIT", &dev_ops, pit_state);