2 * This file is part of the Palacios Virtual Machine Monitor developed
3 * by the V3VEE Project with funding from the United States National
4 * Science Foundation and the Department of Energy.
6 * The V3VEE Project is a joint project between Northwestern University
7 * and the University of New Mexico. You can find out more at
10 * Copyright (c) 2008, Jack Lange <jarusl@cs.northwestern.edu>
11 * Copyright (c) 2008, The V3VEE Project <http://www.v3vee.org>
12 * All rights reserved.
14 * Author: Jack Lange <jarusl@cs.northwestern.edu>
16 * This is free software. You are permitted to use,
17 * redistribute, and modify it as specified in the file "V3VEE_LICENSE".
20 #include <devices/8254.h>
21 #include <palacios/vmm.h>
22 #include <palacios/vmm_time.h>
23 #include <palacios/vmm_util.h>
24 #include <palacios/vmm_intr.h>
30 #define PrintDebug(fmt, args...)
36 #define OSC_HZ 1193182
39 /* The 8254 has three counters and one control port */
40 #define CHANNEL0_PORT 0x40
41 #define CHANNEL1_PORT 0x41
42 #define CHANNEL2_PORT 0x42
43 #define COMMAND_PORT 0x43
46 #define PIT_INTR_NUM 0
48 /* The order of these typedefs is important because the numerical values correspond to the
49 * values coming from the io ports
51 typedef enum {NOT_RUNNING, PENDING, RUNNING} channel_run_state_t;
52 typedef enum {NOT_WAITING, WAITING_LOBYTE, WAITING_HIBYTE} channel_access_state_t;
53 typedef enum {LATCH_COUNT, LOBYTE_ONLY, HIBYTE_ONLY, LOBYTE_HIBYTE} channel_access_mode_t;
54 typedef enum {IRQ_ON_TERM_CNT, ONE_SHOT, RATE_GEN, SQR_WAVE, SW_STROBE, HW_STROBE} channel_op_mode_t;
58 channel_access_mode_t access_mode;
59 channel_access_state_t access_state;
60 channel_run_state_t run_state;
62 channel_op_mode_t op_mode;
65 // Time til interrupt trigger
68 ushort_t reload_value;
70 ushort_t latched_value;
72 enum {NOTLATCHED, LATCHED} latch_state;
74 enum {LSB, MSB} read_state;
76 uint_t output_pin : 1;
77 uint_t gate_input_pin : 1;
96 uint_t access_mode : 2;
100 struct pit_rdb_cmd_word {
101 uint_t rsvd : 1; // SBZ
105 uint_t latch_status : 1;
106 uint_t latch_count : 1;
107 uint_t readback_cmd : 2; // Must Be 0x3
110 struct pit_rdb_status_word {
113 uint_t access_mode : 2;
114 uint_t null_count : 1;
115 uint_t pin_state : 1;
121 * This should call out to handle_SQR_WAVE_tics, etc...
123 // Returns true if the the output signal changed state
124 static int handle_crystal_tics(struct vm_device * dev, struct channel * ch, uint_t oscillations) {
125 uint_t channel_cycles = 0;
126 uint_t output_changed = 0;
128 // PrintDebug("8254 PIT: %d crystal tics\n", oscillations);
129 if (ch->run_state == PENDING) {
131 ch->counter = ch->reload_value;
133 if (ch->op_mode == SQR_WAVE) {
134 ch->counter -= ch->counter % 2;
137 ch->run_state = RUNNING;
138 } else if (ch->run_state != RUNNING) {
139 return output_changed;
143 PrintDebug("8254 PIT: Channel Run State = %d, counter=", ch->run_state);
144 PrintTraceLL(ch->counter);
147 if (ch->op_mode == SQR_WAVE) {
151 if (ch->counter > oscillations) {
152 ch->counter -= oscillations;
153 return output_changed;
155 ushort_t reload_val = ch->reload_value;
157 // TODO: Check this....
158 // Is this correct???
159 if (reload_val == 0) {
163 oscillations -= ch->counter;
167 if (ch->op_mode == SQR_WAVE) {
168 reload_val -= reload_val % 2;
171 channel_cycles += oscillations / reload_val;
172 oscillations = oscillations % reload_val;
174 ch->counter = reload_val - oscillations;
177 // PrintDebug("8254 PIT: Channel Cycles: %d\n", channel_cycles);
181 switch (ch->op_mode) {
182 case IRQ_ON_TERM_CNT:
183 if ((channel_cycles > 0) && (ch->output_pin == 0)) {
189 if ((channel_cycles > 0) && (ch->output_pin == 0)) {
195 // See the data sheet: we ignore the output pin cycle...
196 if (channel_cycles > 0) {
201 ch->output_pin = (ch->output_pin + 1) % 2;
203 if (ch->output_pin == 1) {
209 PrintError("Software strobe not implemented\n");
213 PrintError("Hardware strobe not implemented\n");
220 return output_changed;
225 static void pit_update_time(ullong_t cpu_cycles, ullong_t cpu_freq, void * private_data) {
226 struct vm_device * dev = (struct vm_device *)private_data;
227 struct pit * state = (struct pit *)dev->private_data;
228 // ullong_t tmp_ctr = state->pit_counter;
230 uint_t oscillations = 0;
234 PrintDebug("updating cpu_cycles=");
235 PrintTraceLL(cpu_cycles);
238 PrintDebug("pit_counter=");
239 PrintTraceLL(state->pit_counter);
242 PrintDebug("pit_reload=");
243 PrintTraceLL(state->pit_reload);
247 if (state->pit_counter > cpu_cycles) {
249 state->pit_counter -= cpu_cycles;
251 ushort_t reload_val = state->pit_reload;
252 // Take off the first part
253 cpu_cycles -= state->pit_counter;
254 state->pit_counter = 0;
257 if (cpu_cycles > state->pit_reload) {
258 // how many full oscillations
260 //PrintError("cpu_cycles = %p, reload = %p...\n",
261 // (void *)(addr_t)cpu_cycles,
262 // (void *)(addr_t)state->pit_reload);
264 // How do we check for a one shot....
265 if (state->pit_reload == 0) {
269 tmp_cycles = cpu_cycles;
273 cpu_cycles = tmp_cycles % state->pit_reload;
274 tmp_cycles = tmp_cycles / state->pit_reload;
276 cpu_cycles = do_divll(tmp_cycles, state->pit_reload);
279 oscillations += tmp_cycles;
282 // update counter with remainder (mod reload)
283 state->pit_counter = state->pit_reload - cpu_cycles;
285 //PrintDebug("8254 PIT: Handling %d crystal tics\n", oscillations);
286 if (handle_crystal_tics(dev, &(state->ch_0), oscillations) == 1) {
288 PrintDebug("8254 PIT: Injecting Timer interrupt to guest\n");
289 v3_raise_irq(dev->vm, 0);
292 //handle_crystal_tics(dev, &(state->ch_1), oscillations);
293 //handle_crystal_tics(dev, &(state->ch_2), oscillations);
304 /* This should call out to handle_SQR_WAVE_write, etc...
306 static int handle_channel_write(struct channel * ch, char val) {
308 switch (ch->access_state) {
311 ushort_t tmp_val = ((ushort_t)val) << 8;
312 ch->reload_value &= 0x00ff;
313 ch->reload_value |= tmp_val;
316 if ((ch->op_mode != RATE_GEN) || (ch->run_state != RUNNING)){
317 ch->run_state = PENDING;
320 if (ch->access_mode == LOBYTE_HIBYTE) {
321 ch->access_state = WAITING_LOBYTE;
324 PrintDebug("8254 PIT: updated channel counter: %d\n", ch->reload_value);
325 PrintDebug("8254 PIT: Channel Run State=%d\n", ch->run_state);
329 ch->reload_value &= 0xff00;
330 ch->reload_value |= val;
332 if (ch->access_mode == LOBYTE_HIBYTE) {
333 ch->access_state = WAITING_HIBYTE;
334 } else if ((ch->op_mode != RATE_GEN) || (ch->run_state != RUNNING)) {
335 ch->run_state = PENDING;
338 PrintDebug("8254 PIT: updated channel counter: %d\n", ch->reload_value);
339 PrintDebug("8254 PIT: Channel Run State=%d\n", ch->run_state);
342 PrintError("Invalid Access state\n");
347 switch (ch->op_mode) {
348 case IRQ_ON_TERM_CNT:
361 PrintError("Invalid OP_MODE: %d\n", ch->op_mode);
371 static int handle_channel_read(struct channel * ch, char * val) {
375 if (ch->latch_state == NOTLATCHED) {
376 myval = &(ch->counter);
378 myval = &(ch->latched_value);
381 if (ch->read_state == LSB) {
382 *val = ((char*)myval)[0]; // little endian
383 ch->read_state = MSB;
385 *val = ((char*)myval)[1];
386 ch->read_state = LSB;
387 if (ch->latch_state == LATCHED) {
388 ch->latch_state = NOTLATCHED;
400 static int handle_channel_cmd(struct channel * ch, struct pit_cmd_word cmd) {
401 ch->op_mode = cmd.op_mode;
402 ch->access_mode = cmd.access_mode;
407 switch (cmd.access_mode) {
409 if (ch->latch_state == NOTLATCHED) {
410 ch->latched_value = ch->counter;
411 ch->latch_state = LATCHED;
415 ch->access_state = WAITING_HIBYTE;
419 ch->access_state = WAITING_LOBYTE;
424 switch (cmd.op_mode) {
425 case IRQ_ON_TERM_CNT:
438 PrintError("Invalid OP_MODE: %d\n", cmd.op_mode);
449 static int pit_read_channel(ushort_t port, void * dst, uint_t length, struct vm_device * dev) {
450 struct pit * state = (struct pit *)dev->private_data;
451 char * val = (char *)dst;
454 PrintError("8254 PIT: Invalid Read Write length \n");
458 PrintDebug("8254 PIT: Read of PIT Channel %d\n", port - CHANNEL0_PORT);
462 if (handle_channel_read(&(state->ch_0), val) == -1) {
463 PrintError("CHANNEL0 read error\n");
468 if (handle_channel_read(&(state->ch_1), val) == -1) {
469 PrintError("CHANNEL1 read error\n");
474 if (handle_channel_read(&(state->ch_2), val) == -1) {
475 PrintError("CHANNEL2 read error\n");
480 PrintError("8254 PIT: Read from invalid port (%d)\n", port);
489 static int pit_write_channel(ushort_t port, void * src, uint_t length, struct vm_device * dev) {
490 struct pit * state = (struct pit *)dev->private_data;
491 char val = *(char *)src;
494 PrintError("8254 PIT: Invalid Write Length\n");
498 PrintDebug("8254 PIT: Write to PIT Channel %d (%x)\n", port - CHANNEL0_PORT, *(char*)src);
503 if (handle_channel_write(&(state->ch_0), val) == -1) {
504 PrintError("CHANNEL0 write error\n");
509 if (handle_channel_write(&(state->ch_1), val) == -1) {
510 PrintError("CHANNEL1 write error\n");
515 if (handle_channel_write(&(state->ch_2), val) == -1) {
516 PrintError("CHANNEL2 write error\n");
521 PrintError("8254 PIT: Write to invalid port (%d)\n", port);
531 static int pit_write_command(ushort_t port, void * src, uint_t length, struct vm_device * dev) {
532 struct pit * state = (struct pit *)dev->private_data;
533 struct pit_cmd_word * cmd = (struct pit_cmd_word *)src;
535 PrintDebug("8254 PIT: Write to PIT Command port\n");
536 PrintDebug("8254 PIT: Writing to channel %d (access_mode = %d, op_mode = %d)\n", cmd->channel, cmd->access_mode, cmd->op_mode);
538 PrintError("8254 PIT: Write of Invalid length to command port\n");
542 switch (cmd->channel) {
544 if (handle_channel_cmd(&(state->ch_0), *cmd) == -1) {
545 PrintError("CHANNEL0 command error\n");
550 if (handle_channel_cmd(&(state->ch_1), *cmd) == -1) {
551 PrintError("CHANNEL1 command error\n");
556 if (handle_channel_cmd(&(state->ch_2), *cmd) == -1) {
557 PrintError("CHANNEL2 command error\n");
563 PrintError("Read back command not implemented\n");
577 static struct vm_timer_ops timer_ops = {
578 .update_time = pit_update_time,
582 static void init_channel(struct channel * ch) {
583 ch->run_state = NOT_RUNNING;
584 ch->access_state = NOT_WAITING;
589 ch->reload_value = 0;
591 ch->gate_input_pin = 0;
593 ch->latched_value = 0;
594 ch->latch_state = NOTLATCHED;
595 ch->read_state = LSB;
601 static int pit_init(struct vm_device * dev) {
602 struct pit * state = (struct pit *)dev->private_data;
603 uint_t cpu_khz = V3_CPU_KHZ();
604 ullong_t reload_val = (ullong_t)cpu_khz * 1000;
606 v3_dev_hook_io(dev, CHANNEL0_PORT, &pit_read_channel, &pit_write_channel);
607 v3_dev_hook_io(dev, CHANNEL1_PORT, &pit_read_channel, &pit_write_channel);
608 v3_dev_hook_io(dev, CHANNEL2_PORT, &pit_read_channel, &pit_write_channel);
609 v3_dev_hook_io(dev, COMMAND_PORT, NULL, &pit_write_command);
612 PrintDebug("8254 PIT: OSC_HZ=%d, reload_val=", OSC_HZ);
613 PrintTraceLL(reload_val);
617 v3_add_timer(dev->vm, &timer_ops, dev);
619 // Get cpu frequency and calculate the global pit oscilattor counter/cycle
621 do_divll(reload_val, OSC_HZ);
622 state->pit_counter = reload_val;
623 state->pit_reload = reload_val;
627 init_channel(&(state->ch_0));
628 init_channel(&(state->ch_1));
629 init_channel(&(state->ch_2));
632 PrintDebug("8254 PIT: CPU MHZ=%d -- pit count=", cpu_khz / 1000);
633 PrintTraceLL(state->pit_counter);
640 static int pit_deinit(struct vm_device * dev) {
646 static struct vm_device_ops dev_ops = {
648 .deinit = pit_deinit,
656 struct vm_device * v3_create_pit() {
657 struct pit * pit_state = NULL;
658 pit_state = (struct pit *)V3_Malloc(sizeof(struct pit));
659 V3_ASSERT(pit_state != NULL);
661 struct vm_device * dev = v3_create_device("PIT", &dev_ops, pit_state);