1 #include <devices/8254.h>
2 #include <palacios/vmm.h>
3 #include <palacios/vmm_time.h>
4 #include <palacios/vmm_util.h>
13 #define OSC_HZ 1193182
16 /* The 8254 has three counters and one control port */
17 #define CHANNEL0_PORT 0x40
18 #define CHANNEL1_PORT 0x41
19 #define CHANNEL2_PORT 0x42
20 #define COMMAND_PORT 0x43
23 #define PIT_INTR_NUM 0
25 /* The order of these typedefs is important because the numerical values correspond to the
26 * values coming from the io ports
28 typedef enum {NOT_RUNNING, PENDING, RUNNING} channel_run_state_t;
29 typedef enum {NOT_WAITING, WAITING_LOBYTE, WAITING_HIBYTE} channel_access_state_t;
30 typedef enum {LATCH_COUNT, LOBYTE_ONLY, HIBYTE_ONLY, LOBYTE_HIBYTE} channel_access_mode_t;
31 typedef enum {IRQ_ON_TERM_CNT, ONE_SHOT, RATE_GEN, SQR_WAVE, SW_STROBE, HW_STROBE} channel_op_mode_t;
35 channel_access_mode_t access_mode;
36 channel_access_state_t access_state;
37 channel_run_state_t run_state;
39 channel_op_mode_t op_mode;
42 // Time til interrupt trigger
45 ushort_t reload_value;
47 ushort_t latched_value;
49 enum {NOTLATCHED,LATCHED} latch_state;
51 enum {LSB,MSB} read_state;
53 uint_t output_pin : 1;
54 uint_t gate_input_pin : 1;
73 uint_t access_mode : 2;
77 struct pit_rdb_cmd_word {
78 uint_t rsvd : 1; // SBZ
82 uint_t latch_status : 1;
83 uint_t latch_count : 1;
84 uint_t readback_cmd : 2; // Must Be 0x3
87 struct pit_rdb_status_word {
90 uint_t access_mode : 2;
91 uint_t null_count : 1;
98 * This should call out to handle_SQR_WAVE_tics, etc...
100 // Returns true if the the output signal changed state
101 static int handle_crystal_tics(struct vm_device * dev, struct channel * ch, uint_t oscillations) {
102 uint_t channel_cycles = 0;
103 uint_t output_changed = 0;
105 // PrintDebug("8254 PIT: %d crystal tics\n", oscillations);
106 if (ch->run_state == PENDING) {
108 ch->counter = ch->reload_value;
110 if (ch->op_mode == SQR_WAVE) {
111 ch->counter -= ch->counter % 2;
114 ch->run_state = RUNNING;
115 } else if (ch->run_state != RUNNING) {
116 return output_changed;
120 PrintDebug("8254 PIT: Channel Run State = %d, counter=", ch->run_state);
121 PrintTraceLL(ch->counter);
124 if (ch->op_mode == SQR_WAVE) {
128 if (ch->counter > oscillations) {
129 ch->counter -= oscillations;
130 return output_changed;
132 ushort_t reload_val = ch->reload_value;
133 oscillations -= ch->counter;
138 if (ch->op_mode == SQR_WAVE) {
139 reload_val -= reload_val % 2;
142 channel_cycles += oscillations / reload_val;
143 oscillations = oscillations % reload_val;
145 ch->counter = reload_val - oscillations;
148 // PrintDebug("8254 PIT: Channel Cycles: %d\n", channel_cycles);
152 switch (ch->op_mode) {
153 case IRQ_ON_TERM_CNT:
154 if ((channel_cycles > 0) && (ch->output_pin == 0)) {
160 if ((channel_cycles > 0) && (ch->output_pin == 0)) {
166 // See the data sheet: we ignore the output pin cycle...
167 if (channel_cycles > 0) {
172 ch->output_pin = (ch->output_pin + 1) % 2;
174 if (ch->output_pin == 1) {
189 return output_changed;
194 static void pit_update_time(ullong_t cpu_cycles, ullong_t cpu_freq, void * private_data) {
195 struct vm_device * dev = (struct vm_device *)private_data;
196 struct pit * state = (struct pit *)dev->private_data;
197 // ullong_t tmp_ctr = state->pit_counter;
199 uint_t oscillations = 0;
203 PrintDebug("updating cpu_cycles=");
204 PrintTraceLL(cpu_cycles);
207 PrintDebug("pit_counter=");
208 PrintTraceLL(state->pit_counter);
211 PrintDebug("pit_reload=");
212 PrintTraceLL(state->pit_reload);
216 if (state->pit_counter > cpu_cycles) {
218 state->pit_counter -= cpu_cycles;
221 // Take off the first part
222 cpu_cycles -= state->pit_counter;
223 state->pit_counter = 0;
226 if (cpu_cycles > state->pit_reload) {
227 // how many full oscillations
228 tmp_cycles = cpu_cycles;
230 cpu_cycles = do_divll(tmp_cycles, state->pit_reload);
232 oscillations += tmp_cycles;
235 // update counter with remainder (mod reload)
236 state->pit_counter = state->pit_reload - cpu_cycles;
238 //PrintDebug("8254 PIT: Handling %d crystal tics\n", oscillations);
239 if (handle_crystal_tics(dev, &(state->ch_0), oscillations) == 1) {
241 PrintDebug("8254 PIT: Injecting Timer interrupt to guest\n");
242 dev->vm->vm_ops.raise_irq(dev->vm, 0);
245 //handle_crystal_tics(dev, &(state->ch_1), oscillations);
246 //handle_crystal_tics(dev, &(state->ch_2), oscillations);
257 /* This should call out to handle_SQR_WAVE_write, etc...
259 static int handle_channel_write(struct channel * ch, char val) {
261 switch (ch->access_state) {
264 ushort_t tmp_val = ((ushort_t)val) << 8;
265 ch->reload_value &= 0x00ff;
266 ch->reload_value |= tmp_val;
269 if ((ch->op_mode != RATE_GEN) || (ch->run_state != RUNNING)){
270 ch->run_state = PENDING;
273 if (ch->access_mode == LOBYTE_HIBYTE) {
274 ch->access_state = WAITING_LOBYTE;
277 PrintDebug("8254 PIT: updated channel counter: %d\n", ch->reload_value);
278 PrintDebug("8254 PIT: Channel Run State=%d\n", ch->run_state);
282 ch->reload_value &= 0xff00;
283 ch->reload_value |= val;
285 if (ch->access_mode == LOBYTE_HIBYTE) {
286 ch->access_state = WAITING_HIBYTE;
287 } else if ((ch->op_mode != RATE_GEN) || (ch->run_state != RUNNING)) {
288 ch->run_state = PENDING;
291 PrintDebug("8254 PIT: updated channel counter: %d\n", ch->reload_value);
292 PrintDebug("8254 PIT: Channel Run State=%d\n", ch->run_state);
299 switch (ch->op_mode) {
300 case IRQ_ON_TERM_CNT:
322 static int handle_channel_read(struct channel * ch, char * val) {
326 if (ch->latch_state==NOTLATCHED) {
327 myval = &(ch->counter);
329 myval = &(ch->latched_value);
332 if (ch->read_state==LSB) {
333 *val = ((char*)myval)[0]; // little endian
336 *val = ((char*)myval)[1];
338 if (ch->latch_state==LATCHED) {
339 ch->latch_state=NOTLATCHED;
351 static int handle_channel_cmd(struct channel * ch, struct pit_cmd_word cmd) {
352 ch->op_mode = cmd.op_mode;
353 ch->access_mode = cmd.access_mode;
358 switch (cmd.access_mode) {
360 if (ch->latch_state==NOTLATCHED) {
361 ch->latched_value=ch->counter;
362 ch->latch_state=LATCHED;
366 ch->access_state = WAITING_HIBYTE;
370 ch->access_state = WAITING_LOBYTE;
375 switch (cmd.op_mode) {
376 case IRQ_ON_TERM_CNT:
399 static int pit_read_channel(ushort_t port, void * dst, uint_t length, struct vm_device * dev) {
400 struct pit * state = (struct pit *)dev->private_data;
401 char * val = (char *)dst;
404 PrintDebug("8254 PIT: Invalid Read Write length \n");
408 PrintDebug("8254 PIT: Read of PIT Channel %d\n", port - CHANNEL0_PORT);
412 if (handle_channel_read(&(state->ch_0), val) == -1) {
417 if (handle_channel_read(&(state->ch_1), val) == -1) {
422 if (handle_channel_read(&(state->ch_2), val) == -1) {
427 PrintDebug("8254 PIT: Read from invalid port (%d)\n", port);
436 static int pit_write_channel(ushort_t port, void * src, uint_t length, struct vm_device * dev) {
437 struct pit * state = (struct pit *)dev->private_data;
438 char val = *(char *)src;
441 PrintDebug("8254 PIT: Invalid Write Length\n");
445 PrintDebug("8254 PIT: Write to PIT Channel %d (%x)\n", port - CHANNEL0_PORT, *(char*)src);
450 if (handle_channel_write(&(state->ch_0), val) == -1) {
455 if (handle_channel_write(&(state->ch_1), val) == -1) {
460 if (handle_channel_write(&(state->ch_2), val) == -1) {
465 PrintDebug("8254 PIT: Write to invalid port (%d)\n", port);
475 static int pit_write_command(ushort_t port, void * src, uint_t length, struct vm_device * dev) {
476 struct pit * state = (struct pit *)dev->private_data;
477 struct pit_cmd_word * cmd = (struct pit_cmd_word *)src;
479 PrintDebug("8254 PIT: Write to PIT Command port\n");
480 PrintDebug("8254 PIT: Writing to channel %d (access_mode = %d, op_mode = %d)\n", cmd->channel, cmd->access_mode, cmd->op_mode);
482 PrintDebug("8254 PIT: Write of Invalid length to command port\n");
486 switch (cmd->channel) {
488 if (handle_channel_cmd(&(state->ch_0), *cmd) == -1) {
493 if (handle_channel_cmd(&(state->ch_1), *cmd) == -1) {
498 if (handle_channel_cmd(&(state->ch_2), *cmd) == -1) {
517 static struct vm_timer_ops timer_ops = {
518 .update_time = pit_update_time,
522 static void init_channel(struct channel * ch) {
523 ch->run_state = NOT_RUNNING;
524 ch->access_state = NOT_WAITING;
529 ch->reload_value = 0;
531 ch->gate_input_pin = 0;
534 ch->latch_state=NOTLATCHED;
541 static int pit_init(struct vm_device * dev) {
542 struct pit * state = (struct pit *)dev->private_data;
543 uint_t cpu_khz = V3_CPU_KHZ();
544 ullong_t reload_val = (ullong_t)cpu_khz * 1000;
546 dev_hook_io(dev, CHANNEL0_PORT, &pit_read_channel, &pit_write_channel);
547 dev_hook_io(dev, CHANNEL1_PORT, &pit_read_channel, &pit_write_channel);
548 dev_hook_io(dev, CHANNEL2_PORT, &pit_read_channel, &pit_write_channel);
549 dev_hook_io(dev, COMMAND_PORT, NULL, &pit_write_command);
551 PrintDebug("8254 PIT: OSC_HZ=%d, reload_val=", OSC_HZ);
552 PrintTraceLL(reload_val);
556 v3_add_timer(dev->vm, &timer_ops, dev);
558 // Get cpu frequency and calculate the global pit oscilattor counter/cycle
560 do_divll(reload_val, OSC_HZ);
561 state->pit_counter = reload_val;
562 state->pit_reload = reload_val;
566 init_channel(&(state->ch_0));
567 init_channel(&(state->ch_1));
568 init_channel(&(state->ch_2));
570 PrintDebug("8254 PIT: CPU MHZ=%d -- pit count=", cpu_khz / 1000);
571 PrintTraceLL(state->pit_counter);
577 static int pit_deinit(struct vm_device * dev) {
583 static struct vm_device_ops dev_ops = {
585 .deinit = pit_deinit,
593 struct vm_device * create_pit() {
594 struct pit * pit_state = NULL;
595 pit_state = (struct pit *)V3_Malloc(sizeof(struct pit));
596 V3_ASSERT(pit_state != NULL);
598 struct vm_device * dev = create_device("PIT", &dev_ops, pit_state);