1 #include <devices/8254.h>
2 #include <palacios/vmm.h>
3 #include <palacios/vmm_time.h>
4 #include <palacios/vmm_util.h>
13 #define OSC_HZ 1193182
16 /* The 8254 has three counters and one control port */
17 #define CHANNEL0_PORT 0x40
18 #define CHANNEL1_PORT 0x41
19 #define CHANNEL2_PORT 0x42
20 #define COMMAND_PORT 0x43
23 #define PIT_INTR_NUM 0
25 /* The order of these typedefs is important because the numerical values correspond to the
26 * values coming from the io ports
28 typedef enum {NOT_RUNNING, PENDING, RUNNING} channel_run_state_t;
29 typedef enum {NOT_WAITING, WAITING_LOBYTE, WAITING_HIBYTE} channel_access_state_t;
30 typedef enum {LATCH_COUNT, LOBYTE_ONLY, HIBYTE_ONLY, LOBYTE_HIBYTE} channel_access_mode_t;
31 typedef enum {IRQ_ON_TERM_CNT, ONE_SHOT, RATE_GEN, SQR_WAVE, SW_STROBE, HW_STROBE} channel_op_mode_t;
35 channel_access_mode_t access_mode;
36 channel_access_state_t access_state;
37 channel_run_state_t run_state;
39 channel_op_mode_t op_mode;
42 // Time til interrupt trigger
45 ushort_t reload_value;
47 uint_t output_pin : 1;
48 uint_t gate_input_pin : 1;
67 uint_t access_mode : 2;
71 struct pit_rdb_cmd_word {
72 uint_t rsvd : 1; // SBZ
76 uint_t latch_status : 1;
77 uint_t latch_count : 1;
78 uint_t readback_cmd : 2; // Must Be 0x3
81 struct pit_rdb_status_word {
84 uint_t access_mode : 2;
85 uint_t null_count : 1;
92 * This should call out to handle_SQR_WAVE_tics, etc...
94 // Returns true if the the output signal changed state
95 static int handle_crystal_tics(struct vm_device * dev, struct channel * ch, uint_t oscillations) {
96 uint_t channel_cycles = 0;
97 uint_t output_changed = 0;
99 PrintDebug("8254 PIT: %d crystal tics\n", oscillations);
100 if (ch->run_state == PENDING) {
102 ch->counter = ch->reload_value;
103 ch->run_state = RUNNING;
104 } else if (ch->run_state != RUNNING) {
105 return output_changed;
109 PrintDebug("8254 PIT: Channel Run State = %d, counter=", ch->run_state);
110 PrintTraceLL(ch->counter);
114 if (ch->counter > oscillations) {
115 ch->counter -= oscillations;
116 return output_changed;
118 oscillations -= ch->counter;
123 channel_cycles += oscillations / ch->reload_value;
124 oscillations = oscillations % ch->reload_value;
126 ch->counter = ch->reload_value - oscillations;
129 PrintDebug("8254 PIT: Channel Cycles: %d\n", channel_cycles);
133 switch (ch->op_mode) {
134 case IRQ_ON_TERM_CNT:
135 if ((channel_cycles > 0) && (ch->output_pin == 0)) {
141 if ((channel_cycles > 0) && (ch->output_pin == 0)) {
147 // See the data sheet: we ignore the output pin cycle...
148 if (channel_cycles > 0) {
162 return output_changed;
167 static void pit_update_time(ullong_t cpu_cycles, ullong_t cpu_freq, void * private_data) {
168 struct vm_device * dev = (struct vm_device *)private_data;
169 struct pit * state = (struct pit *)dev->private_data;
170 // ullong_t tmp_ctr = state->pit_counter;
172 uint_t oscillations = 0;
176 PrintDebug("updating cpu_cycles=");
177 PrintTraceLL(cpu_cycles);
180 PrintDebug("pit_counter=");
181 PrintTraceLL(state->pit_counter);
184 PrintDebug("pit_reload=");
185 PrintTraceLL(state->pit_reload);
189 if (state->pit_counter > cpu_cycles) {
191 state->pit_counter -= cpu_cycles;
194 // Take off the first part
195 cpu_cycles -= state->pit_counter;
196 state->pit_counter = 0;
199 if (cpu_cycles > state->pit_reload) {
200 // how many full oscillations
201 tmp_cycles = cpu_cycles;
203 cpu_cycles = do_divll(tmp_cycles, state->pit_reload);
205 oscillations += tmp_cycles;
208 // update counter with remainder (mod reload)
209 state->pit_counter = state->pit_reload - cpu_cycles;
211 //PrintDebug("8254 PIT: Handling %d crystal tics\n", oscillations);
212 if (handle_crystal_tics(dev, &(state->ch_0), oscillations) == 1) {
214 PrintDebug("8254 PIT: Injecting Timer interrupt to guest\n");
215 dev->vm->vm_ops.raise_irq(dev->vm, 0);
218 //handle_crystal_tics(dev, &(state->ch_1), oscillations);
219 //handle_crystal_tics(dev, &(state->ch_2), oscillations);
230 /* This should call out to handle_SQR_WAVE_write, etc...
232 static int handle_channel_write(struct channel * ch, char val) {
234 switch (ch->access_state) {
237 ushort_t tmp_val = ((ushort_t)val) << 8;
238 ch->reload_value &= 0x00ff;
239 ch->reload_value |= tmp_val;
242 if ((ch->op_mode != RATE_GEN) || (ch->run_state != RUNNING)){
243 ch->run_state = PENDING;
246 if (ch->access_mode == LOBYTE_HIBYTE) {
247 ch->access_state = WAITING_LOBYTE;
250 PrintDebug("8254 PIT: updated channel counter: %d\n", ch->reload_value);
251 PrintDebug("8254 PIT: Channel Run State=%d\n", ch->run_state);
255 ch->reload_value &= 0xff00;
256 ch->reload_value |= val;
258 if (ch->access_mode == LOBYTE_HIBYTE) {
259 ch->access_state = WAITING_HIBYTE;
260 } else if ((ch->op_mode != RATE_GEN) || (ch->run_state != RUNNING)) {
261 ch->run_state = PENDING;
264 PrintDebug("8254 PIT: updated channel counter: %d\n", ch->reload_value);
265 PrintDebug("8254 PIT: Channel Run State=%d\n", ch->run_state);
272 switch (ch->op_mode) {
273 case IRQ_ON_TERM_CNT:
294 static int handle_channel_read(struct channel * ch, char * val) {
302 static int handle_channel_cmd(struct channel * ch, struct pit_cmd_word cmd) {
303 ch->op_mode = cmd.op_mode;
304 ch->access_mode = cmd.access_mode;
309 switch (cmd.access_mode) {
314 ch->access_state = WAITING_HIBYTE;
318 ch->access_state = WAITING_LOBYTE;
323 switch (cmd.op_mode) {
324 case IRQ_ON_TERM_CNT:
347 static int pit_read_channel(ushort_t port, void * dst, uint_t length, struct vm_device * dev) {
348 struct pit * state = (struct pit *)dev->private_data;
349 char * val = (char *)dst;
352 PrintDebug("8254 PIT: Invalid Read Write length \n");
356 PrintDebug("8254 PIT: Read of PIT Channel %d\n", port - CHANNEL0_PORT);
360 if (handle_channel_read(&(state->ch_0), val) == -1) {
365 if (handle_channel_read(&(state->ch_1), val) == -1) {
370 if (handle_channel_read(&(state->ch_2), val) == -1) {
375 PrintDebug("8254 PIT: Read from invalid port (%d)\n", port);
384 static int pit_write_channel(ushort_t port, void * src, uint_t length, struct vm_device * dev) {
385 struct pit * state = (struct pit *)dev->private_data;
386 char val = *(char *)src;
389 PrintDebug("8254 PIT: Invalid Write Length\n");
393 PrintDebug("8254 PIT: Write to PIT Channel %d (%x)\n", port - CHANNEL0_PORT, *(char*)src);
398 if (handle_channel_write(&(state->ch_0), val) == -1) {
403 if (handle_channel_write(&(state->ch_1), val) == -1) {
408 if (handle_channel_write(&(state->ch_2), val) == -1) {
413 PrintDebug("8254 PIT: Write to invalid port (%d)\n", port);
423 static int pit_write_command(ushort_t port, void * src, uint_t length, struct vm_device * dev) {
424 struct pit * state = (struct pit *)dev->private_data;
425 struct pit_cmd_word * cmd = (struct pit_cmd_word *)src;
427 PrintDebug("8254 PIT: Write to PIT Command port\n");
428 PrintDebug("8254 PIT: Writing to channel %d (access_mode = %d, op_mode = %d)\n", cmd->channel, cmd->access_mode, cmd->op_mode);
430 PrintDebug("8254 PIT: Write of Invalid length to command port\n");
434 switch (cmd->channel) {
436 if (handle_channel_cmd(&(state->ch_0), *cmd) == -1) {
441 if (handle_channel_cmd(&(state->ch_1), *cmd) == -1) {
446 if (handle_channel_cmd(&(state->ch_2), *cmd) == -1) {
465 static struct vm_timer_ops timer_ops = {
466 .update_time = pit_update_time,
470 static void init_channel(struct channel * ch) {
471 ch->run_state = NOT_RUNNING;
472 ch->access_state = NOT_WAITING;
477 ch->reload_value = 0;
479 ch->gate_input_pin = 0;
485 static int pit_init(struct vm_device * dev) {
486 struct pit * state = (struct pit *)dev->private_data;
487 uint_t cpu_khz = V3_CPU_KHZ();
488 ullong_t reload_val = (ullong_t)cpu_khz * 1000;
490 dev_hook_io(dev, CHANNEL0_PORT, &pit_read_channel, &pit_write_channel);
491 dev_hook_io(dev, CHANNEL1_PORT, &pit_read_channel, &pit_write_channel);
492 dev_hook_io(dev, CHANNEL2_PORT, &pit_read_channel, &pit_write_channel);
493 dev_hook_io(dev, COMMAND_PORT, NULL, &pit_write_command);
495 PrintDebug("8254 PIT: OSC_HZ=%d, reload_val=", OSC_HZ);
496 PrintTraceLL(reload_val);
500 v3_add_timer(dev->vm, &timer_ops, dev);
502 // Get cpu frequency and calculate the global pit oscilattor counter/cycle
504 do_divll(reload_val, OSC_HZ);
505 state->pit_counter = reload_val;
506 state->pit_reload = reload_val;
510 init_channel(&(state->ch_0));
511 init_channel(&(state->ch_1));
512 init_channel(&(state->ch_2));
514 PrintDebug("8254 PIT: CPU MHZ=%d -- pit count=", cpu_khz / 1000);
515 PrintTraceLL(state->pit_counter);
521 static int pit_deinit(struct vm_device * dev) {
527 static struct vm_device_ops dev_ops = {
529 .deinit = pit_deinit,
537 struct vm_device * create_pit() {
538 struct pit * pit_state = NULL;
539 pit_state = (struct pit *)V3_Malloc(sizeof(struct pit));
540 V3_ASSERT(pit_state != NULL);
542 struct vm_device * dev = create_device("PIT", &dev_ops, pit_state);