1 #include <devices/8254.h>
2 #include <palacios/vmm.h>
3 #include <palacios/vmm_time.h>
4 #include <palacios/vmm_util.h>
13 #define OSC_HZ 1193182
16 /* The 8254 has three counters and one control port */
17 #define CHANNEL0_PORT 0x40
18 #define CHANNEL1_PORT 0x41
19 #define CHANNEL2_PORT 0x42
20 #define COMMAND_PORT 0x43
23 #define PIT_INTR_NUM 0
25 /* The order of these typedefs is important because the numerical values correspond to the
26 * values coming from the io ports
28 typedef enum {NOT_RUNNING, PENDING, RUNNING} channel_run_state_t;
29 typedef enum {NOT_WAITING, WAITING_LOBYTE, WAITING_HIBYTE} channel_access_state_t;
30 typedef enum {LATCH_COUNT, LOBYTE_ONLY, HIBYTE_ONLY, LOBYTE_HIBYTE} channel_access_mode_t;
31 typedef enum {IRQ_ON_TERM_CNT, ONE_SHOT, RATE_GEN, SQR_WAVE, SW_STROBE, HW_STROBE} channel_op_mode_t;
35 channel_access_mode_t access_mode;
36 channel_access_state_t access_state;
37 channel_run_state_t run_state;
39 channel_op_mode_t op_mode;
42 // Time til interrupt trigger
45 ushort_t reload_value;
47 uint_t output_pin : 1;
48 uint_t gate_input_pin : 1;
67 uint_t access_mode : 2;
71 struct pit_rdb_cmd_word {
72 uint_t rsvd : 1; // SBZ
76 uint_t latch_status : 1;
77 uint_t latch_count : 1;
78 uint_t readback_cmd : 2; // Must Be 0x3
81 struct pit_rdb_status_word {
84 uint_t access_mode : 2;
85 uint_t null_count : 1;
92 * This should call out to handle_SQR_WAVE_tics, etc...
94 // Returns true if the the output signal changed state
95 static int handle_crystal_tics(struct vm_device * dev, struct channel * ch, uint_t oscillations) {
96 uint_t channel_cycles = 0;
97 uint_t output_changed = 0;
99 // PrintDebug("8254 PIT: %d crystal tics\n", oscillations);
100 if (ch->run_state == PENDING) {
102 ch->counter = ch->reload_value;
104 if (ch->op_mode == SQR_WAVE) {
105 ch->counter -= ch->counter % 2;
108 ch->run_state = RUNNING;
109 } else if (ch->run_state != RUNNING) {
110 return output_changed;
114 PrintDebug("8254 PIT: Channel Run State = %d, counter=", ch->run_state);
115 PrintTraceLL(ch->counter);
118 if (ch->op_mode == SQR_WAVE) {
122 if (ch->counter > oscillations) {
123 ch->counter -= oscillations;
124 return output_changed;
126 ushort_t reload_val = ch->reload_value;
127 oscillations -= ch->counter;
132 if (ch->op_mode == SQR_WAVE) {
133 reload_val -= reload_val % 2;
136 channel_cycles += oscillations / reload_val;
137 oscillations = oscillations % reload_val;
139 ch->counter = reload_val - oscillations;
142 // PrintDebug("8254 PIT: Channel Cycles: %d\n", channel_cycles);
146 switch (ch->op_mode) {
147 case IRQ_ON_TERM_CNT:
148 if ((channel_cycles > 0) && (ch->output_pin == 0)) {
154 if ((channel_cycles > 0) && (ch->output_pin == 0)) {
160 // See the data sheet: we ignore the output pin cycle...
161 if (channel_cycles > 0) {
166 ch->output_pin = (ch->output_pin + 1) % 2;
168 if (ch->output_pin == 1) {
183 return output_changed;
188 static void pit_update_time(ullong_t cpu_cycles, ullong_t cpu_freq, void * private_data) {
189 struct vm_device * dev = (struct vm_device *)private_data;
190 struct pit * state = (struct pit *)dev->private_data;
191 // ullong_t tmp_ctr = state->pit_counter;
193 uint_t oscillations = 0;
197 PrintDebug("updating cpu_cycles=");
198 PrintTraceLL(cpu_cycles);
201 PrintDebug("pit_counter=");
202 PrintTraceLL(state->pit_counter);
205 PrintDebug("pit_reload=");
206 PrintTraceLL(state->pit_reload);
210 if (state->pit_counter > cpu_cycles) {
212 state->pit_counter -= cpu_cycles;
215 // Take off the first part
216 cpu_cycles -= state->pit_counter;
217 state->pit_counter = 0;
220 if (cpu_cycles > state->pit_reload) {
221 // how many full oscillations
222 tmp_cycles = cpu_cycles;
224 cpu_cycles = do_divll(tmp_cycles, state->pit_reload);
226 oscillations += tmp_cycles;
229 // update counter with remainder (mod reload)
230 state->pit_counter = state->pit_reload - cpu_cycles;
232 //PrintDebug("8254 PIT: Handling %d crystal tics\n", oscillations);
233 if (handle_crystal_tics(dev, &(state->ch_0), oscillations) == 1) {
235 PrintDebug("8254 PIT: Injecting Timer interrupt to guest\n");
236 dev->vm->vm_ops.raise_irq(dev->vm, 0);
239 //handle_crystal_tics(dev, &(state->ch_1), oscillations);
240 //handle_crystal_tics(dev, &(state->ch_2), oscillations);
251 /* This should call out to handle_SQR_WAVE_write, etc...
253 static int handle_channel_write(struct channel * ch, char val) {
255 switch (ch->access_state) {
258 ushort_t tmp_val = ((ushort_t)val) << 8;
259 ch->reload_value &= 0x00ff;
260 ch->reload_value |= tmp_val;
263 if ((ch->op_mode != RATE_GEN) || (ch->run_state != RUNNING)){
264 ch->run_state = PENDING;
267 if (ch->access_mode == LOBYTE_HIBYTE) {
268 ch->access_state = WAITING_LOBYTE;
271 PrintDebug("8254 PIT: updated channel counter: %d\n", ch->reload_value);
272 PrintDebug("8254 PIT: Channel Run State=%d\n", ch->run_state);
276 ch->reload_value &= 0xff00;
277 ch->reload_value |= val;
279 if (ch->access_mode == LOBYTE_HIBYTE) {
280 ch->access_state = WAITING_HIBYTE;
281 } else if ((ch->op_mode != RATE_GEN) || (ch->run_state != RUNNING)) {
282 ch->run_state = PENDING;
285 PrintDebug("8254 PIT: updated channel counter: %d\n", ch->reload_value);
286 PrintDebug("8254 PIT: Channel Run State=%d\n", ch->run_state);
293 switch (ch->op_mode) {
294 case IRQ_ON_TERM_CNT:
316 static int handle_channel_read(struct channel * ch, char * val) {
324 static int handle_channel_cmd(struct channel * ch, struct pit_cmd_word cmd) {
325 ch->op_mode = cmd.op_mode;
326 ch->access_mode = cmd.access_mode;
331 switch (cmd.access_mode) {
336 ch->access_state = WAITING_HIBYTE;
340 ch->access_state = WAITING_LOBYTE;
345 switch (cmd.op_mode) {
346 case IRQ_ON_TERM_CNT:
369 static int pit_read_channel(ushort_t port, void * dst, uint_t length, struct vm_device * dev) {
370 struct pit * state = (struct pit *)dev->private_data;
371 char * val = (char *)dst;
374 PrintDebug("8254 PIT: Invalid Read Write length \n");
378 PrintDebug("8254 PIT: Read of PIT Channel %d\n", port - CHANNEL0_PORT);
382 if (handle_channel_read(&(state->ch_0), val) == -1) {
387 if (handle_channel_read(&(state->ch_1), val) == -1) {
392 if (handle_channel_read(&(state->ch_2), val) == -1) {
397 PrintDebug("8254 PIT: Read from invalid port (%d)\n", port);
406 static int pit_write_channel(ushort_t port, void * src, uint_t length, struct vm_device * dev) {
407 struct pit * state = (struct pit *)dev->private_data;
408 char val = *(char *)src;
411 PrintDebug("8254 PIT: Invalid Write Length\n");
415 PrintDebug("8254 PIT: Write to PIT Channel %d (%x)\n", port - CHANNEL0_PORT, *(char*)src);
420 if (handle_channel_write(&(state->ch_0), val) == -1) {
425 if (handle_channel_write(&(state->ch_1), val) == -1) {
430 if (handle_channel_write(&(state->ch_2), val) == -1) {
435 PrintDebug("8254 PIT: Write to invalid port (%d)\n", port);
445 static int pit_write_command(ushort_t port, void * src, uint_t length, struct vm_device * dev) {
446 struct pit * state = (struct pit *)dev->private_data;
447 struct pit_cmd_word * cmd = (struct pit_cmd_word *)src;
449 PrintDebug("8254 PIT: Write to PIT Command port\n");
450 PrintDebug("8254 PIT: Writing to channel %d (access_mode = %d, op_mode = %d)\n", cmd->channel, cmd->access_mode, cmd->op_mode);
452 PrintDebug("8254 PIT: Write of Invalid length to command port\n");
456 switch (cmd->channel) {
458 if (handle_channel_cmd(&(state->ch_0), *cmd) == -1) {
463 if (handle_channel_cmd(&(state->ch_1), *cmd) == -1) {
468 if (handle_channel_cmd(&(state->ch_2), *cmd) == -1) {
487 static struct vm_timer_ops timer_ops = {
488 .update_time = pit_update_time,
492 static void init_channel(struct channel * ch) {
493 ch->run_state = NOT_RUNNING;
494 ch->access_state = NOT_WAITING;
499 ch->reload_value = 0;
501 ch->gate_input_pin = 0;
507 static int pit_init(struct vm_device * dev) {
508 struct pit * state = (struct pit *)dev->private_data;
509 uint_t cpu_khz = V3_CPU_KHZ();
510 ullong_t reload_val = (ullong_t)cpu_khz * 1000;
512 dev_hook_io(dev, CHANNEL0_PORT, &pit_read_channel, &pit_write_channel);
513 dev_hook_io(dev, CHANNEL1_PORT, &pit_read_channel, &pit_write_channel);
514 dev_hook_io(dev, CHANNEL2_PORT, &pit_read_channel, &pit_write_channel);
515 dev_hook_io(dev, COMMAND_PORT, NULL, &pit_write_command);
517 PrintDebug("8254 PIT: OSC_HZ=%d, reload_val=", OSC_HZ);
518 PrintTraceLL(reload_val);
522 v3_add_timer(dev->vm, &timer_ops, dev);
524 // Get cpu frequency and calculate the global pit oscilattor counter/cycle
526 do_divll(reload_val, OSC_HZ);
527 state->pit_counter = reload_val;
528 state->pit_reload = reload_val;
532 init_channel(&(state->ch_0));
533 init_channel(&(state->ch_1));
534 init_channel(&(state->ch_2));
536 PrintDebug("8254 PIT: CPU MHZ=%d -- pit count=", cpu_khz / 1000);
537 PrintTraceLL(state->pit_counter);
543 static int pit_deinit(struct vm_device * dev) {
549 static struct vm_device_ops dev_ops = {
551 .deinit = pit_deinit,
559 struct vm_device * create_pit() {
560 struct pit * pit_state = NULL;
561 pit_state = (struct pit *)V3_Malloc(sizeof(struct pit));
562 V3_ASSERT(pit_state != NULL);
564 struct vm_device * dev = create_device("PIT", &dev_ops, pit_state);