2 * This file is part of the Palacios Virtual Machine Monitor developed
3 * by the V3VEE Project with funding from the United States National
4 * Science Foundation and the Department of Energy.
6 * The V3VEE Project is a joint project between Northwestern University
7 * and the University of New Mexico. You can find out more at
10 * Copyright (c) 2008, Jack Lange <jarusl@cs.northwestern.edu>
11 * Copyright (c) 2008, The V3VEE Project <http://www.v3vee.org>
12 * All rights reserved.
14 * Author: Jack Lange <jarusl@cs.northwestern.edu>
16 * This is free software. You are permitted to use,
17 * redistribute, and modify it as specified in the file "V3VEE_LICENSE".
21 #include <palacios/vmm.h>
22 #include <palacios/vmm_dev_mgr.h>
23 #include <palacios/vmm_time.h>
24 #include <palacios/vmm_util.h>
25 #include <palacios/vmm_intr.h>
26 #include <palacios/vmm_config.h>
29 #ifndef CONFIG_DEBUG_PIT
31 #define PrintDebug(fmt, args...)
37 #define OSC_HZ 1193182
40 /* The 8254 has three counters and one control port */
41 #define CHANNEL0_PORT 0x40
42 #define CHANNEL1_PORT 0x41
43 #define CHANNEL2_PORT 0x42
44 #define COMMAND_PORT 0x43
45 #define SPEAKER_PORT 0x61
48 #define PIT_INTR_NUM 0
49 #define PIT_SPEAKER_GATE 0x01
51 /* The order of these typedefs is important because the numerical values correspond to the
52 * values coming from the io ports
54 typedef enum {NOT_RUNNING, PENDING, RUNNING} channel_run_state_t;
55 typedef enum {NOT_WAITING, WAITING_LOBYTE, WAITING_HIBYTE} channel_access_state_t;
56 typedef enum {LATCH_COUNT, LOBYTE_ONLY, HIBYTE_ONLY, LOBYTE_HIBYTE} channel_access_mode_t;
57 typedef enum {IRQ_ON_TERM_CNT, ONE_SHOT, RATE_GEN, SQR_WAVE, SW_STROBE, HW_STROBE} channel_op_mode_t;
61 channel_access_mode_t access_mode;
62 channel_access_state_t access_state;
63 channel_run_state_t run_state;
65 channel_op_mode_t op_mode;
68 // Time til interrupt trigger
71 ushort_t reload_value;
73 ushort_t latched_value;
75 enum {NOTLATCHED, LATCHED} latch_state;
77 enum {LSB, MSB} read_state;
79 uint_t output_pin : 1;
80 uint_t gate_input_pin : 1;
100 uint_t access_mode : 2;
104 struct pit_rdb_cmd_word {
105 uint_t rsvd : 1; // SBZ
109 uint_t latch_status : 1;
110 uint_t latch_count : 1;
111 uint_t readback_cmd : 2; // Must Be 0x3
114 struct pit_rdb_status_word {
117 uint_t access_mode : 2;
118 uint_t null_count : 1;
119 uint_t pin_state : 1;
125 * This should call out to handle_SQR_WAVE_tics, etc...
127 // Returns true if the the output signal changed state
128 static int handle_crystal_tics(struct vm_device * dev, struct channel * ch, uint_t oscillations) {
129 uint_t channel_cycles = 0;
130 uint_t output_changed = 0;
132 // PrintDebug("8254 PIT: %d crystal tics\n", oscillations);
133 if (ch->run_state == PENDING) {
135 ch->counter = ch->reload_value;
137 if (ch->op_mode == SQR_WAVE) {
138 ch->counter -= ch->counter % 2;
141 ch->run_state = RUNNING;
142 } else if (ch->run_state != RUNNING) {
143 return output_changed;
147 PrintDebug("8254 PIT: Channel Run State = %d, counter=", ch->run_state);
148 PrintTraceLL(ch->counter);
151 if (ch->op_mode == SQR_WAVE) {
155 if (ch->counter > oscillations) {
156 ch->counter -= oscillations;
157 return output_changed;
159 ushort_t reload_val = ch->reload_value;
161 if (ch->op_mode == SW_STROBE) {
165 // TODO: Check this....
166 // Is this correct???
167 if (reload_val == 0) {
171 oscillations -= ch->counter;
175 if (ch->op_mode == SQR_WAVE) {
176 reload_val -= reload_val % 2;
179 channel_cycles += oscillations / reload_val;
180 oscillations = oscillations % reload_val;
182 ch->counter = reload_val - oscillations;
185 // PrintDebug("8254 PIT: Channel Cycles: %d\n", channel_cycles);
189 switch (ch->op_mode) {
190 case IRQ_ON_TERM_CNT:
191 if ((channel_cycles > 0) && (ch->output_pin == 0)) {
197 if ((channel_cycles > 0) && (ch->output_pin == 0)) {
203 // See the data sheet: we ignore the output pin cycle...
204 if (channel_cycles > 0) {
209 ch->output_pin = (ch->output_pin + 1) % 2;
211 if (ch->output_pin == 1) {
218 if (channel_cycles > 0) {
219 if (ch->output_pin == 1) {
226 PrintError("Hardware strobe not implemented\n");
233 return output_changed;
237 #include <palacios/vm_guest.h>
239 static void pit_update_time(struct guest_info * info, ullong_t cpu_cycles, ullong_t cpu_freq, void * private_data) {
240 struct vm_device * dev = (struct vm_device *)private_data;
241 struct pit * state = (struct pit *)dev->private_data;
242 // ullong_t tmp_ctr = state->pit_counter;
244 uint_t oscillations = 0;
248 PrintDebug("updating cpu_cycles=");
249 PrintTraceLL(cpu_cycles);
252 PrintDebug("pit_counter=");
253 PrintTraceLL(state->pit_counter);
256 PrintDebug("pit_reload=");
257 PrintTraceLL(state->pit_reload);
261 if (state->pit_counter > cpu_cycles) {
263 state->pit_counter -= cpu_cycles;
265 ushort_t reload_val = state->pit_reload;
266 // Take off the first part
267 cpu_cycles -= state->pit_counter;
268 state->pit_counter = 0;
271 if (cpu_cycles > state->pit_reload) {
272 // how many full oscillations
274 //PrintError("cpu_cycles = %p, reload = %p...\n",
275 // (void *)(addr_t)cpu_cycles,
276 // (void *)(addr_t)state->pit_reload);
278 // How do we check for a one shot....
279 if (state->pit_reload == 0) {
283 tmp_cycles = cpu_cycles;
287 cpu_cycles = tmp_cycles % state->pit_reload;
288 tmp_cycles = tmp_cycles / state->pit_reload;
290 cpu_cycles = do_divll(tmp_cycles, state->pit_reload);
293 oscillations += tmp_cycles;
296 // update counter with remainder (mod reload)
297 state->pit_counter = state->pit_reload - cpu_cycles;
299 //PrintDebug("8254 PIT: Handling %d crystal tics\n", oscillations);
300 if (handle_crystal_tics(dev, &(state->ch_0), oscillations) == 1) {
302 PrintDebug("8254 PIT: Injecting Timer interrupt to guest\n");
303 v3_raise_irq(info->vm_info, 0);
306 //handle_crystal_tics(dev, &(state->ch_1), oscillations);
307 handle_crystal_tics(dev, &(state->ch_2), oscillations);
317 static void pit_advance_time(struct guest_info * core, void * private_data) {
319 v3_raise_irq(core->vm_info, 0);
324 /* This should call out to handle_SQR_WAVE_write, etc...
326 static int handle_channel_write(struct channel * ch, char val) {
328 switch (ch->access_state) {
331 ushort_t tmp_val = ((ushort_t)val) << 8;
332 ch->reload_value &= 0x00ff;
333 ch->reload_value |= tmp_val;
336 if ((ch->op_mode != RATE_GEN) || (ch->run_state != RUNNING)){
337 ch->run_state = PENDING;
340 if (ch->access_mode == LOBYTE_HIBYTE) {
341 ch->access_state = WAITING_LOBYTE;
344 PrintDebug("8254 PIT: updated channel counter: %d\n", ch->reload_value);
345 PrintDebug("8254 PIT: Channel Run State=%d\n", ch->run_state);
349 ch->reload_value &= 0xff00;
350 ch->reload_value |= val;
352 if (ch->access_mode == LOBYTE_HIBYTE) {
353 ch->access_state = WAITING_HIBYTE;
354 } else if ((ch->op_mode != RATE_GEN) || (ch->run_state != RUNNING)) {
355 ch->run_state = PENDING;
358 PrintDebug("8254 PIT: updated channel counter: %d\n", ch->reload_value);
359 PrintDebug("8254 PIT: Channel Run State=%d\n", ch->run_state);
362 PrintError("Invalid Access state\n");
367 switch (ch->op_mode) {
368 case IRQ_ON_TERM_CNT:
384 PrintError("Invalid OP_MODE: %d\n", ch->op_mode);
394 static int handle_channel_read(struct channel * ch, char * val) {
398 if (ch->latch_state == NOTLATCHED) {
399 myval = &(ch->counter);
401 myval = &(ch->latched_value);
404 if (ch->read_state == LSB) {
405 *val = ((char*)myval)[0]; // little endian
406 ch->read_state = MSB;
408 *val = ((char*)myval)[1];
409 ch->read_state = LSB;
410 if (ch->latch_state == LATCHED) {
411 ch->latch_state = NOTLATCHED;
419 static int handle_speaker_read(uint8_t *speaker, struct channel * ch, char * val) {
422 if ((*speaker & PIT_SPEAKER_GATE)) {
423 *val |= (ch->output_pin << 5);
429 static int handle_speaker_write(uint8_t *speaker, struct channel * ch, char val) {
430 *speaker = (val & ~0x20);
434 static int handle_channel_cmd(struct channel * ch, struct pit_cmd_word cmd) {
435 ch->op_mode = cmd.op_mode;
436 ch->access_mode = cmd.access_mode;
441 switch (cmd.access_mode) {
443 if (ch->latch_state == NOTLATCHED) {
444 ch->latched_value = ch->counter;
445 ch->latch_state = LATCHED;
449 ch->access_state = WAITING_HIBYTE;
453 ch->access_state = WAITING_LOBYTE;
458 switch (cmd.op_mode) {
459 case IRQ_ON_TERM_CNT:
475 PrintError("Invalid OP_MODE: %d\n", cmd.op_mode);
486 static int pit_read_channel(struct guest_info * core, ushort_t port, void * dst, uint_t length, struct vm_device * dev) {
487 struct pit * state = (struct pit *)dev->private_data;
488 char * val = (char *)dst;
491 PrintError("8254 PIT: Invalid Read Write length \n");
495 PrintDebug("8254 PIT: Read of PIT Channel %d\n", port - CHANNEL0_PORT);
499 if (handle_channel_read(&(state->ch_0), val) == -1) {
500 PrintError("CHANNEL0 read error\n");
505 if (handle_channel_read(&(state->ch_1), val) == -1) {
506 PrintError("CHANNEL1 read error\n");
511 if (handle_channel_read(&(state->ch_2), val) == -1) {
512 PrintError("CHANNEL2 read error\n");
517 if (handle_speaker_read(&state->speaker, &(state->ch_2), val) == -1) {
518 PrintError("SPEAKER read error\n");
523 PrintError("8254 PIT: Read from invalid port (%d)\n", port);
532 static int pit_write_channel(struct guest_info * core, ushort_t port, void * src, uint_t length, struct vm_device * dev) {
533 struct pit * state = (struct pit *)dev->private_data;
534 char val = *(char *)src;
537 PrintError("8254 PIT: Invalid Write Length\n");
541 PrintDebug("8254 PIT: Write to PIT Channel %d (%x)\n", port - CHANNEL0_PORT, *(char*)src);
546 if (handle_channel_write(&(state->ch_0), val) == -1) {
547 PrintError("CHANNEL0 write error\n");
552 if (handle_channel_write(&(state->ch_1), val) == -1) {
553 PrintError("CHANNEL1 write error\n");
558 if (handle_channel_write(&(state->ch_2), val) == -1) {
559 PrintError("CHANNEL2 write error\n");
564 if (handle_speaker_write(&state->speaker, &(state->ch_2), val) == -1) {
565 PrintError("SPEAKER write error\n");
570 PrintError("8254 PIT: Write to invalid port (%d)\n", port);
580 static int pit_write_command(struct guest_info * core, ushort_t port, void * src, uint_t length, struct vm_device * dev) {
581 struct pit * state = (struct pit *)dev->private_data;
582 struct pit_cmd_word * cmd = (struct pit_cmd_word *)src;
584 PrintDebug("8254 PIT: Write to PIT Command port\n");
585 PrintDebug("8254 PIT: Writing to channel %d (access_mode = %d, op_mode = %d)\n", cmd->channel, cmd->access_mode, cmd->op_mode);
587 PrintError("8254 PIT: Write of Invalid length to command port\n");
591 switch (cmd->channel) {
593 if (handle_channel_cmd(&(state->ch_0), *cmd) == -1) {
594 PrintError("CHANNEL0 command error\n");
599 if (handle_channel_cmd(&(state->ch_1), *cmd) == -1) {
600 PrintError("CHANNEL1 command error\n");
605 if (handle_channel_cmd(&(state->ch_2), *cmd) == -1) {
606 PrintError("CHANNEL2 command error\n");
612 PrintError("Read back command not implemented\n");
626 static struct vm_timer_ops timer_ops = {
627 .update_time = pit_update_time,
628 .advance_timer = pit_advance_time,
632 static void init_channel(struct channel * ch) {
633 ch->run_state = NOT_RUNNING;
634 ch->access_state = NOT_WAITING;
639 ch->reload_value = 0;
641 ch->gate_input_pin = 0;
643 ch->latched_value = 0;
644 ch->latch_state = NOTLATCHED;
645 ch->read_state = LSB;
653 static int pit_free(struct vm_device * dev) {
659 static struct v3_device_ops dev_ops = {
667 #include <palacios/vm_guest.h>
669 static int pit_init(struct v3_vm_info * vm, v3_cfg_tree_t * cfg) {
670 struct pit * pit_state = NULL;
671 struct vm_device * dev = NULL;
672 char * dev_id = v3_cfg_val(cfg, "ID");
674 // PIT is only usable in non-multicore environments
675 // just hardcode the core context
676 struct guest_info * info = &(vm->cores[0]);
678 uint_t cpu_khz = V3_CPU_KHZ();
679 ullong_t reload_val = (ullong_t)cpu_khz * 1000;
681 pit_state = (struct pit *)V3_Malloc(sizeof(struct pit));
682 V3_ASSERT(pit_state != NULL);
683 pit_state->speaker = 0;
685 dev = v3_allocate_device(dev_id, &dev_ops, pit_state);
687 if (v3_attach_device(vm, dev) == -1) {
688 PrintError("Could not attach device %s\n", dev_id);
692 v3_dev_hook_io(dev, CHANNEL0_PORT, &pit_read_channel, &pit_write_channel);
693 v3_dev_hook_io(dev, CHANNEL1_PORT, &pit_read_channel, &pit_write_channel);
694 v3_dev_hook_io(dev, CHANNEL2_PORT, &pit_read_channel, &pit_write_channel);
695 v3_dev_hook_io(dev, COMMAND_PORT, NULL, &pit_write_command);
696 v3_dev_hook_io(dev, SPEAKER_PORT, &pit_read_channel, &pit_write_channel);
698 #ifdef CONFIG_DEBUG_PIT
699 PrintDebug("8254 PIT: OSC_HZ=%d, reload_val=", OSC_HZ);
700 //PrintTrace(reload_val);
705 v3_add_timer(info, &timer_ops, dev);
707 // Get cpu frequency and calculate the global pit oscilattor counter/cycle
709 do_divll(reload_val, OSC_HZ);
710 pit_state->pit_counter = reload_val;
711 pit_state->pit_reload = reload_val;
715 init_channel(&(pit_state->ch_0));
716 init_channel(&(pit_state->ch_1));
717 init_channel(&(pit_state->ch_2));
719 #ifdef CONFIG_DEBUG_PIT
720 PrintDebug("8254 PIT: CPU MHZ=%d -- pit count=", cpu_khz / 1000);
721 //PrintTraceLL(pit_state->pit_counter);
729 device_register("8254_PIT", pit_init);