2 * This file is part of the Palacios Virtual Machine Monitor developed
3 * by the V3VEE Project with funding from the United States National
4 * Science Foundation and the Department of Energy.
6 * The V3VEE Project is a joint project between Northwestern University
7 * and the University of New Mexico. You can find out more at
10 * Copyright (c) 2008, Jack Lange <jarusl@cs.northwestern.edu>
11 * Copyright (c) 2008, The V3VEE Project <http://www.v3vee.org>
12 * All rights reserved.
14 * Author: Jack Lange <jarusl@cs.northwestern.edu>
16 * This is free software. You are permitted to use,
17 * redistribute, and modify it as specified in the file "V3VEE_LICENSE".
21 #include <palacios/vmm.h>
22 #include <palacios/vmm_dev_mgr.h>
23 #include <palacios/vmm_time.h>
24 #include <palacios/vmm_util.h>
25 #include <palacios/vmm_intr.h>
26 #include <palacios/vmm_config.h>
27 #include <palacios/vmm_io.h>
30 #ifndef V3_CONFIG_DEBUG_PIT
32 #define PrintDebug(fmt, args...)
38 #define OSC_HZ 1193182
41 /* The 8254 has three counters and one control port */
42 #define CHANNEL0_PORT 0x40
43 #define CHANNEL1_PORT 0x41
44 #define CHANNEL2_PORT 0x42
45 #define COMMAND_PORT 0x43
46 #define SPEAKER_PORT 0x61
49 #define PIT_INTR_NUM 0
50 #define PIT_SPEAKER_GATE 0x01
52 /* The order of these typedefs is important because the numerical values correspond to the
53 * values coming from the io ports
55 typedef enum {NOT_RUNNING, PENDING, RUNNING} channel_run_state_t;
56 typedef enum {NOT_WAITING, WAITING_LOBYTE, WAITING_HIBYTE} channel_access_state_t;
57 typedef enum {LATCH_COUNT = 0, LOBYTE_ONLY = 1, HIBYTE_ONLY = 2, LOBYTE_HIBYTE = 3} channel_access_mode_t;
58 typedef enum {IRQ_ON_TERM_CNT = 0, ONE_SHOT = 1, RATE_GEN = 2, SQR_WAVE = 3, SW_STROBE = 4, HW_STROBE = 5} channel_op_mode_t;
62 channel_access_mode_t access_mode;
63 channel_access_state_t access_state;
64 channel_run_state_t run_state;
66 channel_op_mode_t op_mode;
69 // Time til interrupt trigger
72 ushort_t reload_value;
74 ushort_t latched_value;
76 enum {NOTLATCHED, LATCHED} latch_state;
78 enum {LSB, MSB} read_state;
80 uint_t output_pin : 1;
81 uint_t gate_input_pin : 1;
90 struct v3_timer * timer;
92 struct v3_vm_info * vm;
101 struct pit_cmd_word {
104 uint_t access_mode : 2;
108 struct pit_rdb_cmd_word {
109 uint_t rsvd : 1; // SBZ
113 uint_t latch_status : 1;
114 uint_t latch_count : 1;
115 uint_t readback_cmd : 2; // Must Be 0x3
118 struct pit_rdb_status_word {
121 uint_t access_mode : 2;
122 uint_t null_count : 1;
123 uint_t pin_state : 1;
129 * This should call out to handle_SQR_WAVE_tics, etc...
131 // Returns true if the the output signal changed state
132 static int handle_crystal_tics(struct pit * pit, struct channel * ch, uint_t oscillations) {
133 uint_t channel_cycles = 0;
134 uint_t output_changed = 0;
136 // PrintDebug("8254 PIT: %d crystal tics\n", oscillations);
137 if (ch->run_state == PENDING) {
139 ch->counter = ch->reload_value;
141 if (ch->op_mode == SQR_WAVE) {
142 ch->counter -= ch->counter % 2;
145 ch->run_state = RUNNING;
146 } else if (ch->run_state != RUNNING) {
147 return output_changed;
151 PrintDebug("8254 PIT: Channel Run State = %d, counter=", ch->run_state);
152 PrintTraceLL(ch->counter);
155 if (ch->op_mode == SQR_WAVE) {
159 if (ch->counter > oscillations) {
160 ch->counter -= oscillations;
161 return output_changed;
163 ushort_t reload_val = ch->reload_value;
165 if ((ch->op_mode == SW_STROBE) || (ch->op_mode == IRQ_ON_TERM_CNT)) {
169 oscillations -= ch->counter;
173 if (ch->op_mode == SQR_WAVE) {
174 reload_val -= reload_val % 2;
177 // TODO: Check this....
178 // Is this correct???
179 if (reload_val == 0) {
183 channel_cycles += oscillations / reload_val;
184 oscillations = oscillations % reload_val;
186 ch->counter = reload_val - oscillations;
189 // PrintDebug("8254 PIT: Channel Cycles: %d\n", channel_cycles);
193 switch (ch->op_mode) {
194 case IRQ_ON_TERM_CNT:
195 if ((channel_cycles > 0) && (ch->output_pin == 0)) {
201 if ((channel_cycles > 0) && (ch->output_pin == 0)) {
207 // See the data sheet: we ignore the output pin cycle...
208 if (channel_cycles > 0) {
213 ch->output_pin = (ch->output_pin + 1) % 2;
215 if (ch->output_pin == 1) {
222 if (channel_cycles > 0) {
223 if (ch->output_pin == 1) {
230 PrintError("Hardware strobe not implemented\n");
237 return output_changed;
241 #include <palacios/vm_guest.h>
243 static void pit_update_timer(struct guest_info * info, ullong_t cpu_cycles, ullong_t cpu_freq, void * private_data) {
244 struct pit * state = (struct pit *)private_data;
245 // ullong_t tmp_ctr = state->pit_counter;
247 uint_t oscillations = 0;
251 PrintDebug("updating cpu_cycles=");
252 PrintTraceLL(cpu_cycles);
255 PrintDebug("pit_counter=");
256 PrintTraceLL(state->pit_counter);
259 PrintDebug("pit_reload=");
260 PrintTraceLL(state->pit_reload);
264 if (state->pit_counter > cpu_cycles) {
266 state->pit_counter -= cpu_cycles;
268 ushort_t reload_val = state->pit_reload;
269 // Take off the first part
270 cpu_cycles -= state->pit_counter;
271 state->pit_counter = 0;
274 if (cpu_cycles > state->pit_reload) {
275 // how many full oscillations
277 //PrintError("cpu_cycles = %p, reload = %p...\n",
278 // (void *)(addr_t)cpu_cycles,
279 // (void *)(addr_t)state->pit_reload);
281 // How do we check for a one shot....
282 if (state->pit_reload == 0) {
286 tmp_cycles = cpu_cycles;
290 cpu_cycles = tmp_cycles % state->pit_reload;
291 tmp_cycles = tmp_cycles / state->pit_reload;
293 cpu_cycles = do_divll(tmp_cycles, state->pit_reload);
296 oscillations += tmp_cycles;
299 // update counter with remainder (mod reload)
300 state->pit_counter = state->pit_reload - cpu_cycles;
303 PrintDebug("8254 PIT: Handling %d crystal tics\n", oscillations);
306 if (handle_crystal_tics(state, &(state->ch_0), oscillations) == 1) {
308 // PrintDebug("8254 PIT: Injecting Timer interrupt to guest\n");
309 v3_raise_irq(info->vm_info, 0);
312 //handle_crystal_tics(state, &(state->ch_1), oscillations);
313 handle_crystal_tics(state, &(state->ch_2), oscillations);
322 /* This should call out to handle_SQR_WAVE_write, etc...
324 static int handle_channel_write(struct channel * ch, char val) {
326 switch (ch->access_state) {
329 ushort_t tmp_val = ((ushort_t)val) << 8;
330 ch->reload_value &= 0x00ff;
331 ch->reload_value |= tmp_val;
334 if ((ch->op_mode != RATE_GEN) || (ch->run_state != RUNNING)){
335 ch->run_state = PENDING;
338 if (ch->access_mode == LOBYTE_HIBYTE) {
339 ch->access_state = WAITING_LOBYTE;
342 PrintDebug("8254 PIT: updated channel counter: %d\n", ch->reload_value);
343 PrintDebug("8254 PIT: Channel Run State=%d\n", ch->run_state);
347 ch->reload_value &= 0xff00;
348 ch->reload_value |= val;
350 if (ch->access_mode == LOBYTE_HIBYTE) {
351 ch->access_state = WAITING_HIBYTE;
352 } else if ((ch->op_mode != RATE_GEN) || (ch->run_state != RUNNING)) {
353 ch->run_state = PENDING;
356 PrintDebug("8254 PIT: updated channel counter: %d\n", ch->reload_value);
357 PrintDebug("8254 PIT: Channel Run State=%d\n", ch->run_state);
360 PrintError("Invalid Access state\n");
365 switch (ch->op_mode) {
366 case IRQ_ON_TERM_CNT:
382 PrintError("Invalid OP_MODE: %d\n", ch->op_mode);
392 static int handle_channel_read(struct channel * ch, char * val) {
396 if (ch->latch_state == NOTLATCHED) {
397 myval = &(ch->counter);
399 myval = &(ch->latched_value);
402 if (ch->read_state == LSB) {
403 *val = ((char*)myval)[0]; // little endian
404 ch->read_state = MSB;
406 *val = ((char*)myval)[1];
407 ch->read_state = LSB;
408 if (ch->latch_state == LATCHED) {
409 ch->latch_state = NOTLATCHED;
417 static int handle_speaker_read(uint8_t *speaker, struct channel * ch, char * val) {
420 if ((*speaker & PIT_SPEAKER_GATE)) {
421 *val |= (ch->output_pin << 5);
427 static int handle_speaker_write(uint8_t *speaker, struct channel * ch, char val) {
428 *speaker = (val & ~0x20);
432 static int handle_channel_cmd(struct channel * ch, struct pit_cmd_word cmd) {
434 ch->access_mode = cmd.access_mode;
436 if (ch->access_mode != 0) {
437 ch->op_mode = cmd.op_mode;
441 switch (cmd.access_mode) {
443 if (ch->latch_state == NOTLATCHED) {
444 ch->latched_value = ch->counter;
445 ch->latch_state = LATCHED;
449 ch->access_state = WAITING_HIBYTE;
453 ch->access_state = WAITING_LOBYTE;
458 switch (cmd.op_mode) {
459 case IRQ_ON_TERM_CNT:
475 PrintError("Invalid OP_MODE: %d\n", cmd.op_mode);
486 static int pit_read_channel(struct guest_info * core, ushort_t port, void * dst, uint_t length, void * priv_data) {
487 struct pit * state = (struct pit *)priv_data;
488 char * val = (char *)dst;
491 PrintError("8254 PIT: Invalid Read Write length \n");
495 PrintDebug("8254 PIT: Read of PIT Channel %d\n", port - CHANNEL0_PORT);
499 if (handle_channel_read(&(state->ch_0), val) == -1) {
500 PrintError("CHANNEL0 read error\n");
505 if (handle_channel_read(&(state->ch_1), val) == -1) {
506 PrintError("CHANNEL1 read error\n");
511 if (handle_channel_read(&(state->ch_2), val) == -1) {
512 PrintError("CHANNEL2 read error\n");
517 if (handle_speaker_read(&state->speaker, &(state->ch_2), val) == -1) {
518 PrintError("SPEAKER read error\n");
523 PrintError("8254 PIT: Read from invalid port (%d)\n", port);
532 static int pit_write_channel(struct guest_info * core, ushort_t port, void * src, uint_t length, void * priv_data) {
533 struct pit * state = (struct pit *)priv_data;
534 char val = *(char *)src;
537 PrintError("8254 PIT: Invalid Write Length\n");
541 PrintDebug("8254 PIT: Write to PIT Channel %d (%x)\n", port - CHANNEL0_PORT, *(char*)src);
546 if (handle_channel_write(&(state->ch_0), val) == -1) {
547 PrintError("CHANNEL0 write error\n");
552 if (handle_channel_write(&(state->ch_1), val) == -1) {
553 PrintError("CHANNEL1 write error\n");
558 if (handle_channel_write(&(state->ch_2), val) == -1) {
559 PrintError("CHANNEL2 write error\n");
564 if (handle_speaker_write(&state->speaker, &(state->ch_2), val) == -1) {
565 PrintError("SPEAKER write error\n");
570 PrintError("8254 PIT: Write to invalid port (%d)\n", port);
580 static int pit_write_command(struct guest_info * core, ushort_t port, void * src, uint_t length, void * priv_data) {
581 struct pit * state = (struct pit *)priv_data;
582 struct pit_cmd_word * cmd = (struct pit_cmd_word *)src;
584 PrintDebug("8254 PIT: Write to PIT Command port\n");
585 PrintDebug("8254 PIT: Writing to channel %d (access_mode = %d, op_mode = %d)\n", cmd->channel, cmd->access_mode, cmd->op_mode);
587 PrintError("8254 PIT: Write of Invalid length to command port\n");
591 switch (cmd->channel) {
593 if (handle_channel_cmd(&(state->ch_0), *cmd) == -1) {
594 PrintError("CHANNEL0 command error\n");
599 if (handle_channel_cmd(&(state->ch_1), *cmd) == -1) {
600 PrintError("CHANNEL1 command error\n");
605 if (handle_channel_cmd(&(state->ch_2), *cmd) == -1) {
606 PrintError("CHANNEL2 command error\n");
612 PrintError("Read back command not implemented\n");
626 static struct v3_timer_ops timer_ops = {
627 .update_timer = pit_update_timer,
631 static void init_channel(struct channel * ch) {
632 ch->run_state = NOT_RUNNING;
633 ch->access_state = NOT_WAITING;
638 ch->reload_value = 0;
640 ch->gate_input_pin = 0;
642 ch->latched_value = 0;
643 ch->latch_state = NOTLATCHED;
644 ch->read_state = LSB;
652 static int pit_free(void * private_data) {
653 struct pit * state = (struct pit *)private_data;
654 struct guest_info * info = &(state->vm->cores[0]);
658 v3_remove_timer(info, state->timer);
665 #ifdef V3_CONFIG_KEYED_STREAMS
666 static int pit_checkpoint(struct vm_device *dev, v3_keyed_stream_t stream)
668 struct pit *p = (struct pit *) (dev->private_data);
670 v3_keyed_stream_key_t ks;
672 ks = v3_keyed_stream_open_key(stream,dev->name);
678 STD_SAVE(stream,ks,p->pit_counter);
679 STD_SAVE(stream,ks,p->pit_reload);
680 STD_SAVE(stream,ks,p->ch_0);
681 STD_SAVE(stream,ks,p->ch_1);
682 STD_SAVE(stream,ks,p->ch_2);
683 STD_SAVE(stream,ks,p->speaker);
685 v3_keyed_stream_close_key(stream,ks);
692 static int pit_restore(struct vm_device *dev, v3_keyed_stream_t stream)
694 struct pit *p = (struct pit *) (dev->private_data);
696 v3_keyed_stream_key_t ks;
698 ks = v3_keyed_stream_open_key(stream,dev->name);
704 STD_LOAD(stream,ks,p->pit_counter);
705 STD_LOAD(stream,ks,p->pit_reload);
706 STD_LOAD(stream,ks,p->ch_0);
707 STD_LOAD(stream,ks,p->ch_1);
708 STD_LOAD(stream,ks,p->ch_2);
709 STD_LOAD(stream,ks,p->speaker);
711 v3_keyed_stream_close_key(stream,ks);
719 static struct v3_device_ops dev_ops = {
720 .free = (int (*)(void *))pit_free,
721 #ifdef V3_CONFIG_KEYED_STREAMS
722 .checkpoint = pit_checkpoint,
723 .restore = pit_restore,
727 #include <palacios/vm_guest.h>
729 static int pit_init(struct v3_vm_info * vm, v3_cfg_tree_t * cfg) {
730 struct pit * pit_state = NULL;
731 struct vm_device * dev = NULL;
732 char * dev_id = v3_cfg_val(cfg, "ID");
735 // PIT is only usable in non-multicore environments
736 // just hardcode the core context
737 struct guest_info * info = &(vm->cores[0]);
739 uint_t cpu_khz = info->time_state.guest_cpu_freq;
740 ullong_t reload_val = (ullong_t)cpu_khz * 1000;
742 pit_state = (struct pit *)V3_Malloc(sizeof(struct pit));
744 V3_ASSERT(pit_state != NULL);
745 pit_state->speaker = 0;
748 dev = v3_add_device(vm, dev_id, &dev_ops, pit_state);
751 PrintError("Could not attach device %s\n", dev_id);
756 ret |= v3_dev_hook_io(dev, CHANNEL0_PORT, &pit_read_channel, &pit_write_channel);
757 ret |= v3_dev_hook_io(dev, CHANNEL1_PORT, &pit_read_channel, &pit_write_channel);
758 ret |= v3_dev_hook_io(dev, CHANNEL2_PORT, &pit_read_channel, &pit_write_channel);
759 ret |= v3_dev_hook_io(dev, COMMAND_PORT, NULL, &pit_write_command);
760 ret |= v3_dev_hook_io(dev, SPEAKER_PORT, &pit_read_channel, &pit_write_channel);
763 PrintError("8254 PIT: Failed to hook IO ports\n");
764 v3_remove_device(dev);
768 #ifdef V3_CONFIG_DEBUG_PIT
769 PrintDebug("8254 PIT: OSC_HZ=%d, reload_val=", OSC_HZ);
770 //PrintTrace(reload_val);
776 pit_state->timer = v3_add_timer(info, &timer_ops, pit_state);
778 if (pit_state->timer == NULL) {
779 v3_remove_device(dev);
783 // Get cpu frequency and calculate the global pit oscilattor counter/cycle
785 do_divll(reload_val, OSC_HZ);
786 pit_state->pit_counter = reload_val;
787 pit_state->pit_reload = reload_val;
790 init_channel(&(pit_state->ch_0));
791 init_channel(&(pit_state->ch_1));
792 init_channel(&(pit_state->ch_2));
794 #ifdef V3_CONFIG_DEBUG_PIT
795 PrintDebug("8254 PIT: CPU MHZ=%d -- pit count=", cpu_khz / 1000);
796 //PrintTraceLL(pit_state->pit_counter);
804 device_register("8254_PIT", pit_init);