2 * This file is part of the Palacios Virtual Machine Monitor developed
3 * by the V3VEE Project with funding from the United States National
4 * Science Foundation and the Department of Energy.
6 * The V3VEE Project is a joint project between Northwestern University
7 * and the University of New Mexico. You can find out more at
10 * Copyright (c) 2008, Jack Lange <jarusl@cs.northwestern.edu>
11 * Copyright (c) 2008, The V3VEE Project <http://www.v3vee.org>
12 * All rights reserved.
14 * Author: Jack Lange <jarusl@cs.northwestern.edu>
16 * This is free software. You are permitted to use,
17 * redistribute, and modify it as specified in the file "V3VEE_LICENSE".
21 #include <palacios/vmm.h>
22 #include <palacios/vmm_dev_mgr.h>
23 #include <palacios/vmm_time.h>
24 #include <palacios/vmm_util.h>
25 #include <palacios/vmm_intr.h>
26 #include <palacios/vmm_config.h>
29 #ifndef CONFIG_DEBUG_PIT
31 #define PrintDebug(fmt, args...)
37 #define OSC_HZ 1193182
40 /* The 8254 has three counters and one control port */
41 #define CHANNEL0_PORT 0x40
42 #define CHANNEL1_PORT 0x41
43 #define CHANNEL2_PORT 0x42
44 #define COMMAND_PORT 0x43
47 #define PIT_INTR_NUM 0
49 /* The order of these typedefs is important because the numerical values correspond to the
50 * values coming from the io ports
52 typedef enum {NOT_RUNNING, PENDING, RUNNING} channel_run_state_t;
53 typedef enum {NOT_WAITING, WAITING_LOBYTE, WAITING_HIBYTE} channel_access_state_t;
54 typedef enum {LATCH_COUNT, LOBYTE_ONLY, HIBYTE_ONLY, LOBYTE_HIBYTE} channel_access_mode_t;
55 typedef enum {IRQ_ON_TERM_CNT, ONE_SHOT, RATE_GEN, SQR_WAVE, SW_STROBE, HW_STROBE} channel_op_mode_t;
59 channel_access_mode_t access_mode;
60 channel_access_state_t access_state;
61 channel_run_state_t run_state;
63 channel_op_mode_t op_mode;
66 // Time til interrupt trigger
69 ushort_t reload_value;
71 ushort_t latched_value;
73 enum {NOTLATCHED, LATCHED} latch_state;
75 enum {LSB, MSB} read_state;
77 uint_t output_pin : 1;
78 uint_t gate_input_pin : 1;
97 uint_t access_mode : 2;
101 struct pit_rdb_cmd_word {
102 uint_t rsvd : 1; // SBZ
106 uint_t latch_status : 1;
107 uint_t latch_count : 1;
108 uint_t readback_cmd : 2; // Must Be 0x3
111 struct pit_rdb_status_word {
114 uint_t access_mode : 2;
115 uint_t null_count : 1;
116 uint_t pin_state : 1;
122 * This should call out to handle_SQR_WAVE_tics, etc...
124 // Returns true if the the output signal changed state
125 static int handle_crystal_tics(struct vm_device * dev, struct channel * ch, uint_t oscillations) {
126 uint_t channel_cycles = 0;
127 uint_t output_changed = 0;
129 // PrintDebug("8254 PIT: %d crystal tics\n", oscillations);
130 if (ch->run_state == PENDING) {
132 ch->counter = ch->reload_value;
134 if (ch->op_mode == SQR_WAVE) {
135 ch->counter -= ch->counter % 2;
138 ch->run_state = RUNNING;
139 } else if (ch->run_state != RUNNING) {
140 return output_changed;
144 PrintDebug("8254 PIT: Channel Run State = %d, counter=", ch->run_state);
145 PrintTraceLL(ch->counter);
148 if (ch->op_mode == SQR_WAVE) {
152 if (ch->counter > oscillations) {
153 ch->counter -= oscillations;
154 return output_changed;
156 ushort_t reload_val = ch->reload_value;
158 if (ch->op_mode == SW_STROBE) {
162 // TODO: Check this....
163 // Is this correct???
164 if (reload_val == 0) {
168 oscillations -= ch->counter;
172 if (ch->op_mode == SQR_WAVE) {
173 reload_val -= reload_val % 2;
176 channel_cycles += oscillations / reload_val;
177 oscillations = oscillations % reload_val;
179 ch->counter = reload_val - oscillations;
182 // PrintDebug("8254 PIT: Channel Cycles: %d\n", channel_cycles);
186 switch (ch->op_mode) {
187 case IRQ_ON_TERM_CNT:
188 if ((channel_cycles > 0) && (ch->output_pin == 0)) {
194 if ((channel_cycles > 0) && (ch->output_pin == 0)) {
200 // See the data sheet: we ignore the output pin cycle...
201 if (channel_cycles > 0) {
206 ch->output_pin = (ch->output_pin + 1) % 2;
208 if (ch->output_pin == 1) {
215 if (channel_cycles > 0) {
216 if (ch->output_pin == 1) {
223 PrintError("Hardware strobe not implemented\n");
230 return output_changed;
234 #include <palacios/vm_guest.h>
236 static void pit_update_time(struct guest_info * info, ullong_t cpu_cycles, ullong_t cpu_freq, void * private_data) {
237 struct vm_device * dev = (struct vm_device *)private_data;
238 struct pit * state = (struct pit *)dev->private_data;
239 // ullong_t tmp_ctr = state->pit_counter;
241 uint_t oscillations = 0;
245 PrintDebug("updating cpu_cycles=");
246 PrintTraceLL(cpu_cycles);
249 PrintDebug("pit_counter=");
250 PrintTraceLL(state->pit_counter);
253 PrintDebug("pit_reload=");
254 PrintTraceLL(state->pit_reload);
258 if (state->pit_counter > cpu_cycles) {
260 state->pit_counter -= cpu_cycles;
262 ushort_t reload_val = state->pit_reload;
263 // Take off the first part
264 cpu_cycles -= state->pit_counter;
265 state->pit_counter = 0;
268 if (cpu_cycles > state->pit_reload) {
269 // how many full oscillations
271 //PrintError("cpu_cycles = %p, reload = %p...\n",
272 // (void *)(addr_t)cpu_cycles,
273 // (void *)(addr_t)state->pit_reload);
275 // How do we check for a one shot....
276 if (state->pit_reload == 0) {
280 tmp_cycles = cpu_cycles;
284 cpu_cycles = tmp_cycles % state->pit_reload;
285 tmp_cycles = tmp_cycles / state->pit_reload;
287 cpu_cycles = do_divll(tmp_cycles, state->pit_reload);
290 oscillations += tmp_cycles;
293 // update counter with remainder (mod reload)
294 state->pit_counter = state->pit_reload - cpu_cycles;
296 //PrintDebug("8254 PIT: Handling %d crystal tics\n", oscillations);
297 if (handle_crystal_tics(dev, &(state->ch_0), oscillations) == 1) {
299 PrintDebug("8254 PIT: Injecting Timer interrupt to guest\n");
300 v3_raise_irq(info->vm_info, 0);
303 //handle_crystal_tics(dev, &(state->ch_1), oscillations);
304 //handle_crystal_tics(dev, &(state->ch_2), oscillations);
314 static void pit_advance_time(struct guest_info * core, void * private_data) {
316 v3_raise_irq(core->vm_info, 0);
321 /* This should call out to handle_SQR_WAVE_write, etc...
323 static int handle_channel_write(struct channel * ch, char val) {
325 switch (ch->access_state) {
328 ushort_t tmp_val = ((ushort_t)val) << 8;
329 ch->reload_value &= 0x00ff;
330 ch->reload_value |= tmp_val;
333 if ((ch->op_mode != RATE_GEN) || (ch->run_state != RUNNING)){
334 ch->run_state = PENDING;
337 if (ch->access_mode == LOBYTE_HIBYTE) {
338 ch->access_state = WAITING_LOBYTE;
341 PrintDebug("8254 PIT: updated channel counter: %d\n", ch->reload_value);
342 PrintDebug("8254 PIT: Channel Run State=%d\n", ch->run_state);
346 ch->reload_value &= 0xff00;
347 ch->reload_value |= val;
349 if (ch->access_mode == LOBYTE_HIBYTE) {
350 ch->access_state = WAITING_HIBYTE;
351 } else if ((ch->op_mode != RATE_GEN) || (ch->run_state != RUNNING)) {
352 ch->run_state = PENDING;
355 PrintDebug("8254 PIT: updated channel counter: %d\n", ch->reload_value);
356 PrintDebug("8254 PIT: Channel Run State=%d\n", ch->run_state);
359 PrintError("Invalid Access state\n");
364 switch (ch->op_mode) {
365 case IRQ_ON_TERM_CNT:
381 PrintError("Invalid OP_MODE: %d\n", ch->op_mode);
391 static int handle_channel_read(struct channel * ch, char * val) {
395 if (ch->latch_state == NOTLATCHED) {
396 myval = &(ch->counter);
398 myval = &(ch->latched_value);
401 if (ch->read_state == LSB) {
402 *val = ((char*)myval)[0]; // little endian
403 ch->read_state = MSB;
405 *val = ((char*)myval)[1];
406 ch->read_state = LSB;
407 if (ch->latch_state == LATCHED) {
408 ch->latch_state = NOTLATCHED;
420 static int handle_channel_cmd(struct channel * ch, struct pit_cmd_word cmd) {
421 ch->op_mode = cmd.op_mode;
422 ch->access_mode = cmd.access_mode;
427 switch (cmd.access_mode) {
429 if (ch->latch_state == NOTLATCHED) {
430 ch->latched_value = ch->counter;
431 ch->latch_state = LATCHED;
435 ch->access_state = WAITING_HIBYTE;
439 ch->access_state = WAITING_LOBYTE;
444 switch (cmd.op_mode) {
445 case IRQ_ON_TERM_CNT:
461 PrintError("Invalid OP_MODE: %d\n", cmd.op_mode);
472 static int pit_read_channel(struct guest_info * core, ushort_t port, void * dst, uint_t length, struct vm_device * dev) {
473 struct pit * state = (struct pit *)dev->private_data;
474 char * val = (char *)dst;
477 PrintError("8254 PIT: Invalid Read Write length \n");
481 PrintDebug("8254 PIT: Read of PIT Channel %d\n", port - CHANNEL0_PORT);
485 if (handle_channel_read(&(state->ch_0), val) == -1) {
486 PrintError("CHANNEL0 read error\n");
491 if (handle_channel_read(&(state->ch_1), val) == -1) {
492 PrintError("CHANNEL1 read error\n");
497 if (handle_channel_read(&(state->ch_2), val) == -1) {
498 PrintError("CHANNEL2 read error\n");
503 PrintError("8254 PIT: Read from invalid port (%d)\n", port);
512 static int pit_write_channel(struct guest_info * core, ushort_t port, void * src, uint_t length, struct vm_device * dev) {
513 struct pit * state = (struct pit *)dev->private_data;
514 char val = *(char *)src;
517 PrintError("8254 PIT: Invalid Write Length\n");
521 PrintDebug("8254 PIT: Write to PIT Channel %d (%x)\n", port - CHANNEL0_PORT, *(char*)src);
526 if (handle_channel_write(&(state->ch_0), val) == -1) {
527 PrintError("CHANNEL0 write error\n");
532 if (handle_channel_write(&(state->ch_1), val) == -1) {
533 PrintError("CHANNEL1 write error\n");
538 if (handle_channel_write(&(state->ch_2), val) == -1) {
539 PrintError("CHANNEL2 write error\n");
544 PrintError("8254 PIT: Write to invalid port (%d)\n", port);
554 static int pit_write_command(struct guest_info * core, ushort_t port, void * src, uint_t length, struct vm_device * dev) {
555 struct pit * state = (struct pit *)dev->private_data;
556 struct pit_cmd_word * cmd = (struct pit_cmd_word *)src;
558 PrintDebug("8254 PIT: Write to PIT Command port\n");
559 PrintDebug("8254 PIT: Writing to channel %d (access_mode = %d, op_mode = %d)\n", cmd->channel, cmd->access_mode, cmd->op_mode);
561 PrintError("8254 PIT: Write of Invalid length to command port\n");
565 switch (cmd->channel) {
567 if (handle_channel_cmd(&(state->ch_0), *cmd) == -1) {
568 PrintError("CHANNEL0 command error\n");
573 if (handle_channel_cmd(&(state->ch_1), *cmd) == -1) {
574 PrintError("CHANNEL1 command error\n");
579 if (handle_channel_cmd(&(state->ch_2), *cmd) == -1) {
580 PrintError("CHANNEL2 command error\n");
586 PrintError("Read back command not implemented\n");
600 static struct vm_timer_ops timer_ops = {
601 .update_time = pit_update_time,
602 .advance_timer = pit_advance_time,
606 static void init_channel(struct channel * ch) {
607 ch->run_state = NOT_RUNNING;
608 ch->access_state = NOT_WAITING;
613 ch->reload_value = 0;
615 ch->gate_input_pin = 0;
617 ch->latched_value = 0;
618 ch->latch_state = NOTLATCHED;
619 ch->read_state = LSB;
627 static int pit_free(struct vm_device * dev) {
633 static struct v3_device_ops dev_ops = {
641 #include <palacios/vm_guest.h>
643 static int pit_init(struct v3_vm_info * vm, v3_cfg_tree_t * cfg) {
644 struct pit * pit_state = NULL;
645 struct vm_device * dev = NULL;
646 char * name = v3_cfg_val(cfg, "name");
648 // PIT is only usable in non-multicore environments
649 // just hardcode the core context
650 struct guest_info * info = &(vm->cores[0]);
652 uint_t cpu_khz = V3_CPU_KHZ();
653 ullong_t reload_val = (ullong_t)cpu_khz * 1000;
655 pit_state = (struct pit *)V3_Malloc(sizeof(struct pit));
656 V3_ASSERT(pit_state != NULL);
658 dev = v3_allocate_device(name, &dev_ops, pit_state);
660 if (v3_attach_device(vm, dev) == -1) {
661 PrintError("Could not attach device %s\n", name);
665 v3_dev_hook_io(dev, CHANNEL0_PORT, &pit_read_channel, &pit_write_channel);
666 v3_dev_hook_io(dev, CHANNEL1_PORT, &pit_read_channel, &pit_write_channel);
667 v3_dev_hook_io(dev, CHANNEL2_PORT, &pit_read_channel, &pit_write_channel);
668 v3_dev_hook_io(dev, COMMAND_PORT, NULL, &pit_write_command);
670 #ifdef CONFIG_DEBUG_PIT
671 PrintDebug("8254 PIT: OSC_HZ=%d, reload_val=", OSC_HZ);
672 PrintTraceLL(reload_val);
677 v3_add_timer(info, &timer_ops, dev);
679 // Get cpu frequency and calculate the global pit oscilattor counter/cycle
681 do_divll(reload_val, OSC_HZ);
682 pit_state->pit_counter = reload_val;
683 pit_state->pit_reload = reload_val;
687 init_channel(&(pit_state->ch_0));
688 init_channel(&(pit_state->ch_1));
689 init_channel(&(pit_state->ch_2));
691 #ifdef CONFIG_DEBUG_PIT
692 PrintDebug("8254 PIT: CPU MHZ=%d -- pit count=", cpu_khz / 1000);
693 PrintTraceLL(pit_state->pit_counter);
701 device_register("8254_PIT", pit_init);